From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65D372DC32B; Fri, 19 Dec 2025 17:40:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166059; cv=none; b=OGxIEHsOjy+iKkMejO/XYr3KieSm3ibG3Q5QGTXuq8QG5BQhQDMPkT6osx2C3tWT0yRMo2bDizLOfXrxoKo7AtXJHq+V85u1riZ44ypStkrd55+xvG4jQvnJ3+jwME+9AkY/WVnzzRjuGSYABvIRVLUfsMhJYyaXZTamj6FKOz4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166059; c=relaxed/simple; bh=6k6XnSLCX0J/usKJONUDwI7bCA9yVh1g+rcsjInq7KI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=LH032ePjp+PS9MHgEhJoJ2NUTWAwzt39U3j8j3c7EDvoGyrr191lzClHNs4JYl4YTtZT6nBFua1YQT7zgu78G4z2E+U1qA5iT4MH37GwSUnZEIOJw6YdNX1qVeZ7uxWhiqbH4isTlSq8qNPSq8WTXcGWu/xwM4K94ex9482RWbc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kXQtDNM7; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kXQtDNM7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1766166057; x=1797702057; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6k6XnSLCX0J/usKJONUDwI7bCA9yVh1g+rcsjInq7KI=; b=kXQtDNM7SiQa7+zMkMG+FE89qevGlN8ctePhltiE0roO7p+cfwpLXTna QPOHeJ8A6xUJfqPx6wk/2aZogvhTAQM4Zoow92JqBghkCoVLVPHx4JJoa FMIe1qadleMFASiVwm1tBEhZSvsvFrjoPh49leZnjunJYTquGEGCMu2hi VRqVEFEVEQhxwVMI2RVggI1eC6495EtOGZwRqBN71r/FAO2fObYEcyd2F uupZfE8Ruytdz2iiFFj+QMN7pAmnokMT0wPSICiltcRJrmejfvRkmhK1f iQTQbvZk6u8ZvV+UCU4b9dOEGCYQOhdj5+E/bab6dnUa7YObjcFSEbtcr w==; X-CSE-ConnectionGUID: 6jMljgSiRbyMOtJixyzisw== X-CSE-MsgGUID: Dl0SJl1VTseSzyjFifU6Nw== X-IronPort-AV: E=McAfee;i="6800,10657,11647"; a="68173769" X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="68173769" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:40:55 -0800 X-CSE-ConnectionGUID: mzIiNWYsQvayGFFC1KzCdw== X-CSE-MsgGUID: 5jGnh02wR+Ou6ciWVrBFbA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="198974779" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:40:51 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , Benjamin Herrenschmidt , Wei Yang , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , =?UTF-8?q?Malte=20Schr=C3=B6der?= , stable@vger.kernel.org Subject: [PATCH 01/23] PCI: Fix bridge window alignment with optional resources Date: Fri, 19 Dec 2025 19:40:14 +0200 Message-Id: <20251219174036.16738-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable pbus_size_mem() has two alignments, one for required resources in min_align and another in add_align that takes account optional resources. The add_align is applied to the bridge window through the realloc_head list. It can happen, however, that add_align is larger than min_align but calculated size1 and size0 are equal due to extra tailroom (e.g., hotplug reservation, tail alignment), and therefore no entry is created to the realloc_head list. Without the bridge appearing in the realloc head, add_align is lost when pbus_size_mem() returns. The problem is visible in this log for 0000:05:00.0 which lacks add_size ... add_align ... line that would indicate it was added into the realloc_head list: pci 0000:05:00.0: PCI bridge to [bus 06-16] ... pci 0000:06:00.0: bridge window [mem 0x00100000-0x001fffff] to [bus 07] req= uires relaxed alignment rules pci 0000:06:06.0: bridge window [mem 0x00100000-0x001fffff] to [bus 0a] req= uires relaxed alignment rules pci 0000:06:07.0: bridge window [mem 0x00100000-0x003fffff] to [bus 0b] req= uires relaxed alignment rules pci 0000:06:08.0: bridge window [mem 0x00800000-0x00ffffff 64bit pref] to [= bus 0c-14] requires relaxed alignment rules pci 0000:06:08.0: bridge window [mem 0x01000000-0x057fffff] to [bus 0c-14] = requires relaxed alignment rules pci 0000:06:08.0: bridge window [mem 0x01000000-0x057fffff] to [bus 0c-14] = requires relaxed alignment rules pci 0000:06:08.0: bridge window [mem 0x01000000-0x057fffff] to [bus 0c-14] = add_size 100000 add_align 1000000 pci 0000:06:0c.0: bridge window [mem 0x00100000-0x001fffff] to [bus 15] req= uires relaxed alignment rules pci 0000:06:0d.0: bridge window [mem 0x00100000-0x001fffff] to [bus 16] req= uires relaxed alignment rules pci 0000:06:0d.0: bridge window [mem 0x00100000-0x001fffff] to [bus 16] req= uires relaxed alignment rules pci 0000:05:00.0: bridge window [mem 0xd4800000-0xd97fffff]: assigned pci 0000:05:00.0: bridge window [mem 0x1060000000-0x10607fffff 64bit pref]:= assigned pci 0000:06:08.0: bridge window [mem size 0x04900000]: can't assign; no spa= ce pci 0000:06:08.0: bridge window [mem size 0x04900000]: failed to assign While this bug itself seems old, it has likely become more visible after the relaxed tail alignment that does not grossly overestimate the size needed for the bridge window. Make sure add_align > min_align too results in adding an entry into the realloc head list. In addition, add handling to the cases where add_size is zero while only alignment differs. Fixes: d74b9027a4da ("PCI: Consider additional PF's IOV BAR alignment in si= zing and assigning") Reported-by: Malte Schr=C3=B6der Tested-by: Malte Schr=C3=B6der Signed-off-by: Ilpo J=C3=A4rvinen Cc: stable@vger.kernel.org --- drivers/pci/setup-bus.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 6e90f46f52af..4b918ff4d2d8 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -14,6 +14,7 @@ * tighter packing. Prefetchable range support. */ =20 +#include #include #include #include @@ -456,7 +457,7 @@ static void reassign_resources_sorted(struct list_head = *realloc_head, "%s %pR: ignoring failure in optional allocation\n", res_name, res); } - } else if (add_size > 0) { + } else if (add_size > 0 || !IS_ALIGNED(res->start, align)) { res->flags |=3D add_res->flags & (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); if (pci_reassign_resource(dev, idx, add_size, align)) @@ -1442,12 +1443,13 @@ static void pbus_size_mem(struct pci_bus *bus, unsi= gned long type, =20 resource_set_range(b_res, min_align, size0); b_res->flags |=3D IORESOURCE_STARTALIGN; - if (bus->self && size1 > size0 && realloc_head) { + if (bus->self && realloc_head && (size1 > size0 || add_align > min_align)= ) { b_res->flags &=3D ~IORESOURCE_DISABLED; - add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); + add_size =3D size1 > size0 ? size1 - size0 : 0; + add_to_list(realloc_head, bus->self, b_res, add_size, add_align); pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %l= lx\n", b_res, &bus->busn_res, - (unsigned long long) (size1 - size0), + (unsigned long long) add_size, (unsigned long long) add_align); } } --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C74482F7AB0; Fri, 19 Dec 2025 17:41:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166065; cv=none; b=XI0i5OAn/U6YPXaRrA/cwZuLW3SDoo7yNVf3wKiDYCp8ejNrDUtgeSC8l3b6/TKmAuikzLm0cmM/kvWZXDsN3IwT9/HU5XWvtSO2kuJ26cybk6QptJo2MRtMqOcZQ80OZHLNh032QBEpH58QUjIAI1WdJFBgQ7Uo11U/TgDfSRQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166065; c=relaxed/simple; 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d="scan'208";a="198974810" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:41:00 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , =?UTF-8?q?Malte=20Schr=C3=B6der?= , stable@vger.kernel.org Subject: [PATCH 02/23] PCI: Rewrite bridge window head alignment function Date: Fri, 19 Dec 2025 19:40:15 +0200 Message-Id: <20251219174036.16738-3-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The calculation of bridge window head alignment is done by calculate_mem_align() [*]. With the default bridge window alignment, it is used for both head and tail alignment. The selected head alignment does not always result in tight-fitting resources (gap at d4f00000-d4ffffff): d4800000-dbffffff : PCI Bus 0000:06 d4800000-d48fffff : PCI Bus 0000:07 d4800000-d4803fff : 0000:07:00.0 d4800000-d4803fff : nvme d4900000-d49fffff : PCI Bus 0000:0a d4900000-d490ffff : 0000:0a:00.0 d4900000-d490ffff : r8169 d4910000-d4913fff : 0000:0a:00.0 d4a00000-d4cfffff : PCI Bus 0000:0b d4a00000-d4bfffff : 0000:0b:00.0 d4a00000-d4bfffff : 0000:0b:00.0 d4c00000-d4c07fff : 0000:0b:00.0 d4d00000-d4dfffff : PCI Bus 0000:15 d4d00000-d4d07fff : 0000:15:00.0 d4d00000-d4d07fff : xhci-hcd d4e00000-d4efffff : PCI Bus 0000:16 d4e00000-d4e7ffff : 0000:16:00.0 d4e80000-d4e803ff : 0000:16:00.0 d4e80000-d4e803ff : ahci d5000000-dbffffff : PCI Bus 0000:0c This has not been caused problems (for years) with the default bridge window tail alignment that grossly over-estimates the required tail alignment leaving more tail room than necessary. With the introduction of relaxed tail alignment that leaves no extra tail room whatsoever, any gaps will immediately turn into assignment failures. Introduce head alignment calculation that ensures no gaps are left and apply the new approach when using relaxed alignment. We may want to consider using it for the normal alignment eventually, but as the first step, solve only the problem with the relaxed tail alignment. ([*] I don't understand the algorithm in calculate_mem_align().) Fixes: 5d0a8965aea9 ("[PATCH] 2.5.14: New PCI allocation code (alpha, arm, = parisc) [2/2]") Closes: https://bugzilla.kernel.org/show_bug.cgi?id=3D220775 Reported-by: Malte Schr=C3=B6der Tested-by: Malte Schr=C3=B6der Signed-off-by: Ilpo J=C3=A4rvinen Cc: stable@vger.kernel.org --- Little annoyingly, there's difference in what aligns array contains between the legacy alignment approach (which I dare not to touch as I really don't understand what the algorithm tries to do) and this new head aligment algorithm, both consuming stack space. After making the new approach the only available approach in the follow-up patch, only one array remains (however, that follow-up change is also somewhat riskier when it comes to regressions). That being said, the new head alignment could work with the same aligns array as the legacy approach, it just won't necessarily produce an optimal (the smallest possible) head alignment when if (r_size <=3D align) condition is used. Just let me know if that approach is preferred (to save some stack space). --- drivers/pci/setup-bus.c | 53 ++++++++++++++++++++++++++++++++++------- 1 file changed, 44 insertions(+), 9 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 4b918ff4d2d8..80e5a8fc62e7 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1228,6 +1228,45 @@ static inline resource_size_t calculate_mem_align(re= source_size_t *aligns, return min_align; } =20 +/* + * Calculate bridge window head alignment that leaves no gaps in between + * resources. + */ +static resource_size_t calculate_head_align(resource_size_t *aligns, + int max_order) +{ + resource_size_t head_align =3D 1; + resource_size_t remainder =3D 0; + int order; + + /* Take the largest alignment as the starting point. */ + head_align <<=3D max_order + __ffs(SZ_1M); + + for (order =3D max_order - 1; order >=3D 0; order--) { + resource_size_t align1 =3D 1; + + align1 <<=3D order + __ffs(SZ_1M); + + /* + * Account smaller resources with alignment < max_order that + * could be used to fill head room if alignment less than + * max_order is used. + */ + remainder +=3D aligns[order]; + + /* + * Test if head fill is enough to satisfy the alignment of + * the larger resources after reducing the alignment. + */ + while ((head_align > align1) && (remainder >=3D head_align / 2)) { + head_align /=3D 2; + remainder -=3D head_align; + } + } + + return head_align; +} + /** * pbus_upstream_space_available - Check no upstream resource limits alloc= ation * @bus: The bus @@ -1315,13 +1354,13 @@ static void pbus_size_mem(struct pci_bus *bus, unsi= gned long type, { struct pci_dev *dev; resource_size_t min_align, win_align, align, size, size0, size1 =3D 0; - resource_size_t aligns[28]; /* Alignments from 1MB to 128TB */ + resource_size_t aligns[28] =3D {}; /* Alignments from 1MB to 128TB */ + resource_size_t aligns2[28] =3D {};/* Alignments from 1MB to 128TB */ int order, max_order; struct resource *b_res =3D pbus_select_window_for_type(bus, type); resource_size_t children_add_size =3D 0; resource_size_t children_add_align =3D 0; resource_size_t add_align =3D 0; - resource_size_t relaxed_align; resource_size_t old_size; =20 if (!b_res) @@ -1331,7 +1370,6 @@ static void pbus_size_mem(struct pci_bus *bus, unsign= ed long type, if (b_res->parent) return; =20 - memset(aligns, 0, sizeof(aligns)); max_order =3D 0; size =3D 0; =20 @@ -1382,6 +1420,7 @@ static void pbus_size_mem(struct pci_bus *bus, unsign= ed long type, */ if (r_size <=3D align) aligns[order] +=3D align; + aligns2[order] +=3D align; if (order > max_order) max_order =3D order; =20 @@ -1406,9 +1445,7 @@ static void pbus_size_mem(struct pci_bus *bus, unsign= ed long type, =20 if (bus->self && size0 && !pbus_upstream_space_available(bus, b_res, size0, min_align)) { - relaxed_align =3D 1ULL << (max_order + __ffs(SZ_1M)); - relaxed_align =3D max(relaxed_align, win_align); - min_align =3D min(min_align, relaxed_align); + min_align =3D calculate_head_align(aligns2, max_order); size0 =3D calculate_memsize(size, min_size, 0, 0, old_size, win_align); resource_set_range(b_res, min_align, size0); pci_info(bus->self, "bridge window %pR to %pR requires relaxed alignment= rules\n", @@ -1422,9 +1459,7 @@ static void pbus_size_mem(struct pci_bus *bus, unsign= ed long type, =20 if (bus->self && size1 && !pbus_upstream_space_available(bus, b_res, size1, add_align)) { - relaxed_align =3D 1ULL << (max_order + __ffs(SZ_1M)); - relaxed_align =3D max(relaxed_align, win_align); - min_align =3D min(min_align, relaxed_align); + min_align =3D calculate_head_align(aligns2, max_order); size1 =3D calculate_memsize(size, min_size, add_size, children_add_size, old_size, win_align); pci_info(bus->self, --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E716C2550CD; Fri, 19 Dec 2025 17:41:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166072; cv=none; b=CDWBGxhLi7bmTHPaDABs1BzS37R+Q068t0aKFsn6WCp1OjkChbrJmTJH4cu1zdTaiotFU+Nl4y0vXKWliuWvkeJZNJ9Hdl3L4dahr7Z3vK9GQ4zaXSmZVsVMdP5vLuRwdXx8alAR3XJE464wCf2rliC27d8mMpfuZuJXtFABY/k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="198974833" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:41:08 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , =?UTF-8?q?Malte=20Schr=C3=B6der?= Subject: [PATCH 03/23] PCI: Stop over-estimating bridge window size Date: Fri, 19 Dec 2025 19:40:16 +0200 Message-Id: <20251219174036.16738-4-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable New way to calculate the bridge window head alignment produces tight-fit, that is, it does not leave any gaps between the resources. Similarly, relaxed tail alignment does not leave extra tail room. Start to use bridge window calculation that does not over-estimate the size of the required window. pbus_upstream_space_available() can be removed. Tested-by: Malte Schr=C3=B6der Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 97 +++-------------------------------------- 1 file changed, 5 insertions(+), 92 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 80e5a8fc62e7..612288716ba8 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1267,68 +1267,6 @@ static resource_size_t calculate_head_align(resource= _size_t *aligns, return head_align; } =20 -/** - * pbus_upstream_space_available - Check no upstream resource limits alloc= ation - * @bus: The bus - * @res: The resource to help select the correct bridge window - * @size: The size required from the bridge window - * @align: Required alignment for the resource - * - * Check that @size can fit inside the upstream bridge resources that are - * already assigned. Select the upstream bridge window based on the type of - * @res. - * - * Return: %true if enough space is available on all assigned upstream - * resources. - */ -static bool pbus_upstream_space_available(struct pci_bus *bus, - struct resource *res, - resource_size_t size, - resource_size_t align) -{ - struct resource_constraint constraint =3D { - .max =3D RESOURCE_SIZE_MAX, - .align =3D align, - }; - struct pci_bus *downstream =3D bus; - - while ((bus =3D bus->parent)) { - if (pci_is_root_bus(bus)) - break; - - res =3D pbus_select_window(bus, res); - if (!res) - return false; - if (!res->parent) - continue; - - if (resource_size(res) >=3D size) { - struct resource gap =3D {}; - - if (find_resource_space(res, &gap, size, &constraint) =3D=3D 0) { - gap.flags =3D res->flags; - pci_dbg(bus->self, - "Assigned bridge window %pR to %pR free space at %pR\n", - res, &bus->busn_res, &gap); - return true; - } - } - - if (bus->self) { - pci_info(bus->self, - "Assigned bridge window %pR to %pR cannot fit 0x%llx required for %s = bridging to %pR\n", - res, &bus->busn_res, - (unsigned long long)size, - pci_name(downstream->self), - &downstream->busn_res); - } - - return false; - } - - return true; -} - /** * pbus_size_mem() - Size the memory window of a given bus * @@ -1355,7 +1293,6 @@ static void pbus_size_mem(struct pci_bus *bus, unsign= ed long type, struct pci_dev *dev; resource_size_t min_align, win_align, align, size, size0, size1 =3D 0; resource_size_t aligns[28] =3D {}; /* Alignments from 1MB to 128TB */ - resource_size_t aligns2[28] =3D {};/* Alignments from 1MB to 128TB */ int order, max_order; struct resource *b_res =3D pbus_select_window_for_type(bus, type); resource_size_t children_add_size =3D 0; @@ -1414,13 +1351,8 @@ static void pbus_size_mem(struct pci_bus *bus, unsig= ned long type, continue; } size +=3D max(r_size, align); - /* - * Exclude ranges with size > align from calculation of - * the alignment. - */ - if (r_size <=3D align) - aligns[order] +=3D align; - aligns2[order] +=3D align; + + aligns[order] +=3D align; if (order > max_order) max_order =3D order; =20 @@ -1434,38 +1366,19 @@ static void pbus_size_mem(struct pci_bus *bus, unsi= gned long type, =20 old_size =3D resource_size(b_res); win_align =3D window_alignment(bus, b_res->flags); - min_align =3D calculate_mem_align(aligns, max_order); + min_align =3D calculate_head_align(aligns, max_order); min_align =3D max(min_align, win_align); - size0 =3D calculate_memsize(size, min_size, 0, 0, old_size, min_align); + size0 =3D calculate_memsize(size, min_size, 0, 0, old_size, win_align); =20 if (size0) { resource_set_range(b_res, min_align, size0); b_res->flags &=3D ~IORESOURCE_DISABLED; } =20 - if (bus->self && size0 && - !pbus_upstream_space_available(bus, b_res, size0, min_align)) { - min_align =3D calculate_head_align(aligns2, max_order); - size0 =3D calculate_memsize(size, min_size, 0, 0, old_size, win_align); - resource_set_range(b_res, min_align, size0); - pci_info(bus->self, "bridge window %pR to %pR requires relaxed alignment= rules\n", - b_res, &bus->busn_res); - } - if (realloc_head && (add_size > 0 || children_add_size > 0)) { add_align =3D max(min_align, add_align); size1 =3D calculate_memsize(size, min_size, add_size, children_add_size, - old_size, add_align); - - if (bus->self && size1 && - !pbus_upstream_space_available(bus, b_res, size1, add_align)) { - min_align =3D calculate_head_align(aligns2, max_order); - size1 =3D calculate_memsize(size, min_size, add_size, children_add_size, - old_size, win_align); - pci_info(bus->self, - "bridge window %pR to %pR requires relaxed alignment rules\n", - b_res, &bus->busn_res); - } + old_size, win_align); } =20 if (!size0 && !size1) { --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50B1E25743D; Fri, 19 Dec 2025 17:41:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166080; cv=none; b=Z/DBy472s4Ivfuxwy71Hgabe6fNZaHcE+UlAbpfnvJlkE2NiTghHxgNQjnc0LxqX6O34fwV8LilVFPXld69fYTwD27RZC+Vu1NUv7uDSTeLBMypwNBkeQP+/uG8OwSvXZL6Ig7obtCC9UjxJrICu5KMBYcVPFnV3cSCKgKfK4Ko= ARC-Message-Signature: i=1; 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d="scan'208";a="198974843" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:41:16 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 04/23] resource: Increase MAX_IORES_LEVEL to 8 Date: Fri, 19 Dec 2025 19:40:17 +0200 Message-Id: <20251219174036.16738-5-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable While debugging a PCI resource allocation issue, the resources for many nested bridges and endpoints got flattened in /proc/iomem by MAX_IORES_LEVEL that is set to 5. This made the iomem output hard to read as the visual hierarchy cues were lost. Increase MAX_IORES_LEVEL to 8 to avoid flattening PCI topologies with nested bridges so aggressively (the case in the Link has the deepest resource at level 7 so 8 looks a reasonable limit). Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D220775 Signed-off-by: Ilpo J=C3=A4rvinen --- kernel/resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/resource.c b/kernel/resource.c index e4e9bac12e6e..c5f03ac78e44 100644 --- a/kernel/resource.c +++ b/kernel/resource.c @@ -82,7 +82,7 @@ static struct resource *next_resource(struct resource *p,= bool skip_children, =20 #ifdef CONFIG_PROC_FS =20 -enum { MAX_IORES_LEVEL =3D 5 }; +enum { MAX_IORES_LEVEL =3D 8 }; =20 static void *r_start(struct seq_file *m, loff_t *pos) __acquires(resource_lock) --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BE8732E135; Fri, 19 Dec 2025 17:41:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166091; cv=none; b=DICMSZeu7EIViZqeytQQMJ3A8aQmjPAP4DBmLeu04qbJ21ocZ0RGpWtwoB+WIXtp02+1My/c7q5UHaewZ5h/F4eFHgo832F0ZijJGBv4RHX9O5dY3+S4u/bMI+0AAnDdsDnCwa+oN8m0hEzfT2z9Kwo7ddvpTLL6rYorSZkOes0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166091; c=relaxed/simple; bh=2khM7urutIILia6aPBQpLXUSbEISIdV1dOEQaICjbEY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=GRl6LApAbbW5DTii9TF+jwrKx4NsRc1p/1XW3+KuKo3F8f/RFWpmNH5T35LY5VoGMjpjx4BvDvzVnqnQ/lYDvSsXiCZh9DzFXwhbB47V4T3mWGusfuR2Vgq7eLgNxQWSRvYopI77zDPX9Uk6g8bygRpk7LXktg92HHI9jg6CB2g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dYA9jbLi; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dYA9jbLi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1766166089; x=1797702089; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2khM7urutIILia6aPBQpLXUSbEISIdV1dOEQaICjbEY=; b=dYA9jbLiOcUf+oYPrYD1pCsYhooH2vxvXGAOWxH5y60Wez0IzYlRrZi6 TVKPjSIcYTAMIG6uonCqb4zXkxQu60ttVGey1OqS0OLnkWn57C6dOFh08 P1fsscya4prR4euYRbYw606IicQo0dh2BjOAAQsAdeCvEk6eho8wZapMU AFGGoDknz4LYQ0kC5u4vFYcxDRG8Rn2XJuvVD2wPf+ojwCeh0FYFCNl2c WJYckRQ29+uYB/P1mkp1gswHWUK1KbV2jdl6BdnPWDUU/soJoNxQLCuvu lPHkFf4F/2FCDTJHUK71x5s/KOApEQFzuiOlBhEEdwgx2afMY9mdeOVu7 g==; X-CSE-ConnectionGUID: zY2vcjjLSbaj0MzXOXIGhw== X-CSE-MsgGUID: FdN4zo+pQGi4qNerTiXm1A== X-IronPort-AV: E=McAfee;i="6800,10657,11635"; a="68062497" X-IronPort-AV: E=Sophos;i="6.20,256,1758610800"; d="scan'208";a="68062497" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:41:28 -0800 X-CSE-ConnectionGUID: jXZv9FnQTCKDOTtpgWbkJw== X-CSE-MsgGUID: +zhCO223TbSuPnHdfM/HhA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="199747896" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:41:25 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , linux-kernel@vger.kernel.org Cc: Simon Richter Subject: [PATCH 05/23] PCI: Remove old_size limit from bridge window sizing Date: Fri, 19 Dec 2025 19:40:18 +0200 Message-Id: <20251219174036.16738-6-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable calculate_memsize() applies lower bound to the resource size before aligning the resource size making it impossible to shrink bridge window resources. I've not found any justification for this lower bound and nothing indicated it was to work around some HW issue. Prior to the commit 3baeae36039a ("PCI: Use pci_release_resource() instead of release_resource()"), releasing a bridge window during BAR resize resulted in clearing start and end address of the resource. Clearing addresses destroys the resource size as a side-effect, therefore nullifying the effect of the old size lower bound. After the commit 3baeae36039a ("PCI: Use pci_release_resource() instead of release_resource()"), BAR resize uses the aligned old size, which results in exceeding what fits into the parent window in some cases: xe 0030:03:00.0: [drm] Attempting to resize bar from 256MiB -> 16384MiB xe 0030:03:00.0: BAR 0 [mem 0x620c000000000-0x620c000ffffff 64bit]: releasi= ng xe 0030:03:00.0: BAR 2 [mem 0x6200000000000-0x620000fffffff 64bit pref]: re= leasing pci 0030:02:01.0: bridge window [mem 0x6200000000000-0x620001fffffff 64bit = pref]: releasing pci 0030:01:00.0: bridge window [mem 0x6200000000000-0x6203fbff0ffff 64bit = pref]: releasing pci 0030:00:00.0: bridge window [mem 0x6200000000000-0x6203fbff0ffff 64bit = pref]: was not released (still contains assigned resources) pci 0030:00:00.0: Assigned bridge window [mem 0x6200000000000-0x6203fbff0ff= ff 64bit pref] to [bus 01-04] free space at [mem 0x6200400000000-0x62007fff= fffff 64bit pref] pci 0030:00:00.0: Assigned bridge window [mem 0x6200000000000-0x6203fbff0ff= ff 64bit pref] to [bus 01-04] cannot fit 0x4000000000 required for 0030:01:= 00.0 bridging to [bus 02-04] The old size of 0x6200000000000-0x6203fbff0ffff resource was used as the lower bound which results in 0x4000000000 size request due to alignment. That exceed what can fit into the parent window. Since the lower bound never even was enforced fully because the resource addresses were cleared when the bridge window is released, remove the old_size lower bound entirely and trust the calculated bridge window size is enough. This same problem may occur on io window side but seems less likely to cause issues due to general difference in alignment. Removing the lower bound may have other unforeseen consequences in case of io window so it's better to do leave as -next material if no problem is reported related to io window sizing (BAR resize shouldn't touch io windows anyway). Reported-by: Simon Richter Fixes: 3baeae36039a ("PCI: Use pci_release_resource() instead of release_re= source()") Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 612288716ba8..8660449f59bd 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1071,16 +1071,13 @@ static resource_size_t calculate_memsize(resource_s= ize_t size, resource_size_t min_size, resource_size_t add_size, resource_size_t children_add_size, - resource_size_t old_size, resource_size_t align) { if (size < min_size) size =3D min_size; - if (old_size =3D=3D 1) - old_size =3D 0; =20 size =3D max(size, add_size) + children_add_size; - return ALIGN(max(size, old_size), align); + return ALIGN(size, align); } =20 resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus, @@ -1298,7 +1295,6 @@ static void pbus_size_mem(struct pci_bus *bus, unsign= ed long type, resource_size_t children_add_size =3D 0; resource_size_t children_add_align =3D 0; resource_size_t add_align =3D 0; - resource_size_t old_size; =20 if (!b_res) return; @@ -1364,11 +1360,10 @@ static void pbus_size_mem(struct pci_bus *bus, unsi= gned long type, } } =20 - old_size =3D resource_size(b_res); win_align =3D window_alignment(bus, b_res->flags); min_align =3D calculate_head_align(aligns, max_order); min_align =3D max(min_align, win_align); - size0 =3D calculate_memsize(size, min_size, 0, 0, old_size, win_align); + size0 =3D calculate_memsize(size, min_size, 0, 0, win_align); =20 if (size0) { resource_set_range(b_res, min_align, size0); @@ -1378,7 +1373,7 @@ static void pbus_size_mem(struct pci_bus *bus, unsign= ed long type, if (realloc_head && (add_size > 0 || children_add_size > 0)) { add_align =3D max(min_align, add_align); size1 =3D calculate_memsize(size, min_size, add_size, children_add_size, - old_size, win_align); + win_align); } =20 if (!size0 && !size1) { --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F589326948; 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X-CSE-ConnectionGUID: 8ex0sPBFSh+ct2jJt5pu0w== X-CSE-MsgGUID: gouDggFHTcaDL8i+WHXisw== X-IronPort-AV: E=McAfee;i="6800,10657,11635"; a="68062514" X-IronPort-AV: E=Sophos;i="6.20,256,1758610800"; d="scan'208";a="68062514" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:41:41 -0800 X-CSE-ConnectionGUID: Lp5besEGSTyFwbb83btu9g== X-CSE-MsgGUID: o0AcQSYLQvS/8SCGG9AOvg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="199747954" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:41:38 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 06/23] PCI: Push realloc check into pbus_size_mem() Date: Fri, 19 Dec 2025 19:40:19 +0200 Message-Id: <20251219174036.16738-7-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable pbus_size_mem() and calculate_memsize() input both min_size and add_size. They are given the same value if realloc_head is NULL and min_size is 0 otherwise. Both are used in calculate_memsize() to enforce a lower bound to the size. The interface between __pci_bus_size_bridges() and the forementioned functions can be simplied by pushing the realloc check into pbus_size_mem(). There are only two possible cases: 1) when calculating size0, add_size parameter given to calculate_memsize() is always 0 which implies only min_size matters. 2) when calculating size1, realloc_head is not NULL which implies min_size=3D0 so only add_size matters. Drop min_size parameter from pbus_size_mem() and check realloc_head when calling calculate_memsize(). Drop add_size from calculate_memsize() and use only min_size within max() to enforce the lower bound. calculate_iosize() is a bit more complicated than calculate_memsize() and is therefore left as is, but pbus_size_io() can still input only min_size similar to pbus_size_mem(). Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 34 ++++++++++++---------------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 8660449f59bd..f85ae20dc894 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1069,14 +1069,10 @@ static resource_size_t calculate_iosize(resource_si= ze_t size, =20 static resource_size_t calculate_memsize(resource_size_t size, resource_size_t min_size, - resource_size_t add_size, resource_size_t children_add_size, resource_size_t align) { - if (size < min_size) - size =3D min_size; - - size =3D max(size, add_size) + children_add_size; + size =3D max(size, min_size) + children_add_size; return ALIGN(size, align); } =20 @@ -1115,8 +1111,7 @@ static resource_size_t window_alignment(struct pci_bu= s *bus, unsigned long type) * pbus_size_io() - Size the I/O window of a given bus * * @bus: The bus - * @min_size: The minimum I/O window that must be allocated - * @add_size: Additional optional I/O window + * @add_size: Additional I/O window * @realloc_head: Track the additional I/O window on this list * * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these @@ -1124,8 +1119,7 @@ static resource_size_t window_alignment(struct pci_bu= s *bus, unsigned long type) * devices are limited to 256 bytes. We must be careful with the ISA * aliasing though. */ -static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, - resource_size_t add_size, +static void pbus_size_io(struct pci_bus *bus, resource_size_t add_size, struct list_head *realloc_head) { struct pci_dev *dev; @@ -1170,7 +1164,7 @@ static void pbus_size_io(struct pci_bus *bus, resourc= e_size_t min_size, } } =20 - size0 =3D calculate_iosize(size, min_size, size1, 0, 0, + size0 =3D calculate_iosize(size, realloc_head ? 0 : add_size, size1, 0, 0, resource_size(b_res), min_align); =20 if (size0) @@ -1178,7 +1172,7 @@ static void pbus_size_io(struct pci_bus *bus, resourc= e_size_t min_size, =20 size1 =3D size0; if (realloc_head && (add_size > 0 || children_add_size > 0)) { - size1 =3D calculate_iosize(size, min_size, size1, add_size, + size1 =3D calculate_iosize(size, 0, size1, add_size, children_add_size, resource_size(b_res), min_align); } @@ -1269,8 +1263,7 @@ static resource_size_t calculate_head_align(resource_= size_t *aligns, * * @bus: The bus * @type: The type of bridge resource - * @min_size: The minimum memory window that must be allocated - * @add_size: Additional optional memory window + * @add_size: Additional memory window * @realloc_head: Track the additional memory window on this list * * Calculate the size of the bus resource for @type and minimal alignment @@ -1283,7 +1276,6 @@ static resource_size_t calculate_head_align(resource_= size_t *aligns, * supplied. */ static void pbus_size_mem(struct pci_bus *bus, unsigned long type, - resource_size_t min_size, resource_size_t add_size, struct list_head *realloc_head) { @@ -1363,7 +1355,8 @@ static void pbus_size_mem(struct pci_bus *bus, unsign= ed long type, win_align =3D window_alignment(bus, b_res->flags); min_align =3D calculate_head_align(aligns, max_order); min_align =3D max(min_align, win_align); - size0 =3D calculate_memsize(size, min_size, 0, 0, win_align); + size0 =3D calculate_memsize(size, realloc_head ? 0 : add_size, + 0, win_align); =20 if (size0) { resource_set_range(b_res, min_align, size0); @@ -1372,7 +1365,7 @@ static void pbus_size_mem(struct pci_bus *bus, unsign= ed long type, =20 if (realloc_head && (add_size > 0 || children_add_size > 0)) { add_align =3D max(min_align, add_align); - size1 =3D calculate_memsize(size, min_size, add_size, children_add_size, + size1 =3D calculate_memsize(size, add_size, children_add_size, win_align); } =20 @@ -1550,20 +1543,17 @@ void __pci_bus_size_bridges(struct pci_bus *bus, st= ruct list_head *realloc_head) } fallthrough; default: - pbus_size_io(bus, realloc_head ? 0 : additional_io_size, - additional_io_size, realloc_head); + pbus_size_io(bus, additional_io_size, realloc_head); =20 if (pref && (pref->flags & IORESOURCE_PREFETCH)) { pbus_size_mem(bus, IORESOURCE_MEM | IORESOURCE_PREFETCH | (pref->flags & IORESOURCE_MEM_64), - realloc_head ? 0 : additional_mmio_pref_size, additional_mmio_pref_size, realloc_head); } =20 - pbus_size_mem(bus, IORESOURCE_MEM, - realloc_head ? 0 : additional_mmio_size, - additional_mmio_size, realloc_head); + pbus_size_mem(bus, IORESOURCE_MEM, additional_mmio_size, + realloc_head); break; } } --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA7EB33C53B; Fri, 19 Dec 2025 17:41:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166110; cv=none; b=inYDQTSnf/tM9ethjRLoGSxA5FMsUIz+3d8j+BMOaodxj4EH6N0UMqCnTdW+WxPsH4u3nAgghh7eYSdmIaWy1ftA3J7+PKHTg9j96a+ry7ubaRDzCMc6cuReg51d7amBiS9x4r5B/NWQmLAR4Sa0xluarSiECfD51LrhEHu1S1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166110; c=relaxed/simple; bh=cEwYGsfjSljTBm+Y67K3qMuhLIPGBKVketKYBjW7m/g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=p/bfA/+u3fbjGsvj5kFo7mqQRjAdvuezhqiRTlUwQ8JTLuwdRCX9c7yxmTBz9XNoAaxMqAYXmJTW5wQUUwcJiriXRgFru2yVSdMDQXMu4/w6bph7PLco4sJEbe7eswgmBqcRL9/nCfyKpTMdBp0bA1rS56bPLYGMUbEoFnUZUAk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=h4LsSNb8; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="h4LsSNb8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1766166109; x=1797702109; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cEwYGsfjSljTBm+Y67K3qMuhLIPGBKVketKYBjW7m/g=; b=h4LsSNb8m9ShwMd+V+yEy1fFzG5Qzc/UWPDHOhpNR3XDxQ4Fu1W2B4cB 5FlsBMInTRTn/riZFWzMAp7N/2lHG+9U7+owWKmSX9vqt6KSOQi5Iz9r+ 8wWfwizT1d8/h6wwCRn1ptYI1VTO/KbVyfKD0rAqWZYVqWER41VWPLcFE V4+Mv332uEuDLdTPWVbsqb/SpDobcZGEEkYWQceMVK78AQQXT4+SkYe+4 0XI62l5zKvYIwY4ofm8S78pTSc82f5wCmRhcW1jxGIjiZuyGXK02naici A3Lp6CVulJOln9lXhWOPjncbGptq1dUK/VRHZEeO8XcqTcyx9QNvkUaVy g==; X-CSE-ConnectionGUID: j41yHqXYR6Gp9+jBYHRewA== X-CSE-MsgGUID: BGbVYjvVQP+UxnIFzvCGyg== X-IronPort-AV: E=McAfee;i="6800,10657,11635"; a="68062524" X-IronPort-AV: E=Sophos;i="6.20,256,1758610800"; d="scan'208";a="68062524" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:41:49 -0800 X-CSE-ConnectionGUID: jYoerd8kQAy3LNZ4W23YkQ== X-CSE-MsgGUID: DaCg608xR/SjPdH6QzR0Dg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="199747983" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:41:45 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 07/23] PCI: Pass bridge window resource to pbus_size_mem() Date: Fri, 19 Dec 2025 19:40:20 +0200 Message-Id: <20251219174036.16738-8-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable pbus_size_mem() inputs type and calculates bridge window resource within. Its caller (__pci_bus_size_bridges()) also has to lookup the prefetchable window to determine if it exists or not to decide whether to call pbus_size_mem() twice or once. Change the interface such that the caller is responsible in providing the bridge window resource. Passing the resource directly avoids another lookup for the prefetchable window inside pbus_size_mem(). Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index f85ae20dc894..90bb9baf68b9 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1262,11 +1262,11 @@ static resource_size_t calculate_head_align(resourc= e_size_t *aligns, * pbus_size_mem() - Size the memory window of a given bus * * @bus: The bus - * @type: The type of bridge resource + * @b_res: The bridge window resource * @add_size: Additional memory window * @realloc_head: Track the additional memory window on this list * - * Calculate the size of the bus resource for @type and minimal alignment + * Calculate the size of the bridge window @b_res and minimal alignment * which guarantees that all child resources fit in this size. * * Set the bus resource start/end to indicate the required size if there an @@ -1275,15 +1275,14 @@ static resource_size_t calculate_head_align(resourc= e_size_t *aligns, * Add optional resource requests to the @realloc_head list if it is * supplied. */ -static void pbus_size_mem(struct pci_bus *bus, unsigned long type, - resource_size_t add_size, - struct list_head *realloc_head) +static void pbus_size_mem(struct pci_bus *bus, struct resource *b_res, + resource_size_t add_size, + struct list_head *realloc_head) { struct pci_dev *dev; resource_size_t min_align, win_align, align, size, size0, size1 =3D 0; resource_size_t aligns[28] =3D {}; /* Alignments from 1MB to 128TB */ int order, max_order; - struct resource *b_res =3D pbus_select_window_for_type(bus, type); resource_size_t children_add_size =3D 0; resource_size_t children_add_align =3D 0; resource_size_t add_align =3D 0; @@ -1494,7 +1493,7 @@ void __pci_bus_size_bridges(struct pci_bus *bus, stru= ct list_head *realloc_head) struct pci_dev *dev; resource_size_t additional_io_size =3D 0, additional_mmio_size =3D 0, additional_mmio_pref_size =3D 0; - struct resource *pref; + struct resource *b_res; struct pci_host_bridge *host; int hdr_type; =20 @@ -1520,12 +1519,8 @@ void __pci_bus_size_bridges(struct pci_bus *bus, str= uct list_head *realloc_head) host =3D to_pci_host_bridge(bus->bridge); if (!host->size_windows) return; - pci_bus_for_each_resource(bus, pref) - if (pref && (pref->flags & IORESOURCE_PREFETCH)) - break; hdr_type =3D -1; /* Intentionally invalid - not a PCI device. */ } else { - pref =3D &bus->self->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; hdr_type =3D bus->self->hdr_type; } =20 @@ -1545,15 +1540,19 @@ void __pci_bus_size_bridges(struct pci_bus *bus, st= ruct list_head *realloc_head) default: pbus_size_io(bus, additional_io_size, realloc_head); =20 - if (pref && (pref->flags & IORESOURCE_PREFETCH)) { - pbus_size_mem(bus, - IORESOURCE_MEM | IORESOURCE_PREFETCH | - (pref->flags & IORESOURCE_MEM_64), - additional_mmio_pref_size, realloc_head); + b_res =3D pbus_select_window_for_type(bus, IORESOURCE_MEM | + IORESOURCE_PREFETCH | + IORESOURCE_MEM_64); + if (b_res && (b_res->flags & IORESOURCE_PREFETCH)) { + pbus_size_mem(bus, b_res, additional_mmio_pref_size, + realloc_head); } =20 - pbus_size_mem(bus, IORESOURCE_MEM, additional_mmio_size, - realloc_head); + b_res =3D pbus_select_window_for_type(bus, IORESOURCE_MEM); + if (b_res) { + pbus_size_mem(bus, b_res, additional_mmio_size, + realloc_head); + } break; } } --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC30533E36E; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable reassign_resources_sorted() contains a search loop for a particular resource in the head list. res_to_dev_res() already implements the same search so use it instead. Drop unused found_match and dev_res variables. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 90bb9baf68b9..09cc225bf107 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -414,7 +414,6 @@ static void reassign_resources_sorted(struct list_head = *realloc_head, struct list_head *head) { struct pci_dev_resource *add_res, *tmp; - struct pci_dev_resource *dev_res; struct pci_dev *dev; struct resource *res; const char *res_name; @@ -422,8 +421,6 @@ static void reassign_resources_sorted(struct list_head = *realloc_head, int idx; =20 list_for_each_entry_safe(add_res, tmp, realloc_head, list) { - bool found_match =3D false; - res =3D add_res->res; dev =3D add_res->dev; idx =3D pci_resource_num(dev, res); @@ -437,13 +434,7 @@ static void reassign_resources_sorted(struct list_head= *realloc_head, goto out; =20 /* Skip this resource if not found in head list */ - list_for_each_entry(dev_res, head, list) { - if (dev_res->res =3D=3D res) { - found_match =3D true; - break; - } - } - if (!found_match) /* Just skip */ + if (!res_to_dev_res(head, res)) continue; =20 res_name =3D pci_resource_name(dev, idx); --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E5BF33E36E; Fri, 19 Dec 2025 17:42:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166125; cv=none; b=ZOeXMdh5JmcHxVSmWy7w+FdVhkaC3IR4fpH0eiGhe0KQ70nHIRjT8NDkRPyfAOhyU4A/bBcxTfJnNTMwt+0ZcCez3FBsnlsHk1hNKytogABhphYRH51ecjjHabI9FSuWTXUSn7IK9hbjMGGx3Bajv99VmWZd2gRg+sXGTcgQVJQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166125; c=relaxed/simple; bh=om3ws1vRY8NzG2OY8m8A/ZvUw3IlUN/TkNBaTtaKbyU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; 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19 Dec 2025 09:42:01 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 09/23] PCI: Fetch dev_res to local var in __assign_resources_sorted() Date: Fri, 19 Dec 2025 19:40:22 +0200 Message-Id: <20251219174036.16738-10-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable __assign_resources_sorted() calls get_res_add_size() and get_res_add_align(), each walking through the realloc_head list to relocate the corresponding pci_dev_resource entry. Fetch the pci_dev_resource entry into a local variable to avoid double walk. In addition, reverse logic to reduce indentation level. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 09cc225bf107..41417084ddf8 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -596,11 +596,11 @@ static void __assign_resources_sorted(struct list_hea= d *head, LIST_HEAD(local_fail_head); LIST_HEAD(dummy_head); struct pci_dev_resource *save_res; - struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; + struct pci_dev_resource *dev_res, *tmp_res, *dev_res2, *addsize_res; struct resource *res; struct pci_dev *dev; unsigned long fail_type; - resource_size_t add_align, align; + resource_size_t align; =20 if (!realloc_head) realloc_head =3D &dummy_head; @@ -621,8 +621,11 @@ static void __assign_resources_sorted(struct list_head= *head, list_for_each_entry_safe(dev_res, tmp_res, head, list) { res =3D dev_res->res; =20 - res->end +=3D get_res_add_size(realloc_head, res); + addsize_res =3D res_to_dev_res(realloc_head, res); + if (!addsize_res) + continue; =20 + res->end +=3D addsize_res->add_size; /* * There are two kinds of additional resources in the list: * 1. bridge resource -- IORESOURCE_STARTALIGN @@ -632,8 +635,8 @@ static void __assign_resources_sorted(struct list_head = *head, if (!(res->flags & IORESOURCE_STARTALIGN)) continue; =20 - add_align =3D get_res_add_align(realloc_head, res); - + if (addsize_res->min_align <=3D res->start) + continue; /* * The "head" list is sorted by alignment so resources with * bigger alignment will be assigned first. After we @@ -641,17 +644,15 @@ static void __assign_resources_sorted(struct list_hea= d *head, * need to reorder the list by alignment to make it * consistent. */ - if (add_align > res->start) { - resource_set_range(res, add_align, resource_size(res)); - - list_for_each_entry(dev_res2, head, list) { - align =3D pci_resource_alignment(dev_res2->dev, - dev_res2->res); - if (add_align > align) { - list_move_tail(&dev_res->list, - &dev_res2->list); - break; - } + resource_set_range(res, addsize_res->min_align, + resource_size(res)); + + list_for_each_entry(dev_res2, head, list) { + align =3D pci_resource_alignment(dev_res2->dev, + dev_res2->res); + if (addsize_res->min_align > align) { + list_move_tail(&dev_res->list, &dev_res2->list); + break; } } =20 --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 443BC33ADB1; Fri, 19 Dec 2025 17:42:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166134; cv=none; b=L7FK2yKm5VwtGij9aWNN4HAVGQUY9m5mvrNaE/ij/mswmNKbJeCsig1PRFdvHURBNDfasyugMgGIPYXoZmnwIc7dxBokXwZIUg8lkzoHFcTLatHWWaa8mOHgAFyxqkCgC179s1iEYfES0M2wFBW9SJqYbUwqybB7i5RZwdpfVLk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166134; c=relaxed/simple; bh=jbV7bMaiMlBpNb80xOxh5qKE5av1K1eirvSgZubtPoI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=dGqDqy9a9FEujtmTv1tmkhFaET6L/AEwCE16ChAxOsYlv+vNqEos3ef564M2HOOrBKx1wUTHN40NzI6iTujG5yyW/dUqSUCiC2q2fMS2qHSo5Yo/g0iC1mld1trB9c3Tjt96/AF1vj9TefuhR7abFGrCOOePBDrR+8kR0bF4te0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YpqXve16; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YpqXve16" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1766166133; x=1797702133; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jbV7bMaiMlBpNb80xOxh5qKE5av1K1eirvSgZubtPoI=; b=YpqXve16+KAT8VEs/kjSjwWHF3RKT7ZtVty5K/PQvNYuerZo9v6biZng Uj8B4x1FiGFihKBJRtchoh9BOEjvVoNKTixMiDAY8eABYuoN1AC4jtEWX YYEwdQQW1bgzUgzC2xBtcTASntxxrcU2zwOs41O5JIFu6NcrRcRIpSFPd cl00V7sHam6n8ES4wMYvYymIysLLu66kT0ZEIEoa+N2/CbKf6YkbF6NSY +zu0fO3Dcqmrf6YbUkOJmXpy9trimFV9ckxgQnZuJAtxB5VXQ8lQI03/I tVOjsuCZ9Csw/Eebg/T59KROHlWvaax+V3VqYYymwHbg3AGU7ygEA3MjU A==; X-CSE-ConnectionGUID: IhyP7UUDSJKJPqFGPuTiCQ== X-CSE-MsgGUID: doPBobEWSPOrfzcJIPivCA== X-IronPort-AV: E=McAfee;i="6800,10657,11647"; a="68173903" X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="68173903" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:42:12 -0800 X-CSE-ConnectionGUID: CGGMlx9IQVC1/De4Q6CcyQ== X-CSE-MsgGUID: R0NwvNluTtuu0bEiS/0r8g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="229597867" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:42:09 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 10/23] PCI: Add pci_resource_is_bridge_win() Date: Fri, 19 Dec 2025 19:40:23 +0200 Message-Id: <20251219174036.16738-11-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add pci_resource_is_bridge_win() helper to simplify checking if the resource is a bridge window. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/pci-sysfs.c | 2 +- drivers/pci/pci.h | 5 +++++ drivers/pci/setup-bus.c | 7 +++---- drivers/pci/setup-res.c | 2 +- 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index c2df915ad2d2..363187ba4f56 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -181,7 +181,7 @@ static ssize_t resource_show(struct device *dev, struct= device_attribute *attr, struct resource zerores =3D {}; =20 /* For backwards compatibility */ - if (i >=3D PCI_BRIDGE_RESOURCES && i <=3D PCI_BRIDGE_RESOURCE_END && + if (pci_resource_is_bridge_win(i) && res->flags & (IORESOURCE_UNSET | IORESOURCE_DISABLED)) res =3D &zerores; =20 diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 0e67014aa001..c27144af550f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -452,6 +452,11 @@ void pci_walk_bus_locked(struct pci_bus *top, =20 const char *pci_resource_name(struct pci_dev *dev, unsigned int i); bool pci_resource_is_optional(const struct pci_dev *dev, int resno); +static inline bool pci_resource_is_bridge_win(int resno) +{ + return resno >=3D PCI_BRIDGE_RESOURCES && + resno <=3D PCI_BRIDGE_RESOURCE_END; +} =20 /** * pci_resource_num - Reverse lookup resource number from device resources diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 41417084ddf8..403139d8c86a 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -303,8 +303,7 @@ static bool pdev_resource_assignable(struct pci_dev *de= v, struct resource *res) if (!res->flags) return false; =20 - if (idx >=3D PCI_BRIDGE_RESOURCES && idx <=3D PCI_BRIDGE_RESOURCE_END && - res->flags & IORESOURCE_DISABLED) + if (pci_resource_is_bridge_win(idx) && res->flags & IORESOURCE_DISABLED) return false; =20 return true; @@ -389,7 +388,7 @@ static inline void reset_resource(struct pci_dev *dev, = struct resource *res) { int idx =3D pci_resource_num(dev, res); =20 - if (idx >=3D PCI_BRIDGE_RESOURCES && idx <=3D PCI_BRIDGE_RESOURCE_END) { + if (pci_resource_is_bridge_win(idx)) { res->flags |=3D IORESOURCE_UNSET; return; } @@ -985,7 +984,7 @@ int pci_claim_bridge_resource(struct pci_dev *bridge, i= nt i) { int ret =3D -EINVAL; =20 - if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END) + if (!pci_resource_is_bridge_win(i)) return 0; =20 if (pci_claim_resource(bridge, i) =3D=3D 0) diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index e5fcadfc58b0..bb2aef373d6f 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -359,7 +359,7 @@ int pci_assign_resource(struct pci_dev *dev, int resno) =20 res->flags &=3D ~IORESOURCE_UNSET; res->flags &=3D ~IORESOURCE_STARTALIGN; - if (resno >=3D PCI_BRIDGE_RESOURCES && resno <=3D PCI_BRIDGE_RESOURCE_END) + if (pci_resource_is_bridge_win(resno)) res->flags &=3D ~IORESOURCE_DISABLED; =20 pci_info(dev, "%s %pR: assigned\n", res_name, res); --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB3C8341051; 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X-CSE-ConnectionGUID: C1uTfkg0TmSn9wxctrdQaQ== X-CSE-MsgGUID: n97qbBADT5Knnl32qTtZ6g== X-IronPort-AV: E=McAfee;i="6800,10657,11647"; a="68173923" X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="68173923" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:42:19 -0800 X-CSE-ConnectionGUID: dvZzyn5dTGGfJ+B8qmkxHQ== X-CSE-MsgGUID: of1sv5hnTEiu/fEzepHwbg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="229597876" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:42:17 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 11/23] PCI: Log reset and restore of resources Date: Fri, 19 Dec 2025 19:40:24 +0200 Message-Id: <20251219174036.16738-12-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable PCI resource fitting and assignment is complicated to track because it performs many actions without any logging. One of these is resource reset (zeroing the resource) and the restore during the multi-passed resource fitting algorithm. Resource reset does not play well with the other PCI code if the code later wants to reattempt assignment of that resource, knowing that a resource was left into the reset state without a pairing restore is useful for understanding issues that show up as resource assignment failures. Add pci_dbg() to both reset and restore to be better able to track what's going on within the resource fitting algorithm. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 403139d8c86a..a5b6c555a45b 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -136,6 +136,9 @@ static resource_size_t get_res_add_align(struct list_he= ad *head, static void restore_dev_resource(struct pci_dev_resource *dev_res) { struct resource *res =3D dev_res->res; + struct pci_dev *dev =3D dev_res->dev; + int idx =3D pci_resource_num(dev, res); + const char *res_name =3D pci_resource_name(dev, idx); =20 if (WARN_ON_ONCE(res->parent)) return; @@ -143,6 +146,8 @@ static void restore_dev_resource(struct pci_dev_resourc= e *dev_res) res->start =3D dev_res->start; res->end =3D dev_res->end; res->flags =3D dev_res->flags; + + pci_dbg(dev, "%s %pR: resource restored\n", res_name, res); } =20 /* @@ -384,15 +389,18 @@ bool pci_resource_is_optional(const struct pci_dev *d= ev, int resno) return false; } =20 -static inline void reset_resource(struct pci_dev *dev, struct resource *re= s) +static void reset_resource(struct pci_dev *dev, struct resource *res) { int idx =3D pci_resource_num(dev, res); + const char *res_name =3D pci_resource_name(dev, idx); =20 if (pci_resource_is_bridge_win(idx)) { res->flags |=3D IORESOURCE_UNSET; return; } =20 + pci_dbg(dev, "%s %pR: resetting resource\n", res_name, res); + res->start =3D 0; res->end =3D 0; res->flags =3D 0; --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CC8634251B; Fri, 19 Dec 2025 17:42:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166150; cv=none; b=NTX3sB9MBHZL31cffTksqejM2Eu2HGrupTC2viI/MyCTULieaBLepgD/Gu0ubiLahwBfT83rBPisr7Il5+y/nS6zXSuSSwdNAiGoCWjnH3PUCxLdxX1+N9KPKhmzYXeHis5ioef0+Yq8445cfxD4rFcqB0YHR/lwMaLEhKBdNL0= ARC-Message-Signature: i=1; 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d="scan'208";a="229597888" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:42:25 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 12/23] PCI: Check invalid align earlier in pbus_size_mem() Date: Fri, 19 Dec 2025 19:40:25 +0200 Message-Id: <20251219174036.16738-13-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Check for invalid align before any bridge window sizing actions in pbus_size_mem() to avoid need to roll back any sizing calculations. Placing the check earlier will make it easier to add more optional size related calculations at where the SRIOV logic currently is in pbus_size_mem(). Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index a5b6c555a45b..3d1d3cefcdba 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -1311,31 +1312,29 @@ static void pbus_size_mem(struct pci_bus *bus, stru= ct resource *b_res, continue; =20 r_size =3D resource_size(r); - - /* Put SRIOV requested res to the optional list */ - if (realloc_head && pci_resource_is_optional(dev, i)) { - add_align =3D max(pci_resource_alignment(dev, r), add_align); - add_to_list(realloc_head, dev, r, 0, 0 /* Don't care */); - children_add_size +=3D r_size; - continue; - } - + align =3D pci_resource_alignment(dev, r); /* * aligns[0] is for 1MB (since bridge memory * windows are always at least 1MB aligned), so * keep "order" from being negative for smaller * resources. */ - align =3D pci_resource_alignment(dev, r); - order =3D __ffs(align) - __ffs(SZ_1M); - if (order < 0) - order =3D 0; + order =3D max_t(int, __ffs(align) - __ffs(SZ_1M), 0); if (order >=3D ARRAY_SIZE(aligns)) { pci_warn(dev, "%s %pR: disabling; bad alignment %#llx\n", r_name, r, (unsigned long long) align); r->flags =3D 0; continue; } + + /* Put SRIOV requested res to the optional list */ + if (realloc_head && pci_resource_is_optional(dev, i)) { + add_align =3D max(align, add_align); + add_to_list(realloc_head, dev, r, 0, 0 /* Don't care */); + children_add_size +=3D r_size; + continue; + } + size +=3D max(r_size, align); =20 aligns[order] +=3D align; --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5460634251B; Fri, 19 Dec 2025 17:42:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable The resource loop in pbus_size_mem() handles optional resources that are either fully optional (SRIOV and disabled Expansion ROMs) or bridge windows that may be optional only for a part. The logic is little inconsistent when it comes to a bridge window that has only optional children resources as it would be more natural to treat it similar to any fully optional resource. As resource size should be zero in that case, it shouldn't cause any bugs but it still seems useful to address the inconsistency. Place the optional size related code of pbus_size_mem() into pbus_mem_size_optional() and add check into pci_resource_is_optional() for entirely optional bridge windows. Reorder the logic inside pbus_mem_size_optional() such that fully optional resources are handled the same irrespective to whether the resource is a bridge window or not. Additional motivation for this are the upcoming changes that add complexity to the optional sizing logic due to Resizable BAR awareness. The extra logic would exceed any reasonable indentation level if the optional sizing code is kept within the loop body. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 77 +++++++++++++++++++++++++++++------------ 1 file changed, 54 insertions(+), 23 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 3d1d3cefcdba..3fcc7641c374 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -125,15 +125,6 @@ static resource_size_t get_res_add_size(struct list_he= ad *head, return dev_res ? dev_res->add_size : 0; } =20 -static resource_size_t get_res_add_align(struct list_head *head, - struct resource *res) -{ - struct pci_dev_resource *dev_res; - - dev_res =3D res_to_dev_res(head, res); - return dev_res ? dev_res->min_align : 0; -} - static void restore_dev_resource(struct pci_dev_resource *dev_res) { struct resource *res =3D dev_res->res; @@ -386,6 +377,8 @@ bool pci_resource_is_optional(const struct pci_dev *dev= , int resno) return true; if (resno =3D=3D PCI_ROM_RESOURCE && !(res->flags & IORESOURCE_ROM_ENABLE= )) return true; + if (pci_resource_is_bridge_win(resno) && !resource_size(res)) + return true; =20 return false; } @@ -1258,6 +1251,54 @@ static resource_size_t calculate_head_align(resource= _size_t *aligns, return head_align; } =20 +/* + * pbus_size_mem_optional - Account optional resources in bridge window + * + * Account an optional resource or the optional part of the resource in br= idge + * window size. + * + * Return: %true if the resource is entirely optional. + */ +static bool pbus_size_mem_optional(struct pci_dev *dev, int resno, + resource_size_t align, + struct list_head *realloc_head, + resource_size_t *add_align, + resource_size_t *children_add_size) +{ + struct resource *res =3D pci_resource_n(dev, resno); + bool optional =3D pci_resource_is_optional(dev, resno); + resource_size_t r_size =3D resource_size(res); + struct pci_dev_resource *dev_res; + + if (!realloc_head) + return false; + + if (!optional) { + /* + * Only bridges have optional sizes in realloc_head at this + * point. As res_to_dev_res() walks the entire realloc_head + * list, skip calling it when known unnecessary. + */ + if (!pci_resource_is_bridge_win(resno)) + return false; + + dev_res =3D res_to_dev_res(realloc_head, res); + if (dev_res) { + *children_add_size +=3D dev_res->add_size; + *add_align =3D max(*add_align, dev_res->min_align); + } + + return false; + } + + /* Put SRIOV requested res to the optional list */ + add_to_list(realloc_head, dev, res, 0, align); + *children_add_size +=3D r_size; + *add_align =3D max(align, *add_align); + + return true; +} + /** * pbus_size_mem() - Size the memory window of a given bus * @@ -1284,7 +1325,6 @@ static void pbus_size_mem(struct pci_bus *bus, struct= resource *b_res, resource_size_t aligns[28] =3D {}; /* Alignments from 1MB to 128TB */ int order, max_order; resource_size_t children_add_size =3D 0; - resource_size_t children_add_align =3D 0; resource_size_t add_align =3D 0; =20 if (!b_res) @@ -1311,7 +1351,6 @@ static void pbus_size_mem(struct pci_bus *bus, struct= resource *b_res, if (b_res !=3D pbus_select_window(bus, r)) continue; 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X-CSE-ConnectionGUID: PvQsYP4mTmiacGWBVx6OCg== X-CSE-MsgGUID: t1onHBw6Q9SUtxdo9Cf41A== X-IronPort-AV: E=McAfee;i="6800,10657,11647"; a="67880682" X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="67880682" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:42:44 -0800 X-CSE-ConnectionGUID: cKvUx6oqTdK6pI6C/rQIbA== X-CSE-MsgGUID: PngX/G79S2W6hobgLslamw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="198497090" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:42:40 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 14/23] resource: Mark res given to resource_assigned() as const Date: Fri, 19 Dec 2025 19:40:27 +0200 Message-Id: <20251219174036.16738-15-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The caller may hold a const struct resource which will trigger an unnecessary warning when calling resource_assigned() as it will not modify res in anyway. Mark resource_assigned()'s struct resource *res parameter const to avoid the compiler warning. Signed-off-by: Ilpo J=C3=A4rvinen --- include/linux/ioport.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/ioport.h b/include/linux/ioport.h index 9afa30f9346f..60ca6a49839c 100644 --- a/include/linux/ioport.h +++ b/include/linux/ioport.h @@ -338,7 +338,7 @@ static inline bool resource_union(const struct resource= *r1, const struct resour * Check if this resource is added to a resource tree or detached. Caller = is * responsible for not racing assignment. */ -static inline bool resource_assigned(struct resource *res) +static inline bool resource_assigned(const struct resource *res) { return res->parent; } --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA62B34105B; Fri, 19 Dec 2025 17:42:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166175; cv=none; b=aaJ9ntlKAOhITInCGWwAdgwh2YrZ2oZi7ODkl466JPDKd5VHzUkWYNnXn/Bl5wyrYFoRU+hrh5ssu3e1BpU3bdPXZ+wXn6nouCb/I69xvuNEEG7k2VylW1x0iJ7TQIZJx3EM/yzWs1YLzTB63tZmWO61ZHR67waUz6aIZAbBfcU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166175; c=relaxed/simple; bh=Ggh/CA7ZGkotjZdlqofUy3jwBogYwx5cmhDn9qY6gvo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=NfARMArFN7LHC8R5aGnLPt/T5A84NLZd32stFJS4qFBfkrw5p+03CQqtBVBSUMOSsMWmRDvRWSst02oyLwG5uFE8TLsWoksBPiL5TUlVfccPFjDYQcp/iZV6P0buUH54ut2S8ahAtcVARVh20kM16T+yzqArrvfOoKlVg3P4GSk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=fDrXqcdC; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="fDrXqcdC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1766166172; x=1797702172; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ggh/CA7ZGkotjZdlqofUy3jwBogYwx5cmhDn9qY6gvo=; b=fDrXqcdC6mm8TLzV6VZcEsMa9Vg3tt7ZTADvHpAZOghWzi4uJH9CPeME X4BxRDg04YG8GJDGtdKCpBzZ2jfOi4eFXTX2CSu7wlv28xXmUyenvSgSk Ye3WZV2SWTm4lyQgDGPI6sW3YuBSHYTMkHVU/l+/gqj8oZO4CYgrANdoW 8HjjAhr5jeH/YIszpNCD/6Imoq976fo9u2TU2q7IwTo3pioUIkFBcWIsI NqqIdj5QeqcDMaTKp48sdCK9LJ67bKEFoyxk36XmCc1TVnUZz9X0fR6Fk h4SKpCA7geKDwzItZAXKXvWDswcs2ZGkGt/S7nEGWkxe2cglz78sfqeZX Q==; X-CSE-ConnectionGUID: 36SZqhcRTxKWD/Z9PVLDPQ== X-CSE-MsgGUID: PU4HKDtOS3qG1+YfNlFZEA== X-IronPort-AV: E=McAfee;i="6800,10657,11647"; a="67880696" X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="67880696" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:42:51 -0800 X-CSE-ConnectionGUID: mLL18Lu5Qb2O7fcBFaWYsA== X-CSE-MsgGUID: x5pBbgEYSJGm6NVh1aksvg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="198497104" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:42:48 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 15/23] PCI: Use resource_assigned() in setup-bus.c algorithm Date: Fri, 19 Dec 2025 19:40:28 +0200 Message-Id: <20251219174036.16738-16-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Many places in the resource fitting and assignment algorithm want to know if the resource is assigned into the resource tree or not. Convert open-coded ->parent checks to use resource_assigned(). Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 64 +++++++++++++++++++++-------------------- 1 file changed, 33 insertions(+), 31 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 3fcc7641c374..bbc615d85c88 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -132,7 +132,7 @@ static void restore_dev_resource(struct pci_dev_resourc= e *dev_res) int idx =3D pci_resource_num(dev, res); const char *res_name =3D pci_resource_name(dev, idx); =20 - if (WARN_ON_ONCE(res->parent)) + if (WARN_ON_ONCE(resource_assigned(res))) return; =20 res->start =3D dev_res->start; @@ -166,7 +166,7 @@ static struct resource *find_bus_resource_of_type(struc= t pci_bus *bus, if ((r->flags & type_mask) !=3D type) continue; =20 - if (!r->parent) + if (!resource_assigned(r)) return r; if (!r_assigned) r_assigned =3D r; @@ -269,7 +269,7 @@ static struct resource *pbus_select_window_for_type(str= uct pci_bus *bus, struct resource *pbus_select_window(struct pci_bus *bus, const struct resource *res) { - if (res->parent) + if (resource_assigned(res)) return res->parent; =20 return pbus_select_window_for_type(bus, res->flags); @@ -308,7 +308,7 @@ static bool pdev_resource_assignable(struct pci_dev *de= v, struct resource *res) =20 static bool pdev_resource_should_fit(struct pci_dev *dev, struct resource = *res) { - if (res->parent) + if (resource_assigned(res)) return false; =20 if (res->flags & IORESOURCE_PCI_FIXED) @@ -430,7 +430,7 @@ static void reassign_resources_sorted(struct list_head = *realloc_head, * Skip resource that failed the earlier assignment and is * not optional as it would just fail again. */ - if (!res->parent && resource_size(res) && + if (!resource_assigned(res) && resource_size(res) && !pci_resource_is_optional(dev, idx)) goto out; =20 @@ -441,7 +441,7 @@ static void reassign_resources_sorted(struct list_head = *realloc_head, res_name =3D pci_resource_name(dev, idx); add_size =3D add_res->add_size; align =3D add_res->min_align; - if (!res->parent) { + if (!resource_assigned(res)) { resource_set_range(res, align, resource_size(res) + add_size); if (pci_assign_resource(dev, idx)) { @@ -677,7 +677,7 @@ static void __assign_resources_sorted(struct list_head = *head, list_for_each_entry(save_res, &save_head, list) { struct resource *res =3D save_res->res; =20 - if (res->parent) + if (resource_assigned(res)) continue; =20 restore_dev_resource(save_res); @@ -693,7 +693,8 @@ static void __assign_resources_sorted(struct list_head = *head, list_for_each_entry_safe(dev_res, tmp_res, head, list) { res =3D dev_res->res; =20 - if (res->parent && !pci_need_to_release(fail_type, res)) { + if (resource_assigned(res) && + !pci_need_to_release(fail_type, res)) { /* Remove it from realloc_head list */ remove_from_list(realloc_head, res); remove_from_list(&save_head, res); @@ -729,7 +730,7 @@ static void __assign_resources_sorted(struct list_head = *head, res =3D dev_res->res; dev =3D dev_res->dev; =20 - if (res->parent) + if (resource_assigned(res)) continue; =20 if (fail_head) { @@ -779,7 +780,7 @@ void pci_setup_cardbus(struct pci_bus *bus) =20 res =3D bus->resource[0]; pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (res->parent && res->flags & IORESOURCE_IO) { + if (resource_assigned(res) && res->flags & IORESOURCE_IO) { /* * The IO resource is allocated a range twice as large as it * would normally need. This allows us to set both IO regs. @@ -793,7 +794,7 @@ void pci_setup_cardbus(struct pci_bus *bus) =20 res =3D bus->resource[1]; pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (res->parent && res->flags & IORESOURCE_IO) { + if (resource_assigned(res) && res->flags & IORESOURCE_IO) { pci_info(bridge, " bridge window %pR\n", res); pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, region.start); @@ -803,7 +804,7 @@ void pci_setup_cardbus(struct pci_bus *bus) =20 res =3D bus->resource[2]; pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (res->parent && res->flags & IORESOURCE_MEM) { + if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { pci_info(bridge, " bridge window %pR\n", res); pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, region.start); @@ -813,7 +814,7 @@ void pci_setup_cardbus(struct pci_bus *bus) =20 res =3D bus->resource[3]; pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (res->parent && res->flags & IORESOURCE_MEM) { + if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { pci_info(bridge, " bridge window %pR\n", res); pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, region.start); @@ -854,7 +855,7 @@ static void pci_setup_bridge_io(struct pci_dev *bridge) res =3D &bridge->resource[PCI_BRIDGE_IO_WINDOW]; res_name =3D pci_resource_name(bridge, PCI_BRIDGE_IO_WINDOW); pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (res->parent && res->flags & IORESOURCE_IO) { + if (resource_assigned(res) && res->flags & IORESOURCE_IO) { pci_read_config_word(bridge, PCI_IO_BASE, &l); io_base_lo =3D (region.start >> 8) & io_mask; io_limit_lo =3D (region.end >> 8) & io_mask; @@ -886,7 +887,7 @@ static void pci_setup_bridge_mmio(struct pci_dev *bridg= e) res =3D &bridge->resource[PCI_BRIDGE_MEM_WINDOW]; res_name =3D pci_resource_name(bridge, PCI_BRIDGE_MEM_WINDOW); pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (res->parent && res->flags & IORESOURCE_MEM) { + if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { l =3D (region.start >> 16) & 0xfff0; l |=3D region.end & 0xfff00000; pci_info(bridge, " %s %pR\n", res_name, res); @@ -915,7 +916,7 @@ static void pci_setup_bridge_mmio_pref(struct pci_dev *= bridge) res =3D &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; res_name =3D pci_resource_name(bridge, PCI_BRIDGE_PREF_MEM_WINDOW); pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (res->parent && res->flags & IORESOURCE_PREFETCH) { + if (resource_assigned(res) && res->flags & IORESOURCE_PREFETCH) { l =3D (region.start >> 16) & 0xfff0; l |=3D region.end & 0xfff00000; if (res->flags & IORESOURCE_MEM_64) { @@ -1125,7 +1126,7 @@ static void pbus_size_io(struct pci_bus *bus, resourc= e_size_t add_size, return; =20 /* If resource is already assigned, nothing more to do */ - if (b_res->parent) + if (resource_assigned(b_res)) return; =20 min_align =3D window_alignment(bus, IORESOURCE_IO); @@ -1135,7 +1136,7 @@ static void pbus_size_io(struct pci_bus *bus, resourc= e_size_t add_size, pci_dev_for_each_resource(dev, r) { unsigned long r_size; =20 - if (r->parent || !(r->flags & IORESOURCE_IO)) + if (resource_assigned(r) || !(r->flags & IORESOURCE_IO)) continue; =20 if (!pdev_resource_assignable(dev, r)) @@ -1331,7 +1332,7 @@ static void pbus_size_mem(struct pci_bus *bus, struct= resource *b_res, return; =20 /* If resource is already assigned, nothing more to do */ - if (b_res->parent) + if (resource_assigned(b_res)) return; =20 max_order =3D 0; @@ -1436,7 +1437,7 @@ static void pci_bus_size_cardbus(struct pci_bus *bus, u16 ctrl; =20 b_res =3D &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW]; - if (b_res->parent) + if (resource_assigned(b_res)) goto handle_b_res_1; /* * Reserve some resources for CardBus. We reserve a fixed amount @@ -1452,7 +1453,7 @@ static void pci_bus_size_cardbus(struct pci_bus *bus, =20 handle_b_res_1: b_res =3D &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW]; - if (b_res->parent) + if (resource_assigned(b_res)) goto handle_b_res_2; resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); b_res->flags |=3D IORESOURCE_IO | IORESOURCE_STARTALIGN; @@ -1480,7 +1481,7 @@ static void pci_bus_size_cardbus(struct pci_bus *bus, } =20 b_res =3D &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW]; - if (b_res->parent) + if (resource_assigned(b_res)) goto handle_b_res_3; /* * If we have prefetchable memory support, allocate two regions. @@ -1503,7 +1504,7 @@ static void pci_bus_size_cardbus(struct pci_bus *bus, =20 handle_b_res_3: b_res =3D &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW]; - if (b_res->parent) + if (resource_assigned(b_res)) goto handle_done; resource_set_range(b_res, pci_cardbus_mem_size, b_res_3_size); b_res->flags |=3D IORESOURCE_MEM | IORESOURCE_STARTALIGN; @@ -1619,12 +1620,13 @@ static void pdev_assign_fixed_resources(struct pci_= dev *dev) pci_dev_for_each_resource(dev, r) { struct pci_bus *b; =20 - if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) || + if (resource_assigned(r) || + !(r->flags & IORESOURCE_PCI_FIXED) || !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) continue; =20 b =3D dev->bus; - while (b && !r->parent) { + while (b && !resource_assigned(r)) { assign_fixed_resource_on_bus(b, r); b =3D b->parent; } @@ -1680,7 +1682,7 @@ static void pci_claim_device_resources(struct pci_dev= *dev) for (i =3D 0; i < PCI_BRIDGE_RESOURCES; i++) { struct resource *r =3D &dev->resource[i]; =20 - if (!r->flags || r->parent) + if (!r->flags || resource_assigned(r)) continue; =20 pci_claim_resource(dev, i); @@ -1694,7 +1696,7 @@ static void pci_claim_bridge_resources(struct pci_dev= *dev) for (i =3D PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { struct resource *r =3D &dev->resource[i]; =20 - if (!r->flags || r->parent) + if (!r->flags || resource_assigned(r)) continue; =20 pci_claim_bridge_resource(dev, i); @@ -1777,7 +1779,7 @@ static void pci_bridge_release_resources(struct pci_b= us *bus, struct pci_dev *dev =3D bus->self; int idx, ret; =20 - if (!b_win->parent) + if (!resource_assigned(b_win)) return; =20 idx =3D pci_resource_num(dev, b_win); @@ -1973,7 +1975,7 @@ static void adjust_bridge_window(struct pci_dev *brid= ge, struct resource *res, { resource_size_t add_size, size =3D resource_size(res); =20 - if (res->parent) + if (resource_assigned(res)) return; =20 if (!new_size) @@ -2063,7 +2065,7 @@ static void pci_bus_distribute_available_resources(st= ruct pci_bus *bus, * window. */ align =3D pci_resource_alignment(bridge, res); - if (!res->parent && align) + if (!resource_assigned(res) && align) available[i].start =3D min(ALIGN(available[i].start, align), available[i].end + 1); =20 @@ -2512,7 +2514,7 @@ int pci_do_resource_release_and_resize(struct pci_dev= *pdev, int resno, int size =20 i =3D pci_resource_num(dev, res); =20 - if (res->parent) { + if (resource_assigned(res)) { release_child_resources(res); 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X-CSE-ConnectionGUID: e2woBAT7TLCJfzf4T47S1Q== X-CSE-MsgGUID: jRf/bRfrT66zso1QEiAN4w== X-IronPort-AV: E=McAfee;i="6800,10657,11647"; a="67880700" X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="67880700" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:42:58 -0800 X-CSE-ConnectionGUID: SDL0FqBqQCW/Gd2WS+a5Kg== X-CSE-MsgGUID: JsAjfUJ0Tv+VdSUfmQqIAQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="198497113" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:42:55 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 16/23] PCI: Properly prefix struct pci_dev_resource handling functions Date: Fri, 19 Dec 2025 19:40:29 +0200 Message-Id: <20251219174036.16738-17-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable setup-bus.c has static functions for handling struct pci_dev_resource related operation which have no prefixes. Add prefixes to those function names as add_to_list() will be needed in another file by an upcoming change. Signed-off-by: Ilpo J=C3=A4rvinen --- I'm open to naming these with a different prefix, as "devres" is already used in the other context. The current name comes from the struct pci_dev_resource that holds information during resource fitting and assignment algorithm (mainly old resource addresses, optional size). --- drivers/pci/setup-bus.c | 114 +++++++++++++++++++++------------------- 1 file changed, 61 insertions(+), 53 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index bbc615d85c88..3cc26fede31a 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -49,7 +49,7 @@ struct pci_dev_resource { unsigned long flags; }; =20 -static void free_list(struct list_head *head) +static void pci_dev_res_free_list(struct list_head *head) { struct pci_dev_resource *dev_res, *tmp; =20 @@ -60,16 +60,17 @@ static void free_list(struct list_head *head) } =20 /** - * add_to_list() - Add a new resource tracker to the list + * pci_dev_res_add_to_list() - Add a new resource tracker to the list * @head: Head of the list * @dev: Device to which the resource belongs * @res: Resource to be tracked * @add_size: Additional size to be optionally added to the resource * @min_align: Minimum memory window alignment */ -static int add_to_list(struct list_head *head, struct pci_dev *dev, - struct resource *res, resource_size_t add_size, - resource_size_t min_align) +static int pci_dev_res_add_to_list(struct list_head *head, struct pci_dev = *dev, + struct resource *res, + resource_size_t add_size, + resource_size_t min_align) { struct pci_dev_resource *tmp; =20 @@ -90,7 +91,8 @@ static int add_to_list(struct list_head *head, struct pci= _dev *dev, return 0; } =20 -static void remove_from_list(struct list_head *head, struct resource *res) +static void pci_dev_res_remove_from_list(struct list_head *head, + struct resource *res) { struct pci_dev_resource *dev_res, *tmp; =20 @@ -125,7 +127,7 @@ static resource_size_t get_res_add_size(struct list_hea= d *head, return dev_res ? dev_res->add_size : 0; } =20 -static void restore_dev_resource(struct pci_dev_resource *dev_res) +static void pci_dev_res_restore(struct pci_dev_resource *dev_res) { struct resource *res =3D dev_res->res; struct pci_dev *dev =3D dev_res->dev; @@ -498,9 +500,9 @@ static void assign_requested_resources_sorted(struct li= st_head *head, =20 if (pci_assign_resource(dev, idx)) { if (fail_head) { - add_to_list(fail_head, dev, res, - 0 /* don't care */, - 0 /* don't care */); + pci_dev_res_add_to_list(fail_head, dev, res, + 0 /* don't care */, + 0 /* don't care */); } } } @@ -612,8 +614,9 @@ static void __assign_resources_sorted(struct list_head = *head, =20 /* Save original start, end, flags etc at first */ list_for_each_entry(dev_res, head, list) { - if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { - free_list(&save_head); + if (pci_dev_res_add_to_list(&save_head, dev_res->dev, + dev_res->res, 0, 0)) { + pci_dev_res_free_list(&save_head); goto assign; } } @@ -666,8 +669,9 @@ static void __assign_resources_sorted(struct list_head = *head, if (list_empty(&local_fail_head)) { /* Remove head list from realloc_head list */ list_for_each_entry(dev_res, head, list) - remove_from_list(realloc_head, dev_res->res); - free_list(&save_head); + pci_dev_res_remove_from_list(realloc_head, + dev_res->res); + pci_dev_res_free_list(&save_head); goto out; } =20 @@ -680,10 +684,10 @@ static void __assign_resources_sorted(struct list_hea= d *head, if (resource_assigned(res)) continue; =20 - restore_dev_resource(save_res); + pci_dev_res_restore(save_res); } - free_list(&local_fail_head); - free_list(&save_head); + pci_dev_res_free_list(&local_fail_head); + pci_dev_res_free_list(&save_head); goto out; } =20 @@ -696,26 +700,26 @@ static void __assign_resources_sorted(struct list_hea= d *head, if (resource_assigned(res) && !pci_need_to_release(fail_type, res)) { /* Remove it from realloc_head list */ - remove_from_list(realloc_head, res); - remove_from_list(&save_head, res); + pci_dev_res_remove_from_list(realloc_head, res); + pci_dev_res_remove_from_list(&save_head, res); list_del(&dev_res->list); kfree(dev_res); } } =20 - free_list(&local_fail_head); + pci_dev_res_free_list(&local_fail_head); /* Release assigned resource */ list_for_each_entry(dev_res, head, list) { res =3D dev_res->res; dev =3D dev_res->dev; =20 pci_release_resource(dev, pci_resource_num(dev, res)); - restore_dev_resource(dev_res); + pci_dev_res_restore(dev_res); } /* Restore start/end/flags from saved list */ list_for_each_entry(save_res, &save_head, list) - restore_dev_resource(save_res); - free_list(&save_head); + pci_dev_res_restore(save_res); + pci_dev_res_free_list(&save_head); =20 /* Satisfy the must-have resource requests */ assign_requested_resources_sorted(head, NULL, false); @@ -734,15 +738,15 @@ static void __assign_resources_sorted(struct list_hea= d *head, continue; =20 if (fail_head) { - add_to_list(fail_head, dev, res, - 0 /* don't care */, - 0 /* don't care */); + pci_dev_res_add_to_list(fail_head, dev, res, + 0 /* don't care */, + 0 /* don't care */); } =20 reset_resource(dev, res); } =20 - free_list(head); + pci_dev_res_free_list(head); } =20 static void pdev_assign_resources_sorted(struct pci_dev *dev, @@ -1183,8 +1187,8 @@ static void pbus_size_io(struct pci_bus *bus, resourc= e_size_t add_size, b_res->flags |=3D IORESOURCE_STARTALIGN; if (bus->self && size1 > size0 && realloc_head) { b_res->flags &=3D ~IORESOURCE_DISABLED; - add_to_list(realloc_head, bus->self, b_res, size1-size0, - min_align); + pci_dev_res_add_to_list(realloc_head, bus->self, b_res, + size1 - size0, min_align); pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n", b_res, &bus->busn_res, (unsigned long long) size1 - size0); @@ -1293,7 +1297,7 @@ static bool pbus_size_mem_optional(struct pci_dev *de= v, int resno, } =20 /* Put SRIOV requested res to the optional list */ - add_to_list(realloc_head, dev, res, 0, align); + pci_dev_res_add_to_list(realloc_head, dev, res, 0, align); *children_add_size +=3D r_size; *add_align =3D max(align, *add_align); =20 @@ -1411,7 +1415,8 @@ static void pbus_size_mem(struct pci_bus *bus, struct= resource *b_res, if (bus->self && realloc_head && (size1 > size0 || add_align > min_align)= ) { b_res->flags &=3D ~IORESOURCE_DISABLED; add_size =3D size1 > size0 ? size1 - size0 : 0; - add_to_list(realloc_head, bus->self, b_res, add_size, add_align); + pci_dev_res_add_to_list(realloc_head, bus->self, b_res, + add_size, add_align); pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %l= lx\n", b_res, &bus->busn_res, (unsigned long long) add_size, @@ -1447,8 +1452,9 @@ static void pci_bus_size_cardbus(struct pci_bus *bus, b_res->flags |=3D IORESOURCE_IO | IORESOURCE_STARTALIGN; if (realloc_head) { b_res->end -=3D pci_cardbus_io_size; - add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, - pci_cardbus_io_size); + pci_dev_res_add_to_list(realloc_head, bridge, b_res, + pci_cardbus_io_size, + pci_cardbus_io_size); } =20 handle_b_res_1: @@ -1459,8 +1465,9 @@ static void pci_bus_size_cardbus(struct pci_bus *bus, b_res->flags |=3D IORESOURCE_IO | IORESOURCE_STARTALIGN; if (realloc_head) { b_res->end -=3D pci_cardbus_io_size; - add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, - pci_cardbus_io_size); + pci_dev_res_add_to_list(realloc_head, bridge, b_res, + pci_cardbus_io_size, + pci_cardbus_io_size); } =20 handle_b_res_2: @@ -1494,8 +1501,9 @@ static void pci_bus_size_cardbus(struct pci_bus *bus, IORESOURCE_STARTALIGN; if (realloc_head) { b_res->end -=3D pci_cardbus_mem_size; - add_to_list(realloc_head, bridge, b_res, - pci_cardbus_mem_size, pci_cardbus_mem_size); + pci_dev_res_add_to_list(realloc_head, bridge, b_res, + pci_cardbus_mem_size, + pci_cardbus_mem_size); } =20 /* Reduce that to half */ @@ -1510,8 +1518,8 @@ static void pci_bus_size_cardbus(struct pci_bus *bus, b_res->flags |=3D IORESOURCE_MEM | IORESOURCE_STARTALIGN; if (realloc_head) { b_res->end -=3D b_res_3_size; - add_to_list(realloc_head, bridge, b_res, b_res_3_size, - pci_cardbus_mem_size); + pci_dev_res_add_to_list(realloc_head, bridge, b_res, + b_res_3_size, pci_cardbus_mem_size); } =20 handle_done: @@ -1997,7 +2005,7 @@ static void adjust_bridge_window(struct pci_dev *brid= ge, struct resource *res, =20 /* If the resource is part of the add_list, remove it now */ if (add_list) - remove_from_list(add_list, res); + pci_dev_res_remove_from_list(add_list, res); } =20 static void remove_dev_resource(struct resource *avail, struct pci_dev *de= v, @@ -2249,9 +2257,9 @@ static void pci_prepare_next_assign_round(struct list= _head *fail_head, =20 /* Restore size and flags */ list_for_each_entry(fail_res, fail_head, list) - restore_dev_resource(fail_res); + pci_dev_res_restore(fail_res); =20 - free_list(fail_head); + pci_dev_res_free_list(fail_head); } =20 /* @@ -2298,7 +2306,7 @@ void pci_assign_unassigned_root_bus_resources(struct = pci_bus *bus) /* Depth last, allocate resources and update the hardware. */ __pci_bus_assign_resources(bus, add_list, &fail_head); if (WARN_ON_ONCE(add_list && !list_empty(add_list))) - free_list(add_list); + pci_dev_res_free_list(add_list); tried_times++; =20 /* Any device complain? */ @@ -2313,7 +2321,7 @@ void pci_assign_unassigned_root_bus_resources(struct = pci_bus *bus) dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting= with pci=3Drealloc=3Doff\n"); } - free_list(&fail_head); + pci_dev_res_free_list(&fail_head); break; } =20 @@ -2361,7 +2369,7 @@ void pci_assign_unassigned_bridge_resources(struct pc= i_dev *bridge) =20 __pci_bridge_assign_resources(bridge, &add_list, &fail_head); if (WARN_ON_ONCE(!list_empty(&add_list))) - free_list(&add_list); + pci_dev_res_free_list(&add_list); tried_times++; =20 if (list_empty(&fail_head)) @@ -2369,7 +2377,7 @@ void pci_assign_unassigned_bridge_resources(struct pc= i_dev *bridge) =20 if (tried_times >=3D 2) { /* Still fail, don't need to try more */ - free_list(&fail_head); + pci_dev_res_free_list(&fail_head); break; } =20 @@ -2410,7 +2418,7 @@ static int pbus_reassign_bridge_resources(struct pci_= bus *bus, struct resource * =20 /* Ignore BARs which are still in use */ if (!res->child) { - ret =3D add_to_list(saved, bridge, res, 0, 0); + ret =3D pci_dev_res_add_to_list(saved, bridge, res, 0, 0); if (ret) return ret; =20 @@ -2432,12 +2440,12 @@ static int pbus_reassign_bridge_resources(struct pc= i_bus *bus, struct resource * __pci_bus_size_bridges(bridge->subordinate, &added); __pci_bridge_assign_resources(bridge, &added, &failed); if (WARN_ON_ONCE(!list_empty(&added))) - free_list(&added); + pci_dev_res_free_list(&added); =20 if (!list_empty(&failed)) { if (pci_required_resource_failed(&failed, type)) ret =3D -ENOSPC; - free_list(&failed); + pci_dev_res_free_list(&failed); if (ret) return ret; =20 @@ -2485,7 +2493,7 @@ int pci_do_resource_release_and_resize(struct pci_dev= *pdev, int resno, int size if (b_win !=3D pbus_select_window(bus, r)) continue; =20 - ret =3D add_to_list(&saved, pdev, r, 0, 0); + ret =3D pci_dev_res_add_to_list(&saved, pdev, r, 0, 0); if (ret) goto restore; pci_release_resource(pdev, i); @@ -2503,7 +2511,7 @@ int pci_do_resource_release_and_resize(struct pci_dev= *pdev, int resno, int size =20 out: up_read(&pci_bus_sem); - free_list(&saved); + pci_dev_res_free_list(&saved); return ret; =20 restore: @@ -2519,7 +2527,7 @@ int pci_do_resource_release_and_resize(struct pci_dev= *pdev, int resno, int size pci_release_resource(dev, i); } =20 - restore_dev_resource(dev_res); + pci_dev_res_restore(dev_res); =20 ret =3D pci_claim_resource(dev, i); if (ret) @@ -2551,6 +2559,6 @@ void pci_assign_unassigned_bus_resources(struct pci_b= us *bus) up_read(&pci_bus_sem); __pci_bus_assign_resources(bus, &add_list, NULL); if (WARN_ON_ONCE(!list_empty(&add_list))) - free_list(&add_list); + pci_dev_res_free_list(&add_list); } EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources); --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B4BB3451D7; Fri, 19 Dec 2025 17:43:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="67880709" X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="67880709" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:43:07 -0800 X-CSE-ConnectionGUID: eruT82EtR+WEsyWrb6aoMA== X-CSE-MsgGUID: EYlxlf+wQfCgePlp+0hrCg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="198497122" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:43:03 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 17/23] PCI: Separate cardbus setup & build it only with CONFIG_CARDBUS Date: Fri, 19 Dec 2025 19:40:30 +0200 Message-Id: <20251219174036.16738-18-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable PCI bridge window setup code includes special code to handle CardBus bridges. CardBus has long since fallen out of favor and modern systems have no use for it. Move CardBus setup code into own file and use existing CONFIG_CARDBUS for deciding whether it should be built or not. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/Makefile | 1 + drivers/pci/pci.h | 23 ++++- drivers/pci/setup-bus.c | 171 ++-------------------------------- drivers/pci/setup-cardbus.c | 167 +++++++++++++++++++++++++++++++++ drivers/pcmcia/yenta_socket.c | 2 +- include/linux/pci.h | 6 +- 6 files changed, 202 insertions(+), 168 deletions(-) create mode 100644 drivers/pci/setup-cardbus.c diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index e10cfe5a280b..8922f90afecb 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_PCI_TSM) +=3D tsm.o obj-$(CONFIG_PCI_DYNAMIC_OF_NODES) +=3D of_property.o obj-$(CONFIG_PCI_NPEM) +=3D npem.o obj-$(CONFIG_PCIE_TPH) +=3D tph.o +obj-$(CONFIG_CARDBUS) +=3D setup-cardbus.o =20 # Endpoint library must be initialized before its users obj-$(CONFIG_PCI_ENDPOINT) +=3D endpoint/ diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index c27144af550f..2340e9df05c2 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -379,6 +379,23 @@ extern unsigned long pci_hotplug_bus_size; extern unsigned long pci_cardbus_io_size; extern unsigned long pci_cardbus_mem_size; =20 +#ifdef CONFIG_CARDBUS +unsigned long pci_cardbus_resource_alignment(struct resource *res); +int pci_bus_size_cardbus_bridge(struct pci_bus *bus, + struct list_head *realloc_head); + +#else +static inline unsigned long pci_cardbus_resource_alignment(struct resource= *res) +{ + return 0; +} +static inline int pci_bus_size_cardbus_bridge(struct pci_bus *bus, + struct list_head *realloc_head) +{ + return -EOPNOTSUPP; +} +#endif /* CONFIG_CARDBUS */ + /** * pci_match_one_device - Tell if a PCI device structure has a matching * PCI device id structure @@ -440,6 +457,10 @@ void __pci_size_stdbars(struct pci_dev *dev, int count, int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, struct resource *res, unsigned int reg, u32 *sizes); void pci_configure_ari(struct pci_dev *dev); + +int pci_dev_res_add_to_list(struct list_head *head, struct pci_dev *dev, + struct resource *res, resource_size_t add_size, + resource_size_t min_align); void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head); void __pci_bus_assign_resources(const struct pci_bus *bus, @@ -929,8 +950,6 @@ static inline void pci_suspend_ptm(struct pci_dev *dev)= { } static inline void pci_resume_ptm(struct pci_dev *dev) { } #endif =20 -unsigned long pci_cardbus_resource_alignment(struct resource *); - static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, struct resource *res) { diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 3cc26fede31a..e680f75a5b5e 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -67,10 +67,9 @@ static void pci_dev_res_free_list(struct list_head *head) * @add_size: Additional size to be optionally added to the resource * @min_align: Minimum memory window alignment */ -static int pci_dev_res_add_to_list(struct list_head *head, struct pci_dev = *dev, - struct resource *res, - resource_size_t add_size, - resource_size_t min_align) +int pci_dev_res_add_to_list(struct list_head *head, struct pci_dev *dev, + struct resource *res, resource_size_t add_size, + resource_size_t min_align) { struct pci_dev_resource *tmp; =20 @@ -773,61 +772,6 @@ static void pbus_assign_resources_sorted(const struct = pci_bus *bus, __assign_resources_sorted(&head, realloc_head, fail_head); } =20 -void pci_setup_cardbus(struct pci_bus *bus) -{ - struct pci_dev *bridge =3D bus->self; - struct resource *res; - struct pci_bus_region region; - - pci_info(bridge, "CardBus bridge to %pR\n", - &bus->busn_res); - - res =3D bus->resource[0]; - pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (resource_assigned(res) && res->flags & IORESOURCE_IO) { - /* - * The IO resource is allocated a range twice as large as it - * would normally need. This allows us to set both IO regs. - */ - pci_info(bridge, " bridge window %pR\n", res); - pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, - region.start); - pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, - region.end); - } - - res =3D bus->resource[1]; - pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (resource_assigned(res) && res->flags & IORESOURCE_IO) { - pci_info(bridge, " bridge window %pR\n", res); - pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, - region.start); - pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, - region.end); - } - - res =3D bus->resource[2]; - pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { - pci_info(bridge, " bridge window %pR\n", res); - pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, - region.start); - pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, - region.end); - } - - res =3D bus->resource[3]; - pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { - pci_info(bridge, " bridge window %pR\n", res); - pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, - region.start); - pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, - region.end); - } -} -EXPORT_SYMBOL(pci_setup_cardbus); - /* * Initialize bridges with base/limit values we have collected. PCI-to-PCI * Bridge Architecture Specification rev. 1.1 (1998) requires that if there @@ -1424,108 +1368,6 @@ static void pbus_size_mem(struct pci_bus *bus, stru= ct resource *b_res, } } =20 -unsigned long pci_cardbus_resource_alignment(struct resource *res) -{ - if (res->flags & IORESOURCE_IO) - return pci_cardbus_io_size; - if (res->flags & IORESOURCE_MEM) - return pci_cardbus_mem_size; - return 0; -} - -static void pci_bus_size_cardbus(struct pci_bus *bus, - struct list_head *realloc_head) -{ - struct pci_dev *bridge =3D bus->self; - struct resource *b_res; - resource_size_t b_res_3_size =3D pci_cardbus_mem_size * 2; - u16 ctrl; - - b_res =3D &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW]; - if (resource_assigned(b_res)) - goto handle_b_res_1; - /* - * Reserve some resources for CardBus. We reserve a fixed amount - * of bus space for CardBus bridges. - */ - resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); - b_res->flags |=3D IORESOURCE_IO | IORESOURCE_STARTALIGN; - if (realloc_head) { - b_res->end -=3D pci_cardbus_io_size; - pci_dev_res_add_to_list(realloc_head, bridge, b_res, - pci_cardbus_io_size, - pci_cardbus_io_size); - } - -handle_b_res_1: - b_res =3D &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW]; - if (resource_assigned(b_res)) - goto handle_b_res_2; - resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); - b_res->flags |=3D IORESOURCE_IO | IORESOURCE_STARTALIGN; - if (realloc_head) { - b_res->end -=3D pci_cardbus_io_size; - pci_dev_res_add_to_list(realloc_head, bridge, b_res, - pci_cardbus_io_size, - pci_cardbus_io_size); - } - -handle_b_res_2: - /* MEM1 must not be pref MMIO */ - pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); - if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { - ctrl &=3D ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; - pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); - pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); - } - - /* Check whether prefetchable memory is supported by this bridge. */ - pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); - if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { - ctrl |=3D PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; - pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); - pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); - } - - b_res =3D &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW]; - if (resource_assigned(b_res)) - goto handle_b_res_3; - /* - * If we have prefetchable memory support, allocate two regions. - * Otherwise, allocate one region of twice the size. - */ - if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { - resource_set_range(b_res, pci_cardbus_mem_size, - pci_cardbus_mem_size); - b_res->flags |=3D IORESOURCE_MEM | IORESOURCE_PREFETCH | - IORESOURCE_STARTALIGN; - if (realloc_head) { - b_res->end -=3D pci_cardbus_mem_size; - pci_dev_res_add_to_list(realloc_head, bridge, b_res, - pci_cardbus_mem_size, - pci_cardbus_mem_size); - } - - /* Reduce that to half */ - b_res_3_size =3D pci_cardbus_mem_size; - } - -handle_b_res_3: - b_res =3D &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW]; - if (resource_assigned(b_res)) - goto handle_done; - resource_set_range(b_res, pci_cardbus_mem_size, b_res_3_size); - b_res->flags |=3D IORESOURCE_MEM | IORESOURCE_STARTALIGN; - if (realloc_head) { - b_res->end -=3D b_res_3_size; - pci_dev_res_add_to_list(realloc_head, bridge, b_res, - b_res_3_size, pci_cardbus_mem_size); - } - -handle_done: - ; -} - void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc= _head) { struct pci_dev *dev; @@ -1542,7 +1384,8 @@ void __pci_bus_size_bridges(struct pci_bus *bus, stru= ct list_head *realloc_head) =20 switch (dev->hdr_type) { case PCI_HEADER_TYPE_CARDBUS: - pci_bus_size_cardbus(b, realloc_head); + if (pci_bus_size_cardbus_bridge(b, realloc_head)) + continue; break; =20 case PCI_HEADER_TYPE_BRIDGE: @@ -1666,7 +1509,7 @@ void __pci_bus_assign_resources(const struct pci_bus = *bus, break; =20 case PCI_HEADER_TYPE_CARDBUS: - pci_setup_cardbus(b); + pci_setup_cardbus_bridge(b); break; =20 default: @@ -1771,7 +1614,7 @@ static void __pci_bridge_assign_resources(const struc= t pci_dev *bridge, break; =20 case PCI_CLASS_BRIDGE_CARDBUS: - pci_setup_cardbus(b); + pci_setup_cardbus_bridge(b); break; =20 default: diff --git a/drivers/pci/setup-cardbus.c b/drivers/pci/setup-cardbus.c new file mode 100644 index 000000000000..b017a2039fe1 --- /dev/null +++ b/drivers/pci/setup-cardbus.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cardbus bridge setup routines. + */ + +#include +#include +#include + +#include "pci.h" + +unsigned long pci_cardbus_resource_alignment(struct resource *res) +{ + if (res->flags & IORESOURCE_IO) + return pci_cardbus_io_size; + if (res->flags & IORESOURCE_MEM) + return pci_cardbus_mem_size; + return 0; +} + +int pci_bus_size_cardbus_bridge(struct pci_bus *bus, + struct list_head *realloc_head) +{ + struct pci_dev *bridge =3D bus->self; + struct resource *b_res; + resource_size_t b_res_3_size =3D pci_cardbus_mem_size * 2; + u16 ctrl; + + b_res =3D &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW]; + if (resource_assigned(b_res)) + goto handle_b_res_1; + /* + * Reserve some resources for CardBus. We reserve a fixed amount + * of bus space for CardBus bridges. + */ + resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); + b_res->flags |=3D IORESOURCE_IO | IORESOURCE_STARTALIGN; + if (realloc_head) { + b_res->end -=3D pci_cardbus_io_size; + pci_dev_res_add_to_list(realloc_head, bridge, b_res, + pci_cardbus_io_size, + pci_cardbus_io_size); + } + +handle_b_res_1: + b_res =3D &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW]; + if (resource_assigned(b_res)) + goto handle_b_res_2; + resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); + b_res->flags |=3D IORESOURCE_IO | IORESOURCE_STARTALIGN; + if (realloc_head) { + b_res->end -=3D pci_cardbus_io_size; + pci_dev_res_add_to_list(realloc_head, bridge, b_res, + pci_cardbus_io_size, + pci_cardbus_io_size); + } + +handle_b_res_2: + /* MEM1 must not be pref MMIO */ + pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); + if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { + ctrl &=3D ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; + pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); + pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); + } + + /* Check whether prefetchable memory is supported by this bridge. */ + pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); + if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { + ctrl |=3D PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; + pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); + pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); + } + + b_res =3D &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW]; + if (resource_assigned(b_res)) + goto handle_b_res_3; + /* + * If we have prefetchable memory support, allocate two regions. + * Otherwise, allocate one region of twice the size. + */ + if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { + resource_set_range(b_res, pci_cardbus_mem_size, + pci_cardbus_mem_size); + b_res->flags |=3D IORESOURCE_MEM | IORESOURCE_PREFETCH | + IORESOURCE_STARTALIGN; + if (realloc_head) { + b_res->end -=3D pci_cardbus_mem_size; + pci_dev_res_add_to_list(realloc_head, bridge, b_res, + pci_cardbus_mem_size, + pci_cardbus_mem_size); + } + + /* Reduce that to half */ + b_res_3_size =3D pci_cardbus_mem_size; + } + +handle_b_res_3: + b_res =3D &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW]; + if (resource_assigned(b_res)) + goto handle_done; + resource_set_range(b_res, pci_cardbus_mem_size, b_res_3_size); + b_res->flags |=3D IORESOURCE_MEM | IORESOURCE_STARTALIGN; + if (realloc_head) { + b_res->end -=3D b_res_3_size; + pci_dev_res_add_to_list(realloc_head, bridge, b_res, + b_res_3_size, pci_cardbus_mem_size); + } + +handle_done: + return 0; +} + +void pci_setup_cardbus_bridge(struct pci_bus *bus) +{ + struct pci_dev *bridge =3D bus->self; + struct resource *res; + struct pci_bus_region region; + + pci_info(bridge, "CardBus bridge to %pR\n", + &bus->busn_res); + + res =3D bus->resource[0]; + pcibios_resource_to_bus(bridge->bus, ®ion, res); + if (resource_assigned(res) && res->flags & IORESOURCE_IO) { + /* + * The IO resource is allocated a range twice as large as it + * would normally need. This allows us to set both IO regs. + */ + pci_info(bridge, " bridge window %pR\n", res); + pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, + region.start); + pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, + region.end); + } + + res =3D bus->resource[1]; + pcibios_resource_to_bus(bridge->bus, ®ion, res); + if (resource_assigned(res) && res->flags & IORESOURCE_IO) { + pci_info(bridge, " bridge window %pR\n", res); + pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, + region.start); + pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, + region.end); + } + + res =3D bus->resource[2]; + pcibios_resource_to_bus(bridge->bus, ®ion, res); + if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { + pci_info(bridge, " bridge window %pR\n", res); + pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, + region.start); + pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, + region.end); + } + + res =3D bus->resource[3]; + pcibios_resource_to_bus(bridge->bus, ®ion, res); + if (resource_assigned(res) && res->flags & IORESOURCE_MEM) { + pci_info(bridge, " bridge window %pR\n", res); + pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, + region.start); + pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, + region.end); + } +} +EXPORT_SYMBOL(pci_setup_cardbus_bridge); diff --git a/drivers/pcmcia/yenta_socket.c b/drivers/pcmcia/yenta_socket.c index 923ed23570a0..34c4eaee7dfc 100644 --- a/drivers/pcmcia/yenta_socket.c +++ b/drivers/pcmcia/yenta_socket.c @@ -779,7 +779,7 @@ static void yenta_allocate_resources(struct yenta_socke= t *socket) IORESOURCE_MEM, PCI_CB_MEMORY_BASE_1, PCI_CB_MEMORY_LIMIT_1); if (program) - pci_setup_cardbus(socket->dev->subordinate); + pci_setup_cardbus_bridge(socket->dev->subordinate); } =20 =20 diff --git a/include/linux/pci.h b/include/linux/pci.h index 864775651c6f..ddec80c92816 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1243,7 +1243,11 @@ void pci_stop_and_remove_bus_device(struct pci_dev *= dev); void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); void pci_stop_root_bus(struct pci_bus *bus); void pci_remove_root_bus(struct pci_bus *bus); -void pci_setup_cardbus(struct pci_bus *bus); +#ifdef CONFIG_CARDBUS +void pci_setup_cardbus_bridge(struct pci_bus *bus); +#else +static inline void pci_setup_cardbus_bridge(struct pci_bus *bus) { } +#endif void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); void pci_sort_breadthfirst(void); #define dev_is_pci(d) ((d)->bus =3D=3D &pci_bus_type) --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9420D346AF2; Fri, 19 Dec 2025 17:43:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166208; cv=none; b=jWLfu5E4MI+xrK6LW42DqcOASwfJtybap/ScGm/p/c+VMdyjP5m0junzGC3EsyVOEr4p5v/J5ljFZvGRraYN5bm2wN1XDKCwN92AL9iXyoFe7tuhVZjXcXj6D3ly/wFek+kbRHqFnRVW1EKOyMElsS/KUVxSUM9zk7sEtcPvbPw= ARC-Message-Signature: i=1; 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d="scan'208";a="198066163" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:43:12 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 18/23] PCI: Handle CardBus specific params in setup-cardbus.c Date: Fri, 19 Dec 2025 19:40:31 +0200 Message-Id: <20251219174036.16738-19-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Move cardbus window sizing parameters to setup-cardbus.c that contains all the other CardBus code. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/pci.c | 14 +++----------- drivers/pci/pci.h | 4 ++-- drivers/pci/setup-cardbus.c | 21 +++++++++++++++++++++ 3 files changed, 26 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 13dbb405dc31..85c22f30e20a 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -99,12 +99,6 @@ bool pci_reset_supported(struct pci_dev *dev) int pci_domains_supported =3D 1; #endif =20 -#define DEFAULT_CARDBUS_IO_SIZE (256) -#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) -/* pci=3Dcbmemsize=3DnnM,cbiosize=3Dnn can override this */ -unsigned long pci_cardbus_io_size =3D DEFAULT_CARDBUS_IO_SIZE; -unsigned long pci_cardbus_mem_size =3D DEFAULT_CARDBUS_MEM_SIZE; - #define DEFAULT_HOTPLUG_IO_SIZE (256) #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024) #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024) @@ -6630,7 +6624,9 @@ static int __init pci_setup(char *str) if (k) *k++ =3D 0; if (*str && (str =3D pcibios_setup(str)) && *str) { - if (!strcmp(str, "nomsi")) { + if (!pci_setup_cardbus(str)) { + /* Function handled the parameters */ + } else if (!strcmp(str, "nomsi")) { pci_no_msi(); } else if (!strncmp(str, "noats", 5)) { pr_info("PCIe: ATS is disabled\n"); @@ -6649,10 +6645,6 @@ static int __init pci_setup(char *str) pcie_ari_disabled =3D true; } else if (!strncmp(str, "notph", 5)) { pci_no_tph(); - } else if (!strncmp(str, "cbiosize=3D", 9)) { - pci_cardbus_io_size =3D memparse(str + 9, &str); - } else if (!strncmp(str, "cbmemsize=3D", 10)) { - pci_cardbus_mem_size =3D memparse(str + 10, &str); } else if (!strncmp(str, "resource_alignment=3D", 19)) { resource_alignment_param =3D str + 19; } else if (!strncmp(str, "ecrc=3D", 5)) { diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 2340e9df05c2..dbea5db07959 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -376,13 +376,12 @@ extern unsigned long pci_hotplug_io_size; extern unsigned long pci_hotplug_mmio_size; extern unsigned long pci_hotplug_mmio_pref_size; extern unsigned long pci_hotplug_bus_size; -extern unsigned long pci_cardbus_io_size; -extern unsigned long pci_cardbus_mem_size; =20 #ifdef CONFIG_CARDBUS unsigned long pci_cardbus_resource_alignment(struct resource *res); int pci_bus_size_cardbus_bridge(struct pci_bus *bus, struct list_head *realloc_head); +int pci_setup_cardbus(char *str); =20 #else static inline unsigned long pci_cardbus_resource_alignment(struct resource= *res) @@ -394,6 +393,7 @@ static inline int pci_bus_size_cardbus_bridge(struct pc= i_bus *bus, { return -EOPNOTSUPP; } +static inline int pci_setup_cardbus(char *str) { return -ENOENT; } #endif /* CONFIG_CARDBUS */ =20 /** diff --git a/drivers/pci/setup-cardbus.c b/drivers/pci/setup-cardbus.c index b017a2039fe1..93a2b43c637b 100644 --- a/drivers/pci/setup-cardbus.c +++ b/drivers/pci/setup-cardbus.c @@ -3,12 +3,20 @@ * Cardbus bridge setup routines. */ =20 +#include #include #include +#include #include =20 #include "pci.h" =20 +#define DEFAULT_CARDBUS_IO_SIZE SZ_256 +#define DEFAULT_CARDBUS_MEM_SIZE SZ_64M +/* pci=3Dcbmemsize=3DnnM,cbiosize=3Dnn can override this */ +static unsigned long pci_cardbus_io_size =3D DEFAULT_CARDBUS_IO_SIZE; +static unsigned long pci_cardbus_mem_size =3D DEFAULT_CARDBUS_MEM_SIZE; + unsigned long pci_cardbus_resource_alignment(struct resource *res) { if (res->flags & IORESOURCE_IO) @@ -165,3 +173,16 @@ void pci_setup_cardbus_bridge(struct pci_bus *bus) } } EXPORT_SYMBOL(pci_setup_cardbus_bridge); + +int pci_setup_cardbus(char *str) +{ + if (!strncmp(str, "cbiosize=3D", 9)) { + pci_cardbus_io_size =3D memparse(str + 9, &str); + return 0; + } else if (!strncmp(str, "cbmemsize=3D", 10)) { + pci_cardbus_mem_size =3D memparse(str + 10, &str); + return 0; + } + + return -ENOENT; +} --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80028346E44; Fri, 19 Dec 2025 17:43:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166210; 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d="scan'208";a="78764461" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:43:26 -0800 X-CSE-ConnectionGUID: wnpqMUtcQtevZwT1v63keg== X-CSE-MsgGUID: cN1QY9FmSaiRqFYsWXVP3g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="198066198" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:43:21 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 19/23] PCI: Use scnprintf() instead of sprintf() Date: Fri, 19 Dec 2025 19:40:32 +0200 Message-Id: <20251219174036.16738-20-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Using sprintf() is deprecated as it does not do proper size checks. While the code in pci_scan_bridge_extend() is safe wrt. overwriting the destination buffer, use scnprintf() to not promote use of a deprecated sprint() (and allow eventually removing it from the kernel). Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/probe.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 41183aed8f5d..5d8ce6381dff 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -1573,9 +1574,9 @@ static int pci_scan_bridge_extend(struct pci_bus *bus= , struct pci_dev *dev, pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); } =20 - sprintf(child->name, - (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), - pci_domain_nr(bus), child->number); + scnprintf(child->name, sizeof(child->name), + (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), + pci_domain_nr(bus), child->number); =20 /* Check that all devices are accessible */ while (bus->parent) { --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86B9234A3D0; Fri, 19 Dec 2025 17:43:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166213; cv=none; b=OvMjjERkKFyIc8rnkmOX7xWI0H0a6MDAysoeqNtCJHLCpwdwtr23OYrOo+VRtspH7POdkSWb+TsnAQ/I3VJ/cSwrU96oElxjbAbjhNSzkYWYE8OBXKrm4HzmGW+Of3ng8DDnky8zoWiS7BKx2v71hK6TWPt0m/i4Y5eDsMGlh+M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166213; c=relaxed/simple; bh=9OXK7oj9p5RkvtU+sQOiWMUrwzzLE6Ndnnatux4N3+k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=puxjdBjhETlhAPHvmEaLlStZiYzJ2aZVjKoyHnzq7AEwX+Hx1cxQwEzt9qbg/mNHGdRsGOjQLyLuYBt8wUuoxj0eBCCwg17R6AlALsOUNs3UXgTc0gGw4LIcTuVPX1G3fM6dl0VAQAn8PuZYqWUNed2aUwixpgetrhyhYFZRQCU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QRc/LWu0; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QRc/LWu0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1766166211; x=1797702211; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9OXK7oj9p5RkvtU+sQOiWMUrwzzLE6Ndnnatux4N3+k=; b=QRc/LWu0thSbS1J8fnu6HEQPDT5vXJDSnJ6dGmfc+PD5kOpmFfp1jnwd 22OWPLMIDhhxYkKhCXM7T/f8wwTPSlsgz4dHMv6TxWwR1+ItvEzBOqrlj nxokiUyule0o1MpEydN3090QAdgYezpMEB3SmN0FC4OkjkJozCswtY6Er aD+ddEHkOrFdEc+MkTJ97WadUP2CJqIwd+RfL10sWRgbK+Q1OuVwgwPAp Zp49qUdJa1Hbenv19rJUhPlBzv9+7vlLTmlu4V6DSLjEnmt4DJCKpECXQ 77yCGnadAjROD4q+5HHAB6dHZDLaoWjTf23SzvlviSu5T4ZzbWoF45lug g==; X-CSE-ConnectionGUID: r/BZVR7pQKmenu0MvFhAug== X-CSE-MsgGUID: 4/U4kRTSTc+hlxBzTNJM5Q== X-IronPort-AV: E=McAfee;i="6800,10657,11647"; a="78764464" X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="78764464" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:43:31 -0800 X-CSE-ConnectionGUID: LyhCpZhsRQWSVlMCeeb09w== X-CSE-MsgGUID: Kl1tojkpTBKXwwGi+7LBig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="198066243" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:43:29 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 20/23] PCI: Add Bus Number + Secondary Latency Timer as dword fields Date: Fri, 19 Dec 2025 19:40:33 +0200 Message-Id: <20251219174036.16738-21-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable uapi/linux/pci_regs.h defines Primary/Secondary/Subordinate Bus Numbers and Secondary Latency Timer (PCIe r7.0, sec. 7.5.1.3) as byte register offsets but in practice the code may read/write the entire dword. In the lack of defines to handle the dword fields, the code ends up using literals which are not as easy to read. Add dword field masks for the Bus Number and Secondary Latency Timer fields. Signed-off-by: Ilpo J=C3=A4rvinen --- include/uapi/linux/pci_regs.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 3add74ae2594..8be55ece2a21 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -132,6 +132,11 @@ #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interfac= e */ +/* Masks for dword-sized processing of Bus Number and Sec Latency Timer fi= elds */ +#define PCI_PRIMARY_BUS_MASK 0x000000ff +#define PCI_SECONDARY_BUS_MASK 0x0000ff00 +#define PCI_SUBORDINATE_BUS_MASK 0x00ff0000 +#define PCI_SEC_LATENCY_TIMER_MASK 0xff000000 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ #define PCI_IO_LIMIT 0x1d #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D67134B43D; Fri, 19 Dec 2025 17:43:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166221; cv=none; b=K9HTKh/L7Sj/9L4TN/0o6BebItq9xj7lytfED/tgh3X18AazBzTxvI1o8GWYO15yRaTzy1X5lSH4lA0gtRfwCFftS+1L4WL0jaBtl/Ya74byhgviAbGbYDvqHUzodomIEVypehKeju0g5dizOILrRyG+KcKBJCp6ujT3LMBRM3c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166221; c=relaxed/simple; bh=Hh2MVJQRLsQAGxUX6ZiAqbTDSFXBiN+yB+eNqilMsjk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=aW+baJWPF11nsunXXApirT64X1srIvrVw4s9TVcAxGPKrSwlCSrWD16Ew8zmyFyUFeuBZ9zun+cyP2faQfEQ2tSEKkGQ8kzrVKPOpx4byNzxU33RHteRJoC46wRxP1EZw/TtuDWeKi9nUoNsy9NHYd0MHcVhHlE/XDPsyOpLIb0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=P/3mopGl; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="P/3mopGl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1766166220; x=1797702220; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Hh2MVJQRLsQAGxUX6ZiAqbTDSFXBiN+yB+eNqilMsjk=; b=P/3mopGlxP5LSIRRAVWe2TPacS2sFXda6HtcQvTkB6x87DMDO5i74+wm iyJPxBszMXEkk1Nl3T11aSzth0Z41nmylrtCWufCMKl9q48JW6Cl/HbL0 mlTPqxo3UmK4JLIvAkWOmoKXLZ2q3dOz44mK2FysvAefsQR3OT1xlbZKW ArG3xzHZJtOtG1UfbJfokIn2Xf79wmHzYfAeH2KQKrzuzxBKquuvleYUL iEG19HNzL9s+NGEZCpNIgTyeXLrIb8z4tdGU/DZM8Z99+aBVvUjdJIhEC BtvktHpDKdwnkePH5UNe3r7s3icdB5mqcNsuL14ny0ALp7bHUwEjZLwqR A==; X-CSE-ConnectionGUID: O85SDRhMTLmBKlv7z/X7hg== X-CSE-MsgGUID: /pUwTPcqQE+F5M5+rjrovA== X-IronPort-AV: E=McAfee;i="6800,10657,11647"; a="78764479" X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="78764479" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:43:39 -0800 X-CSE-ConnectionGUID: VC88LqgnQ+qaBleWJhyL+Q== X-CSE-MsgGUID: ez3t73HbQEWQRlYb2Ptw3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="198066258" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:43:37 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 21/23] PCI: Convert to use Bus Number field defines Date: Fri, 19 Dec 2025 19:40:34 +0200 Message-Id: <20251219174036.16738-22-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Convert literals for Primary/Secondary/Subordinate Bus Numbers to use the field defines to improve code readability. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/probe.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 5d8ce6381dff..1781a0a39f4a 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -526,8 +526,8 @@ static void pci_read_bridge_windows(struct pci_dev *bri= dge) =20 pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses); res.flags =3D IORESOURCE_BUS; - res.start =3D (buses >> 8) & 0xff; - res.end =3D (buses >> 16) & 0xff; + res.start =3D FIELD_GET(PCI_SECONDARY_BUS_MASK, buses); + res.end =3D FIELD_GET(PCI_SUBORDINATE_BUS_MASK, buses); pci_info(bridge, "PCI bridge to %pR%s\n", &res, bridge->transparent ? " (subtractive decode)" : ""); =20 @@ -1395,9 +1395,9 @@ static int pci_scan_bridge_extend(struct pci_bus *bus= , struct pci_dev *dev, pm_runtime_get_sync(&dev->dev); =20 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); - primary =3D buses & 0xFF; - secondary =3D (buses >> 8) & 0xFF; - subordinate =3D (buses >> 16) & 0xFF; + primary =3D FIELD_GET(PCI_PRIMARY_BUS_MASK, buses); + secondary =3D FIELD_GET(PCI_SECONDARY_BUS_MASK, buses); + subordinate =3D FIELD_GET(PCI_SUBORDINATE_BUS_MASK, buses); =20 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", secondary, subordinate, pass); @@ -1478,7 +1478,7 @@ static int pci_scan_bridge_extend(struct pci_bus *bus= , struct pci_dev *dev, * ranges. */ pci_write_config_dword(dev, PCI_PRIMARY_BUS, - buses & ~0xffffff); + buses & PCI_SEC_LATENCY_TIMER_MASK); goto out; } =20 @@ -1509,18 +1509,19 @@ static int pci_scan_bridge_extend(struct pci_bus *b= us, struct pci_dev *dev, if (available_buses) available_buses--; =20 - buses =3D (buses & 0xff000000) - | ((unsigned int)(child->primary) << 0) - | ((unsigned int)(child->busn_res.start) << 8) - | ((unsigned int)(child->busn_res.end) << 16); + buses =3D (buses & PCI_SEC_LATENCY_TIMER_MASK) | + FIELD_PREP(PCI_PRIMARY_BUS_MASK, child->primary) | + FIELD_PREP(PCI_SECONDARY_BUS_MASK, child->busn_res.start) | + FIELD_PREP(PCI_SUBORDINATE_BUS_MASK, child->busn_res.end); =20 /* * yenta.c forces a secondary latency timer of 176. * Copy that behaviour here. */ if (is_cardbus) { - buses &=3D ~0xff000000; - buses |=3D CARDBUS_LATENCY_TIMER << 24; + buses &=3D ~PCI_SEC_LATENCY_TIMER_MASK; + buses |=3D FIELD_PREP(PCI_SEC_LATENCY_TIMER_MASK, + CARDBUS_LATENCY_TIMER); } =20 /* We need to blast all three values with a single write */ --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1E5C349B1B; Fri, 19 Dec 2025 17:43:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; 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a="68174101" X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="68174101" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:43:46 -0800 X-CSE-ConnectionGUID: EIl401OETwWVSgvtYBSxRg== X-CSE-MsgGUID: RwHcTT/RS2K8Zu+4+TFFbw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="203072226" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:43:44 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 22/23] PCI: Add pbus_validate_busn() for Bus Number validation Date: Fri, 19 Dec 2025 19:40:35 +0200 Message-Id: <20251219174036.16738-23-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable pci_scan_bridge_extend() validates bus numbers but upcoming changes that separate CardBus code into own function need to call that the same validation. Thus, add pbus_validate_busn for validating the Bus Numbers. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/pci.h | 1 + drivers/pci/probe.c | 33 +++++++++++++++++++++------------ 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index dbea5db07959..b20ff7ef20ff 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -501,6 +501,7 @@ static inline int pci_resource_num(const struct pci_dev= *dev, return resno; } =20 +void pbus_validate_busn(struct pci_bus *bus); struct resource *pbus_select_window(struct pci_bus *bus, const struct resource *res); void pci_reassigndev_resource_alignment(struct pci_dev *dev); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 1781a0a39f4a..49468644e730 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1314,6 +1314,26 @@ static void pci_enable_rrs_sv(struct pci_dev *pdev) =20 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, unsigned int available_buses); + +void pbus_validate_busn(struct pci_bus *bus) +{ + struct pci_bus *upstream =3D bus->parent; + struct pci_dev *bridge =3D bus->self; + + /* Check that all devices are accessible */ + while (upstream->parent) { + if ((bus->busn_res.end > upstream->busn_res.end) || + (bus->number > upstream->busn_res.end) || + (bus->number < upstream->number) || + (bus->busn_res.end < upstream->number)) { + pci_info(bridge, "devices behind bridge are unusable because %pR cannot= be assigned for them\n", + &bus->busn_res); + break; + } + upstream =3D upstream->parent; + } +} + /** * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus * numbers from EA capability. @@ -1579,18 +1599,7 @@ static int pci_scan_bridge_extend(struct pci_bus *bu= s, struct pci_dev *dev, (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), pci_domain_nr(bus), child->number); =20 - /* Check that all devices are accessible */ - while (bus->parent) { - if ((child->busn_res.end > bus->busn_res.end) || - (child->number > bus->busn_res.end) || - (child->number < bus->number) || - (child->busn_res.end < bus->number)) { - dev_info(&dev->dev, "devices behind bridge are unusable because %pR can= not be assigned for them\n", - &child->busn_res); - break; - } - bus =3D bus->parent; - } + pbus_validate_busn(child); =20 out: /* Clear errors in the Secondary Status Register */ --=20 2.39.5 From nobody Sun Feb 8 00:49:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F22EA34D902; Fri, 19 Dec 2025 17:43:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166235; cv=none; b=eTF00UZcal8OzVS7qJx3lr/TvIUIwq5CaRDdO6XUoi7qPK0Rp2L7SW3viaxKoSM5XmaQHAN4wFyb5tNjiZOd1pOL3YaQjLu0d+bItG08kspMYe9ihBL0QUQXhxK1pLRZF5Y1a4/siPfIOZYUoOWljOZyxuVFpjcs1BWI5mk3Xrc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766166235; c=relaxed/simple; bh=KYG4GDajgVVuI+uxlotc+TQZSUuGeQu22he7gV/rcB0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=EH8haode5++BoNzJZWY/SbwJgV6+ga5JxHC5svu40N4fFmDuFyCHxgghAiwSRLCwRwq+FDFTbtcsE4HbDQ7OSe7p8/PNkjK+560I1Hddm1S8zRSvCTBVUG0Jfnu9wEE+M52lNC3BC9Me3DLXkrLVttyIPDMo8vzQLRQrV8J6JC0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cp587MHt; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cp587MHt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1766166234; x=1797702234; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KYG4GDajgVVuI+uxlotc+TQZSUuGeQu22he7gV/rcB0=; b=cp587MHtX6wGvbLXa2UTWvuw/rw2vcuJ0QefqksR89i3LHn0Z5yuFScL B17UDKvbjk/c0O/qp0/meZTArhjYcbje0k/VSGtAxrIJ8VOC3y9v35t98 xwZWrlbx1G5bZ85+FD9kqkLbeQmjXSz3z2WEHM5MC65Imk8TX9ZDdsVRZ LWkDAogQnzu4qJ6HKiiWNnX39Bc7jzuxM7C3izcANuAd0LEar+26fxjv6 drfctqMj0gAx8nSVBzkJi2DZ6EvwF0noGa9WLJ1lxipHp/zvJX29YYQUi HyehnpgSluEnVqTO3tFqb1ZnCOCZVxa/ds/lS35NKo+vRTwYV0avPLm5L A==; X-CSE-ConnectionGUID: GG6AFbHhSaCwOBTwl8XX+A== X-CSE-MsgGUID: M+ux0yixQHqOT/RHb5n9QQ== X-IronPort-AV: E=McAfee;i="6800,10657,11647"; a="68174116" X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="68174116" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:43:54 -0800 X-CSE-ConnectionGUID: /bVBM2hHSBmND0G1aUHsIA== X-CSE-MsgGUID: kAgnohgiSxqmWcqyiqMduQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,161,1763452800"; d="scan'208";a="203072240" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.61]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2025 09:43:51 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Dominik Brodowski , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 23/23] PCI: Move scanbus bridge scanning to setup-cardbus.c Date: Fri, 19 Dec 2025 19:40:36 +0200 Message-Id: <20251219174036.16738-24-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> References: <20251219174036.16738-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable PCI core's pci_scan_bridge_extend() contains convoluted logic specific to setting up bus numbers for legacy CardBus bridges. Extract the CardBus specific part out into setup-cardbus.c to make the core code cleaner and allow leaving CardBus bridge support out from modern systems. Signed-off-by: Ilpo J=C3=A4rvinen --- I'm somewhat skeptical that EA capability is relevant for CardBus bridge but I've left it in place as I'm not 100% sure about it. ECN for EA Capability is from 2014 which is quite late considering CardBus timeline (PCMCIA ceased to exist in 2009). If it's not relevant, dropping its support from CardBus side would allow small simplifications to pci_cardbus_scan_bridge_extend(). --- drivers/pci/pci.h | 16 +++++ drivers/pci/probe.c | 73 +++++----------------- drivers/pci/setup-cardbus.c | 118 ++++++++++++++++++++++++++++++++++++ 3 files changed, 149 insertions(+), 58 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index b20ff7ef20ff..c586bf8a9da9 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -242,6 +242,7 @@ void pci_config_pm_runtime_put(struct pci_dev *dev); void pci_pm_power_up_and_verify_state(struct pci_dev *pci_dev); void pci_pm_init(struct pci_dev *dev); void pci_ea_init(struct pci_dev *dev); +bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub); void pci_msi_init(struct pci_dev *dev); void pci_msix_init(struct pci_dev *dev); bool pci_bridge_d3_possible(struct pci_dev *dev); @@ -377,10 +378,17 @@ extern unsigned long pci_hotplug_mmio_size; extern unsigned long pci_hotplug_mmio_pref_size; extern unsigned long pci_hotplug_bus_size; =20 +static inline bool pci_is_cardbus_bridge(struct pci_dev *dev) +{ + return dev->hdr_type =3D=3D PCI_HEADER_TYPE_CARDBUS; +} #ifdef CONFIG_CARDBUS unsigned long pci_cardbus_resource_alignment(struct resource *res); int pci_bus_size_cardbus_bridge(struct pci_bus *bus, struct list_head *realloc_head); +int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *de= v, + u32 buses, int max, + unsigned int available_buses, int pass); int pci_setup_cardbus(char *str); =20 #else @@ -393,6 +401,14 @@ static inline int pci_bus_size_cardbus_bridge(struct p= ci_bus *bus, { return -EOPNOTSUPP; } +static inline int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, + struct pci_dev *dev, + u32 buses, int max, + unsigned int available_buses, + int pass) +{ + return max; +} static inline int pci_setup_cardbus(char *str) { return -ENOENT; } #endif /* CONFIG_CARDBUS */ =20 diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 49468644e730..89f0717efd48 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -25,9 +25,6 @@ #include #include "pci.h" =20 -#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ -#define CARDBUS_RESERVE_BUSNR 3 - static struct resource busn_resource =3D { .name =3D "PCI busn", .start =3D 0, @@ -1345,7 +1342,7 @@ void pbus_validate_busn(struct pci_bus *bus) * and subordinate bus numbers, return true with the bus numbers in @sec * and @sub. Otherwise return false. */ -static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) +bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) { int ea, offset; u32 dw; @@ -1399,8 +1396,7 @@ static int pci_scan_bridge_extend(struct pci_bus *bus= , struct pci_dev *dev, int pass) { struct pci_bus *child; - int is_cardbus =3D (dev->hdr_type =3D=3D PCI_HEADER_TYPE_CARDBUS); - u32 buses, i, j =3D 0; + u32 buses; u16 bctl; u8 primary, secondary, subordinate; int broken =3D 0; @@ -1444,8 +1440,15 @@ static int pci_scan_bridge_extend(struct pci_bus *bu= s, struct pci_dev *dev, pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); =20 - if ((secondary || subordinate) && !pcibios_assign_all_busses() && - !is_cardbus && !broken) { + if (pci_is_cardbus_bridge(dev)) { + max =3D pci_cardbus_scan_bridge_extend(bus, dev, buses, max, + available_buses, + pass); + goto out; + } + + if ((secondary || subordinate) && + !pcibios_assign_all_busses() && !broken) { unsigned int cmax, buses; =20 /* @@ -1487,7 +1490,7 @@ static int pci_scan_bridge_extend(struct pci_bus *bus= , struct pci_dev *dev, * do in the second pass. */ if (!pass) { - if (pcibios_assign_all_busses() || broken || is_cardbus) + if (pcibios_assign_all_busses() || broken) =20 /* * Temporarily disable forwarding of the @@ -1534,55 +1537,11 @@ static int pci_scan_bridge_extend(struct pci_bus *b= us, struct pci_dev *dev, FIELD_PREP(PCI_SECONDARY_BUS_MASK, child->busn_res.start) | FIELD_PREP(PCI_SUBORDINATE_BUS_MASK, child->busn_res.end); =20 - /* - * yenta.c forces a secondary latency timer of 176. - * Copy that behaviour here. - */ - if (is_cardbus) { - buses &=3D ~PCI_SEC_LATENCY_TIMER_MASK; - buses |=3D FIELD_PREP(PCI_SEC_LATENCY_TIMER_MASK, - CARDBUS_LATENCY_TIMER); - } - /* We need to blast all three values with a single write */ pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); =20 - if (!is_cardbus) { - child->bridge_ctl =3D bctl; - max =3D pci_scan_child_bus_extend(child, available_buses); - } else { - - /* - * For CardBus bridges, we leave 4 bus numbers as - * cards with a PCI-to-PCI bridge can be inserted - * later. - */ - for (i =3D 0; i < CARDBUS_RESERVE_BUSNR; i++) { - struct pci_bus *parent =3D bus; - if (pci_find_bus(pci_domain_nr(bus), - max+i+1)) - break; - while (parent->parent) { - if ((!pcibios_assign_all_busses()) && - (parent->busn_res.end > max) && - (parent->busn_res.end <=3D max+i)) { - j =3D 1; - } - parent =3D parent->parent; - } - if (j) { - - /* - * Often, there are two CardBus - * bridges -- try to leave one - * valid bus number for each one. - */ - i /=3D 2; - break; - } - } - max +=3D i; - } + child->bridge_ctl =3D bctl; + max =3D pci_scan_child_bus_extend(child, available_buses); =20 /* * Set subordinate bus number to its real value. @@ -1594,9 +1553,7 @@ static int pci_scan_bridge_extend(struct pci_bus *bus= , struct pci_dev *dev, pci_bus_update_busn_res_end(child, max); pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); } - - scnprintf(child->name, sizeof(child->name), - (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), + scnprintf(child->name, sizeof(child->name), "PCI Bus %04x:%02x", pci_domain_nr(bus), child->number); =20 pbus_validate_busn(child); diff --git a/drivers/pci/setup-cardbus.c b/drivers/pci/setup-cardbus.c index 93a2b43c637b..1ebd13a1f730 100644 --- a/drivers/pci/setup-cardbus.c +++ b/drivers/pci/setup-cardbus.c @@ -3,14 +3,19 @@ * Cardbus bridge setup routines. */ =20 +#include #include #include #include #include +#include #include =20 #include "pci.h" =20 +#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ +#define CARDBUS_RESERVE_BUSNR 3 + #define DEFAULT_CARDBUS_IO_SIZE SZ_256 #define DEFAULT_CARDBUS_MEM_SIZE SZ_64M /* pci=3Dcbmemsize=3DnnM,cbiosize=3Dnn can override this */ @@ -186,3 +191,116 @@ int pci_setup_cardbus(char *str) =20 return -ENOENT; } + +int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *de= v, + u32 buses, int max, + unsigned int available_buses, int pass) +{ + struct pci_bus *child; + bool fixed_buses; + u8 fixed_sec, fixed_sub; + int next_busnr; + u32 i, j =3D 0; + + /* + * We need to assign a number to this bus which we always do in the + * second pass. + */ + if (!pass) { + /* + * Temporarily disable forwarding of the configuration + * cycles on all bridges in this bus segment to avoid + * possible conflicts in the second pass between two bridges + * programmed with overlapping bus ranges. + */ + pci_write_config_dword(dev, PCI_PRIMARY_BUS, + buses & PCI_SEC_LATENCY_TIMER_MASK); + return max; + } + + /* Clear errors */ + pci_write_config_word(dev, PCI_STATUS, 0xffff); + + /* Read bus numbers from EA Capability (if present) */ + fixed_buses =3D pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); + if (fixed_buses) + next_busnr =3D fixed_sec; + else + next_busnr =3D max + 1; + + /* + * Prevent assigning a bus number that already exists. This can + * happen when a bridge is hot-plugged, so in this case we only + * re-scan this bus. + */ + child =3D pci_find_bus(pci_domain_nr(bus), next_busnr); + if (!child) { + child =3D pci_add_new_bus(bus, dev, next_busnr); + if (!child) + return max; + pci_bus_insert_busn_res(child, next_busnr, bus->busn_res.end); + } + max++; + if (available_buses) + available_buses--; + + buses =3D (buses & PCI_SEC_LATENCY_TIMER_MASK) | + FIELD_PREP(PCI_PRIMARY_BUS_MASK, child->primary) | + FIELD_PREP(PCI_SECONDARY_BUS_MASK, child->busn_res.start) | + FIELD_PREP(PCI_SUBORDINATE_BUS_MASK, child->busn_res.end); + + /* + * yenta.c forces a secondary latency timer of 176. + * Copy that behaviour here. + */ + buses &=3D ~PCI_SEC_LATENCY_TIMER_MASK; + buses |=3D FIELD_PREP(PCI_SEC_LATENCY_TIMER_MASK, CARDBUS_LATENCY_TIMER); + + /* We need to blast all three values with a single write */ + pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); + + /* + * For CardBus bridges, we leave 4 bus numbers as cards with a + * PCI-to-PCI bridge can be inserted later. + */ + for (i =3D 0; i < CARDBUS_RESERVE_BUSNR; i++) { + struct pci_bus *parent =3D bus; + + if (pci_find_bus(pci_domain_nr(bus), max + i + 1)) + break; + + while (parent->parent) { + if (!pcibios_assign_all_busses() && + (parent->busn_res.end > max) && + (parent->busn_res.end <=3D max + i)) { + j =3D 1; + } + parent =3D parent->parent; + } + if (j) { + /* + * Often, there are two CardBus bridges -- try to + * leave one valid bus number for each one. + */ + i /=3D 2; + break; + } + } + max +=3D i; + + /* + * Set subordinate bus number to its real value. If fixed + * subordinate bus number exists from EA capability then use it. + */ + if (fixed_buses) + max =3D fixed_sub; + pci_bus_update_busn_res_end(child, max); + pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); + + scnprintf(child->name, sizeof(child->name), "PCI CardBus %04x:%02x", + pci_domain_nr(bus), child->number); + + pbus_validate_busn(child); + + return max; +} --=20 2.39.5