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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Subject: [PATCH net v2 3/3] octeon_ep_vf: ensure dbell BADDR updation Date: Fri, 19 Dec 2025 10:07:49 +0000 Message-ID: <20251219100751.3063135-4-vimleshk@marvell.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251219100751.3063135-1-vimleshk@marvell.com> References: <20251219100751.3063135-1-vimleshk@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=csSWUl4i c=1 sm=1 tr=0 ts=69452411 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=M5GUcnROAAAA:8 a=9s7rcsES4n5jIWhP9eIA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA4MyBTYWx0ZWRfX5dNWPQgI1KvM 5odDQj7o690Y4u282pbhwxsU3PMyiJAzg47oZTt5bggi6XuIdD9zk78kSfqfxymg1RsWELNZPFY chPlTBf3sZ+x96Iw2ivgDBbicyC0YU5uyI1K2ETQuACjBc4HhHirnusbPoNhOpHhJ+HxcUETxph vaZbUeuZe8iYxDQQrojS6MSWJRxxzS8NAEsg7Zlacg2rWlELq3G2m3ESVIeFeSvFcDrzNoPaQ8d xB7fWIamGNCt+qIfZwz9KvWcIk8FC2n/Z84iMmag18Fs67al5O/njJsJk+QJQoEe/bnx41xxkyQ VEaBghe1wGz3iFQFiT+Ay/KEhlER7ATNcXmMokBjb8FWADHLmhaWGcga7KgMRR20krPE0MVyr0C B9DQ3iTPtQ1T7mlCt5I1gGjg+9rwSGFpQrh3i1rBlZkAfBu5t1nqNfLA5KbidOoKcuSGXASmkr1 yBPLzj+MkIiu5tiOZaQ== X-Proofpoint-ORIG-GUID: NBSaBuKmIkB09m6-E7OVcMvljmKyoEON X-Proofpoint-GUID: NBSaBuKmIkB09m6-E7OVcMvljmKyoEON X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_03,2025-12-17_02,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Make sure the OUT DBELL base address reflects the latest values written to it. Fix: Add a wait until the OUT DBELL base address register is updated with the DMA ring descriptor address, and modify the setup_oq function to properly handle failures. Fixes: 2c0c32c72be29 ("octeon_ep_vf: add hardware configuration APIs") Signed-off-by: Sathesh Edara Signed-off-by: Shinas Rasheed Signed-off-by: Vimlesh Kumar --- V2: - Format code to avoid line exceeding 80 columns. - Use ULLONG_MAX and return standard err code. - Place limit to unbounded loop by adding timeout. V1: https://lore.kernel.org/all/20251212122304.2562229-4-vimleshk@marvell.c= om/ .../marvell/octeon_ep_vf/octep_vf_cn9k.c | 3 +- .../marvell/octeon_ep_vf/octep_vf_cnxk.c | 36 +++++++++++++++++-- .../marvell/octeon_ep_vf/octep_vf_main.h | 2 +- .../marvell/octeon_ep_vf/octep_vf_rx.c | 4 ++- 4 files changed, 39 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c b/dr= ivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c index 88937fce75f1..4c769b27c278 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c @@ -196,7 +196,7 @@ static void octep_vf_setup_iq_regs_cn93(struct octep_vf= _device *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_vf_setup_oq_regs_cn93(struct octep_vf_device *oct, int o= q_no) +static int octep_vf_setup_oq_regs_cn93(struct octep_vf_device *oct, int oq= _no) { struct octep_vf_oq *oq =3D oct->oq[oq_no]; u32 time_threshold =3D 0; @@ -239,6 +239,7 @@ static void octep_vf_setup_oq_regs_cn93(struct octep_vf= _device *oct, int oq_no) time_threshold =3D CFG_GET_OQ_INTR_TIME(oct->conf); reg_val =3D ((u64)time_threshold << 32) | CFG_GET_OQ_INTR_PKT(oct->conf); octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_INT_LEVELS(oq_no), reg_val); + return 0; } =20 /* Setup registers for a VF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c b/dr= ivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c index 1f79dfad42c6..3967d0e0de82 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c @@ -199,12 +199,14 @@ static void octep_vf_setup_iq_regs_cnxk(struct octep_= vf_device *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_vf_setup_oq_regs_cnxk(struct octep_vf_device *oct, int o= q_no) +static int octep_vf_setup_oq_regs_cnxk(struct octep_vf_device *oct, int oq= _no) { struct octep_vf_oq *oq =3D oct->oq[oq_no]; u32 time_threshold =3D 0; u64 oq_ctl =3D ULL(0); + u64 reg_ba_val; u64 reg_val; + unsigned long t_out_jiffies; =20 reg_val =3D octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no)); =20 @@ -214,6 +216,35 @@ static void octep_vf_setup_oq_regs_cnxk(struct octep_v= f_device *oct, int oq_no) reg_val =3D octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no)); } while (!(reg_val & CNXK_VF_R_OUT_CTL_IDLE)); } + octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_WMARK(oq_no), + oq->max_count); + /* Wait for WMARK to get applied */ + usleep_range(10, 15); + + octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_no), + oq->desc_ring_dma); + octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_RSIZE(oq_no), + oq->max_count); + reg_ba_val =3D octep_vf_read_csr64(oct, + CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_no)); + if (reg_ba_val !=3D oq->desc_ring_dma) { + t_out_jiffies =3D jiffies + 10 * HZ; + do { + if (reg_ba_val =3D=3D ULLONG_MAX) + return -EFAULT; + octep_vf_write_csr64(oct, + CNXK_VF_SDP_R_OUT_SLIST_BADDR + (oq_no), oq->desc_ring_dma); + octep_vf_write_csr64(oct, + CNXK_VF_SDP_R_OUT_SLIST_RSIZE + (oq_no), oq->max_count); + reg_ba_val =3D + octep_vf_read_csr64(oct, + CNXK_VF_SDP_R_OUT_SLIST_BADDR + (oq_no)); + } while ((reg_ba_val !=3D oq->desc_ring_dma) && + time_before(jiffies, t_out_jiffies)); + } =20 reg_val &=3D ~(CNXK_VF_R_OUT_CTL_IMODE); reg_val &=3D ~(CNXK_VF_R_OUT_CTL_ROR_P); @@ -227,8 +258,6 @@ static void octep_vf_setup_oq_regs_cnxk(struct octep_vf= _device *oct, int oq_no) reg_val |=3D (CNXK_VF_R_OUT_CTL_ES_P); =20 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no), reg_val); - octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_no), oq->desc_= ring_dma); - octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_RSIZE(oq_no), oq->max_c= ount); =20 oq_ctl =3D octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no)); /* Clear the ISIZE and BSIZE (22-0) */ @@ -250,6 +279,7 @@ static void octep_vf_setup_oq_regs_cnxk(struct octep_vf= _device *oct, int oq_no) reg_val &=3D ~GENMASK_ULL(31, 0); reg_val |=3D CFG_GET_OQ_WMARK(oct->conf); octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_WMARK(oq_no), reg_val); + return 0; } =20 /* Setup registers for a VF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h b/dr= ivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h index b9f13506f462..c74cd2369e90 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h @@ -55,7 +55,7 @@ struct octep_vf_mmio { =20 struct octep_vf_hw_ops { void (*setup_iq_regs)(struct octep_vf_device *oct, int q); - void (*setup_oq_regs)(struct octep_vf_device *oct, int q); + int (*setup_oq_regs)(struct octep_vf_device *oct, int q); void (*setup_mbox_regs)(struct octep_vf_device *oct, int mbox); =20 irqreturn_t (*non_ioq_intr_handler)(void *ioq_vector); diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c b/driv= ers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c index d70c8be3cfc4..6446f6bf0b90 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c @@ -171,7 +171,9 @@ static int octep_vf_setup_oq(struct octep_vf_device *oc= t, int q_no) goto oq_fill_buff_err; =20 octep_vf_oq_reset_indices(oq); - oct->hw_ops.setup_oq_regs(oct, q_no); + if (oct->hw_ops.setup_oq_regs(oct, q_no)) + goto oq_fill_buff_err; + oct->num_oqs++; =20 return 0; --=20 2.47.0