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Miller" , Eric Dumazet , Jakub Kicinski , "Paolo Abeni" Subject: [PATCH net v2 2/3] octeon_ep: ensure dbell BADDR updation Date: Fri, 19 Dec 2025 10:07:48 +0000 Message-ID: <20251219100751.3063135-3-vimleshk@marvell.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251219100751.3063135-1-vimleshk@marvell.com> References: <20251219100751.3063135-1-vimleshk@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=csSWUl4i c=1 sm=1 tr=0 ts=6945240d cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=M5GUcnROAAAA:8 a=HhD5TD71VMN5Ao0PvCkA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA4MyBTYWx0ZWRfX+6oSOrbSk8ol XfZkXHj2j9zoRsWUfXwjbDIZ4KhP6VNXGAMWQIES5OwyfkyVw6PsHw9v7bXBORIXD/E7e1klMFD K+05iGzbX2Ir1SoGpy7lP1ScdYuRWTRJt4YkZUJ3gyGhpS7ArTy3+ji4oBvTGvnMDxMotd5dhED SHupjlsRqAgVyIay1v3AaqbxbH8T84b1uFNE+XzP3A61/YnoLxzso9Skk6wAwrjnzw5kW8wiYR9 hQ1/AREC4qjTX3CCpYg1ifii8WBL3+5JtWdCt6+200x/Vo3iPQnTGdL1lVfDpxMz2zoQar1e4Ph a78nNLksooM4cL3kWgazIi9i8v0V8Yi+4ubdP5e0z1HbnE52LW9J+TRNyQfk2lTZWS7iOqFqwyp ZBrdh7bW9VmJk/TYGCk+IT9Bpg9AQwmX2zbzKa+eXvGBknISgOW04XEiWwxfs91KXrwjCnreH70 LQV+mSF7FZtxr+H01Fg== X-Proofpoint-ORIG-GUID: fGJzaPfb-agJfGcwel6bXHnxQ88xiN8c X-Proofpoint-GUID: fGJzaPfb-agJfGcwel6bXHnxQ88xiN8c X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_03,2025-12-17_02,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Make sure the OUT DBELL base address reflects the latest values written to it. Fix: Add a wait until the OUT DBELL base address register is updated with the DMA ring descriptor address, and modify the setup_oq function to properly handle failures. Fixes: 0807dc76f3bf5 ("octeon_ep: support Octeon CN10K devices") Signed-off-by: Sathesh Edara Signed-off-by: Shinas Rasheed Signed-off-by: Vimlesh Kumar --- V2: - Format code to avoid line exceeding 80 columns. - Use ULLONG_MAX and return standard err code. - Place limit to unbounded loop by adding timeout. V1: https://lore.kernel.org/all/20251212122304.2562229-3-vimleshk@marvell.c= om/ .../marvell/octeon_ep/octep_cn9k_pf.c | 3 +- .../marvell/octeon_ep/octep_cnxk_pf.c | 37 ++++++++++++++++--- .../ethernet/marvell/octeon_ep/octep_main.h | 2 +- .../net/ethernet/marvell/octeon_ep/octep_rx.c | 4 +- 4 files changed, 38 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c index 2574a6061e3d..2a5cebbf1ff8 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c @@ -307,7 +307,7 @@ static void octep_setup_iq_regs_cn93_pf(struct octep_de= vice *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_setup_oq_regs_cn93_pf(struct octep_device *oct, int oq_n= o) +static int octep_setup_oq_regs_cn93_pf(struct octep_device *oct, int oq_no) { u64 reg_val; u64 oq_ctl =3D 0ULL; @@ -355,6 +355,7 @@ static void octep_setup_oq_regs_cn93_pf(struct octep_de= vice *oct, int oq_no) reg_val =3D ((u64)time_threshold << 32) | CFG_GET_OQ_INTR_PKT(oct->conf); octep_write_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no), reg_val); + return 0; } =20 /* Setup registers for a PF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c index 73cd0ca758f0..1ca8da3f7dc7 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c @@ -8,6 +8,7 @@ #include #include #include +#include =20 #include "octep_config.h" #include "octep_main.h" @@ -327,11 +328,13 @@ static void octep_setup_iq_regs_cnxk_pf(struct octep_= device *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_setup_oq_regs_cnxk_pf(struct octep_device *oct, int oq_n= o) +static int octep_setup_oq_regs_cnxk_pf(struct octep_device *oct, int oq_no) { u64 reg_val; u64 oq_ctl =3D 0ULL; + u64 reg_ba_val; u32 time_threshold =3D 0; + unsigned long t_out_jiffies; struct octep_oq *oq =3D oct->oq[oq_no]; =20 oq_no +=3D CFG_GET_PORTS_PF_SRN(oct->conf); @@ -343,6 +346,33 @@ static void octep_setup_oq_regs_cnxk_pf(struct octep_d= evice *oct, int oq_no) reg_val =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no)); } while (!(reg_val & CNXK_R_OUT_CTL_IDLE)); } + octep_write_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no), oq->max_count); + /* Wait for WMARK to get applied */ + usleep_range(10, 15); + + octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), + oq->desc_ring_dma); + octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), + oq->max_count); + reg_ba_val =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no)); + + if (reg_ba_val !=3D oq->desc_ring_dma) { + t_out_jiffies =3D jiffies + 10 * HZ; + do { + if (reg_ba_val =3D=3D ULLONG_MAX) + return -EFAULT; + octep_write_csr64(oct, + CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), + oq->desc_ring_dma); + octep_write_csr64(oct, + CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), + oq->max_count); + reg_ba_val =3D + octep_read_csr64(oct, + CNXK_SDP_R_OUT_SLIST_BADDR(oq_no)); + } while ((reg_ba_val !=3D oq->desc_ring_dma) && + time_before(jiffies, t_out_jiffies)); + } =20 reg_val &=3D ~(CNXK_R_OUT_CTL_IMODE); reg_val &=3D ~(CNXK_R_OUT_CTL_ROR_P); @@ -356,10 +386,6 @@ static void octep_setup_oq_regs_cnxk_pf(struct octep_d= evice *oct, int oq_no) reg_val |=3D (CNXK_R_OUT_CTL_ES_P); =20 octep_write_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no), reg_val); - octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), - oq->desc_ring_dma); - octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), - oq->max_count); =20 oq_ctl =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no)); =20 @@ -385,6 +411,7 @@ static void octep_setup_oq_regs_cnxk_pf(struct octep_de= vice *oct, int oq_no) reg_val &=3D ~0xFFFFFFFFULL; reg_val |=3D CFG_GET_OQ_WMARK(oct->conf); octep_write_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no), reg_val); + return 0; } =20 /* Setup registers for a PF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_main.h b/drivers/= net/ethernet/marvell/octeon_ep/octep_main.h index 81ac4267811c..35d0ff289a70 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_main.h +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_main.h @@ -77,7 +77,7 @@ struct octep_pci_win_regs { =20 struct octep_hw_ops { void (*setup_iq_regs)(struct octep_device *oct, int q); - void (*setup_oq_regs)(struct octep_device *oct, int q); + int (*setup_oq_regs)(struct octep_device *oct, int q); void (*setup_mbox_regs)(struct octep_device *oct, int mbox); =20 irqreturn_t (*mbox_intr_handler)(void *ioq_vector); diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_rx.c b/drivers/ne= t/ethernet/marvell/octeon_ep/octep_rx.c index 82b6b19e76b4..1581cc468d74 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_rx.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_rx.c @@ -170,7 +170,9 @@ static int octep_setup_oq(struct octep_device *oct, int= q_no) goto oq_fill_buff_err; =20 octep_oq_reset_indices(oq); - oct->hw_ops.setup_oq_regs(oct, q_no); + if (oct->hw_ops.setup_oq_regs(oct, q_no)) + goto oq_fill_buff_err; + oct->num_oqs++; =20 return 0; --=20 2.47.0