From nobody Sun Feb 8 22:05:43 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67AB72EBB98; Fri, 19 Dec 2025 10:08:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766138901; cv=none; b=ORW8PbMmg+bqc/mjDa2wqYzJi1V+EowjbQ5c7uCHVKybozBoI66jHOnZPyOhXEr/H7uL76nKjyhX3hk6Loeyx1Qwu7p+MViB8iZLHX+1rMHh4Bw/rPqU7tI1GpvsMxkMOrnbWscZms25UfxVjfW/oewRY0S6KPwEQHo+Q6A4+l0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766138901; c=relaxed/simple; bh=3ek0r+aa4N27wO/oL9dlAc4TS8JLpWW8SraPtFy+OOs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=s4fHP1G3nP7+VMesvRvOlTcu8HeboDkmM372daqEtpkd+inkcw/qBE9pH8vgZJjKcJK5V/mjePC890HDqOryo/wqCMDRgYHxEj9w3FE4fMiKI7smFPhxW9zVusRJ9z2tTIL/M6XQ5Ax9sS4mytP/2kSAgIZxSqq6MiCUvJIQ4BM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=J1/dmuyc; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="J1/dmuyc" Received: from pps.filterd (m0431383.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BIJkNoq750231; Fri, 19 Dec 2025 02:08:10 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=X ItjOIlO0kG7ewyTA2KA7Fk1vCYAF8Rxhl8hUlLUcsY=; b=J1/dmuycMmFdfmyfl 9BRvglKhvnEPwk6sc+/q8HeLvdcFIQ0AzxF69uUEqBaZ3KYGHd3uVk5aJjY4p1pl HMNSyFOOC9aGkMabvVig0DugLE/Famrd9OxRSnmo00JTZQfdUEwOjklhF6LjG2A5 UrieprQbCYVowrOLAVjA6XAdJblDwvm6PIjZwIfG0nm4gIvJCOz2+7KssA7G0P7o pjja/fc/528RMCDmGKjLX+4K1HmTF2GfamM8b4JYIVYbA37TlcpJ7D6/zWcFahc4 UrP21cALTwu5lUVCMlfvRPS+Ilo3KfJ9h5S2wZMDSAseMiWq6xkUqiF34imadHDK 321XQ== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 4b4r249gem-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 19 Dec 2025 02:08:10 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Fri, 19 Dec 2025 02:08:22 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Fri, 19 Dec 2025 02:08:22 -0800 Received: from sapphire1.sclab.marvell.com (unknown [10.111.132.245]) by maili.marvell.com (Postfix) with ESMTP id BA95E5B695F; Fri, 19 Dec 2025 02:08:08 -0800 (PST) From: Vimlesh Kumar To: , CC: , , , "Vimlesh Kumar" , Veerasenareddy Burru , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , "Paolo Abeni" , Satananda Burla , "Abhijit Ayarekar" Subject: [PATCH net v2 1/3] octeon_ep: disable per ring interrupts Date: Fri, 19 Dec 2025 10:07:47 +0000 Message-ID: <20251219100751.3063135-2-vimleshk@marvell.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251219100751.3063135-1-vimleshk@marvell.com> References: <20251219100751.3063135-1-vimleshk@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=csSWUl4i c=1 sm=1 tr=0 ts=6945240a cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=M5GUcnROAAAA:8 a=BjJIY8cOur314jIlsncA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA4MyBTYWx0ZWRfX79LZm2mzvRlH Bsp0i6jjsLCp2fGgrCcRRa1692am5+g4OVHFdy27GJ+U41b7iMytgC9vKvb8zaf22uaoRL3C7VJ 9ou4xlOrrXRSY84sIsniXrLRuNaaurG0kmEkDP0JLjgNX+53bUqro6EbTxPYgbP+fajxDIE6vru EqxIeC2hTz66tIVS14ZVDEKwn7Tf2NZq9dnvsl0DseieDxb2ZlOKo9NUwH1LlNnjVGHwuaNjSF5 qwhhUlsJe5QtS9U9cIcCN7xWDeBnA+Vzcy82GwK6QvJ0OhIUhb+/l28m2bONRygDZnkAydM8lIG SqQhNw1XFrfGleRxRYaQ3vOqKb+ysPKyYf/74WkWcnABanqhOcta4+Q8bZEXye7554XqTVCuyjb 9HnW6CYNgrhAnPvuX/Wj9QlTFG0VcQjrPJlU44HfJI/FTelok73L0FlEFZPKTzqYSjuF9c6KM+x sSU5D0a+lt3rsMurs2w== X-Proofpoint-ORIG-GUID: gwMHoHds1h0IZzzETtP7zypfVjinQDDB X-Proofpoint-GUID: gwMHoHds1h0IZzzETtP7zypfVjinQDDB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_03,2025-12-17_02,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Disable the MSI-X per ring interrupt for every PF ring when PF netdev goes down. Fixes: 1f2c2d0cee023 ("octeon_ep: add hardware configuration APIs") Signed-off-by: Sathesh Edara Signed-off-by: Shinas Rasheed Signed-off-by: Vimlesh Kumar --- V2: Use BIT_ULL macro wherever applicable.=20 V1: https://lore.kernel.org/all/20251212122304.2562229-2-vimleshk@marvell.c= om/ .../ethernet/marvell/octeon_ep/octep_cn9k_pf.c | 18 +++++++++++++++--- .../ethernet/marvell/octeon_ep/octep_cnxk_pf.c | 18 +++++++++++++++--- .../marvell/octeon_ep/octep_regs_cn9k_pf.h | 1 + .../marvell/octeon_ep/octep_regs_cnxk_pf.h | 1 + 4 files changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c index b5805969404f..2574a6061e3d 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c @@ -696,14 +696,26 @@ static void octep_enable_interrupts_cn93_pf(struct oc= tep_device *oct) /* Disable all interrupts */ static void octep_disable_interrupts_cn93_pf(struct octep_device *oct) { - u64 intr_mask =3D 0ULL; + u64 reg_val, intr_mask =3D 0ULL; int srn, num_rings, i; =20 srn =3D CFG_GET_PORTS_PF_SRN(oct->conf); num_rings =3D CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); =20 - for (i =3D 0; i < num_rings; i++) - intr_mask |=3D (0x1ULL << (srn + i)); + for (i =3D 0; i < num_rings; i++) { + intr_mask |=3D (BIT_ULL(srn + i)); + reg_val =3D octep_read_csr64(oct, + CN93_SDP_R_IN_INT_LEVELS(srn + i)); + reg_val &=3D (~CN93_INT_ENA_BIT); + octep_write_csr64(oct, + CN93_SDP_R_IN_INT_LEVELS(srn + i), reg_val); + + reg_val =3D octep_read_csr64(oct, + CN93_SDP_R_OUT_INT_LEVELS(srn + i)); + reg_val &=3D (~CN93_INT_ENA_BIT); + octep_write_csr64(oct, + CN93_SDP_R_OUT_INT_LEVELS(srn + i), reg_val); + } =20 octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask); octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask); diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c index 5de0b5ecbc5f..73cd0ca758f0 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c @@ -720,14 +720,26 @@ static void octep_enable_interrupts_cnxk_pf(struct oc= tep_device *oct) /* Disable all interrupts */ static void octep_disable_interrupts_cnxk_pf(struct octep_device *oct) { - u64 intr_mask =3D 0ULL; + u64 reg_val, intr_mask =3D 0ULL; int srn, num_rings, i; =20 srn =3D CFG_GET_PORTS_PF_SRN(oct->conf); num_rings =3D CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); =20 - for (i =3D 0; i < num_rings; i++) - intr_mask |=3D (0x1ULL << (srn + i)); + for (i =3D 0; i < num_rings; i++) { + intr_mask |=3D BIT_ULL(srn + i); + reg_val =3D octep_read_csr64(oct, + CNXK_SDP_R_IN_INT_LEVELS(srn + i)); + reg_val &=3D (~CNXK_INT_ENA_BIT); + octep_write_csr64(oct, + CNXK_SDP_R_IN_INT_LEVELS(srn + i), reg_val); + + reg_val =3D octep_read_csr64(oct, + CNXK_SDP_R_OUT_INT_LEVELS(srn + i)); + reg_val &=3D (~CNXK_INT_ENA_BIT); + octep_write_csr64(oct, + CNXK_SDP_R_OUT_INT_LEVELS(srn + i), reg_val); + } =20 octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask); octep_write_csr64(oct, CNXK_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask); diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h b/= drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h index ca473502d7a0..42cb199bd085 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h @@ -386,5 +386,6 @@ #define CN93_PEM_BAR4_INDEX 7 #define CN93_PEM_BAR4_INDEX_SIZE 0x400000ULL #define CN93_PEM_BAR4_INDEX_OFFSET (CN93_PEM_BAR4_INDEX * CN93_PEM_BAR= 4_INDEX_SIZE) +#define CN93_INT_ENA_BIT (BIT_ULL(62)) =20 #endif /* _OCTEP_REGS_CN9K_PF_H_ */ diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h b/= drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h index e637d7c8224d..9eaadded9c50 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h @@ -412,5 +412,6 @@ #define CNXK_PEM_BAR4_INDEX 7 #define CNXK_PEM_BAR4_INDEX_SIZE 0x400000ULL #define CNXK_PEM_BAR4_INDEX_OFFSET (CNXK_PEM_BAR4_INDEX * CNXK_PEM_BAR4_IN= DEX_SIZE) +#define CNXK_INT_ENA_BIT (BIT_ULL(62)) =20 #endif /* _OCTEP_REGS_CNXK_PF_H_ */ --=20 2.47.0 From nobody Sun Feb 8 22:05:43 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 332092C21F9; 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Miller" , Eric Dumazet , Jakub Kicinski , "Paolo Abeni" Subject: [PATCH net v2 2/3] octeon_ep: ensure dbell BADDR updation Date: Fri, 19 Dec 2025 10:07:48 +0000 Message-ID: <20251219100751.3063135-3-vimleshk@marvell.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251219100751.3063135-1-vimleshk@marvell.com> References: <20251219100751.3063135-1-vimleshk@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=csSWUl4i c=1 sm=1 tr=0 ts=6945240d cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=M5GUcnROAAAA:8 a=HhD5TD71VMN5Ao0PvCkA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA4MyBTYWx0ZWRfX+6oSOrbSk8ol XfZkXHj2j9zoRsWUfXwjbDIZ4KhP6VNXGAMWQIES5OwyfkyVw6PsHw9v7bXBORIXD/E7e1klMFD K+05iGzbX2Ir1SoGpy7lP1ScdYuRWTRJt4YkZUJ3gyGhpS7ArTy3+ji4oBvTGvnMDxMotd5dhED SHupjlsRqAgVyIay1v3AaqbxbH8T84b1uFNE+XzP3A61/YnoLxzso9Skk6wAwrjnzw5kW8wiYR9 hQ1/AREC4qjTX3CCpYg1ifii8WBL3+5JtWdCt6+200x/Vo3iPQnTGdL1lVfDpxMz2zoQar1e4Ph a78nNLksooM4cL3kWgazIi9i8v0V8Yi+4ubdP5e0z1HbnE52LW9J+TRNyQfk2lTZWS7iOqFqwyp ZBrdh7bW9VmJk/TYGCk+IT9Bpg9AQwmX2zbzKa+eXvGBknISgOW04XEiWwxfs91KXrwjCnreH70 LQV+mSF7FZtxr+H01Fg== X-Proofpoint-ORIG-GUID: fGJzaPfb-agJfGcwel6bXHnxQ88xiN8c X-Proofpoint-GUID: fGJzaPfb-agJfGcwel6bXHnxQ88xiN8c X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_03,2025-12-17_02,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Make sure the OUT DBELL base address reflects the latest values written to it. Fix: Add a wait until the OUT DBELL base address register is updated with the DMA ring descriptor address, and modify the setup_oq function to properly handle failures. Fixes: 0807dc76f3bf5 ("octeon_ep: support Octeon CN10K devices") Signed-off-by: Sathesh Edara Signed-off-by: Shinas Rasheed Signed-off-by: Vimlesh Kumar --- V2: - Format code to avoid line exceeding 80 columns. - Use ULLONG_MAX and return standard err code. - Place limit to unbounded loop by adding timeout. V1: https://lore.kernel.org/all/20251212122304.2562229-3-vimleshk@marvell.c= om/ .../marvell/octeon_ep/octep_cn9k_pf.c | 3 +- .../marvell/octeon_ep/octep_cnxk_pf.c | 37 ++++++++++++++++--- .../ethernet/marvell/octeon_ep/octep_main.h | 2 +- .../net/ethernet/marvell/octeon_ep/octep_rx.c | 4 +- 4 files changed, 38 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c index 2574a6061e3d..2a5cebbf1ff8 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c @@ -307,7 +307,7 @@ static void octep_setup_iq_regs_cn93_pf(struct octep_de= vice *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_setup_oq_regs_cn93_pf(struct octep_device *oct, int oq_n= o) +static int octep_setup_oq_regs_cn93_pf(struct octep_device *oct, int oq_no) { u64 reg_val; u64 oq_ctl =3D 0ULL; @@ -355,6 +355,7 @@ static void octep_setup_oq_regs_cn93_pf(struct octep_de= vice *oct, int oq_no) reg_val =3D ((u64)time_threshold << 32) | CFG_GET_OQ_INTR_PKT(oct->conf); octep_write_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no), reg_val); + return 0; } =20 /* Setup registers for a PF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c index 73cd0ca758f0..1ca8da3f7dc7 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c @@ -8,6 +8,7 @@ #include #include #include +#include =20 #include "octep_config.h" #include "octep_main.h" @@ -327,11 +328,13 @@ static void octep_setup_iq_regs_cnxk_pf(struct octep_= device *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_setup_oq_regs_cnxk_pf(struct octep_device *oct, int oq_n= o) +static int octep_setup_oq_regs_cnxk_pf(struct octep_device *oct, int oq_no) { u64 reg_val; u64 oq_ctl =3D 0ULL; + u64 reg_ba_val; u32 time_threshold =3D 0; + unsigned long t_out_jiffies; struct octep_oq *oq =3D oct->oq[oq_no]; =20 oq_no +=3D CFG_GET_PORTS_PF_SRN(oct->conf); @@ -343,6 +346,33 @@ static void octep_setup_oq_regs_cnxk_pf(struct octep_d= evice *oct, int oq_no) reg_val =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no)); } while (!(reg_val & CNXK_R_OUT_CTL_IDLE)); } + octep_write_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no), oq->max_count); + /* Wait for WMARK to get applied */ + usleep_range(10, 15); + + octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), + oq->desc_ring_dma); + octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), + oq->max_count); + reg_ba_val =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no)); + + if (reg_ba_val !=3D oq->desc_ring_dma) { + t_out_jiffies =3D jiffies + 10 * HZ; + do { + if (reg_ba_val =3D=3D ULLONG_MAX) + return -EFAULT; + octep_write_csr64(oct, + CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), + oq->desc_ring_dma); + octep_write_csr64(oct, + CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), + oq->max_count); + reg_ba_val =3D + octep_read_csr64(oct, + CNXK_SDP_R_OUT_SLIST_BADDR(oq_no)); + } while ((reg_ba_val !=3D oq->desc_ring_dma) && + time_before(jiffies, t_out_jiffies)); + } =20 reg_val &=3D ~(CNXK_R_OUT_CTL_IMODE); reg_val &=3D ~(CNXK_R_OUT_CTL_ROR_P); @@ -356,10 +386,6 @@ static void octep_setup_oq_regs_cnxk_pf(struct octep_d= evice *oct, int oq_no) reg_val |=3D (CNXK_R_OUT_CTL_ES_P); =20 octep_write_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no), reg_val); - octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), - oq->desc_ring_dma); - octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), - oq->max_count); =20 oq_ctl =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no)); =20 @@ -385,6 +411,7 @@ static void octep_setup_oq_regs_cnxk_pf(struct octep_de= vice *oct, int oq_no) reg_val &=3D ~0xFFFFFFFFULL; reg_val |=3D CFG_GET_OQ_WMARK(oct->conf); octep_write_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no), reg_val); + return 0; } =20 /* Setup registers for a PF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_main.h b/drivers/= net/ethernet/marvell/octeon_ep/octep_main.h index 81ac4267811c..35d0ff289a70 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_main.h +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_main.h @@ -77,7 +77,7 @@ struct octep_pci_win_regs { =20 struct octep_hw_ops { void (*setup_iq_regs)(struct octep_device *oct, int q); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Subject: [PATCH net v2 3/3] octeon_ep_vf: ensure dbell BADDR updation Date: Fri, 19 Dec 2025 10:07:49 +0000 Message-ID: <20251219100751.3063135-4-vimleshk@marvell.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251219100751.3063135-1-vimleshk@marvell.com> References: <20251219100751.3063135-1-vimleshk@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=csSWUl4i c=1 sm=1 tr=0 ts=69452411 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=M5GUcnROAAAA:8 a=9s7rcsES4n5jIWhP9eIA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA4MyBTYWx0ZWRfX5dNWPQgI1KvM 5odDQj7o690Y4u282pbhwxsU3PMyiJAzg47oZTt5bggi6XuIdD9zk78kSfqfxymg1RsWELNZPFY chPlTBf3sZ+x96Iw2ivgDBbicyC0YU5uyI1K2ETQuACjBc4HhHirnusbPoNhOpHhJ+HxcUETxph vaZbUeuZe8iYxDQQrojS6MSWJRxxzS8NAEsg7Zlacg2rWlELq3G2m3ESVIeFeSvFcDrzNoPaQ8d xB7fWIamGNCt+qIfZwz9KvWcIk8FC2n/Z84iMmag18Fs67al5O/njJsJk+QJQoEe/bnx41xxkyQ VEaBghe1wGz3iFQFiT+Ay/KEhlER7ATNcXmMokBjb8FWADHLmhaWGcga7KgMRR20krPE0MVyr0C B9DQ3iTPtQ1T7mlCt5I1gGjg+9rwSGFpQrh3i1rBlZkAfBu5t1nqNfLA5KbidOoKcuSGXASmkr1 yBPLzj+MkIiu5tiOZaQ== X-Proofpoint-ORIG-GUID: NBSaBuKmIkB09m6-E7OVcMvljmKyoEON X-Proofpoint-GUID: NBSaBuKmIkB09m6-E7OVcMvljmKyoEON X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_03,2025-12-17_02,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Make sure the OUT DBELL base address reflects the latest values written to it. Fix: Add a wait until the OUT DBELL base address register is updated with the DMA ring descriptor address, and modify the setup_oq function to properly handle failures. Fixes: 2c0c32c72be29 ("octeon_ep_vf: add hardware configuration APIs") Signed-off-by: Sathesh Edara Signed-off-by: Shinas Rasheed Signed-off-by: Vimlesh Kumar --- V2: - Format code to avoid line exceeding 80 columns. - Use ULLONG_MAX and return standard err code. - Place limit to unbounded loop by adding timeout. V1: https://lore.kernel.org/all/20251212122304.2562229-4-vimleshk@marvell.c= om/ .../marvell/octeon_ep_vf/octep_vf_cn9k.c | 3 +- .../marvell/octeon_ep_vf/octep_vf_cnxk.c | 36 +++++++++++++++++-- .../marvell/octeon_ep_vf/octep_vf_main.h | 2 +- .../marvell/octeon_ep_vf/octep_vf_rx.c | 4 ++- 4 files changed, 39 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c b/dr= ivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c index 88937fce75f1..4c769b27c278 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c @@ -196,7 +196,7 @@ static void octep_vf_setup_iq_regs_cn93(struct octep_vf= _device *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_vf_setup_oq_regs_cn93(struct octep_vf_device *oct, int o= q_no) +static int octep_vf_setup_oq_regs_cn93(struct octep_vf_device *oct, int oq= _no) { struct octep_vf_oq *oq =3D oct->oq[oq_no]; u32 time_threshold =3D 0; @@ -239,6 +239,7 @@ static void octep_vf_setup_oq_regs_cn93(struct octep_vf= _device *oct, int oq_no) time_threshold =3D CFG_GET_OQ_INTR_TIME(oct->conf); reg_val =3D ((u64)time_threshold << 32) | CFG_GET_OQ_INTR_PKT(oct->conf); octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_INT_LEVELS(oq_no), reg_val); + return 0; } =20 /* Setup registers for a VF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c b/dr= ivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c index 1f79dfad42c6..3967d0e0de82 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c @@ -199,12 +199,14 @@ static void octep_vf_setup_iq_regs_cnxk(struct octep_= vf_device *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_vf_setup_oq_regs_cnxk(struct octep_vf_device *oct, int o= q_no) +static int octep_vf_setup_oq_regs_cnxk(struct octep_vf_device *oct, int oq= _no) { struct octep_vf_oq *oq =3D oct->oq[oq_no]; u32 time_threshold =3D 0; u64 oq_ctl =3D ULL(0); + u64 reg_ba_val; u64 reg_val; + unsigned long t_out_jiffies; =20 reg_val =3D octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no)); =20 @@ -214,6 +216,35 @@ static void octep_vf_setup_oq_regs_cnxk(struct octep_v= f_device *oct, int oq_no) reg_val =3D octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no)); } while (!(reg_val & CNXK_VF_R_OUT_CTL_IDLE)); } + octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_WMARK(oq_no), + oq->max_count); + /* Wait for WMARK to get applied */ + usleep_range(10, 15); + + octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_no), + oq->desc_ring_dma); + octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_RSIZE(oq_no), + oq->max_count); + reg_ba_val =3D octep_vf_read_csr64(oct, + CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_no)); + if (reg_ba_val !=3D oq->desc_ring_dma) { + t_out_jiffies =3D jiffies + 10 * HZ; + do { + if (reg_ba_val =3D=3D ULLONG_MAX) + return -EFAULT; + octep_vf_write_csr64(oct, + CNXK_VF_SDP_R_OUT_SLIST_BADDR + (oq_no), oq->desc_ring_dma); + octep_vf_write_csr64(oct, + CNXK_VF_SDP_R_OUT_SLIST_RSIZE + (oq_no), oq->max_count); + reg_ba_val =3D + octep_vf_read_csr64(oct, + CNXK_VF_SDP_R_OUT_SLIST_BADDR + (oq_no)); + } while ((reg_ba_val !=3D oq->desc_ring_dma) && + time_before(jiffies, t_out_jiffies)); + } =20 reg_val &=3D ~(CNXK_VF_R_OUT_CTL_IMODE); reg_val &=3D ~(CNXK_VF_R_OUT_CTL_ROR_P); @@ -227,8 +258,6 @@ static void octep_vf_setup_oq_regs_cnxk(struct octep_vf= _device *oct, int oq_no) reg_val |=3D (CNXK_VF_R_OUT_CTL_ES_P); =20 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no), reg_val); - octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_no), oq->desc_= ring_dma); - octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_RSIZE(oq_no), oq->max_c= ount); =20 oq_ctl =3D octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no)); /* Clear the ISIZE and BSIZE (22-0) */ @@ -250,6 +279,7 @@ static void octep_vf_setup_oq_regs_cnxk(struct octep_vf= _device *oct, int oq_no) reg_val &=3D ~GENMASK_ULL(31, 0); reg_val |=3D CFG_GET_OQ_WMARK(oct->conf); octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_WMARK(oq_no), reg_val); + return 0; } =20 /* Setup registers for a VF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h b/dr= ivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h index b9f13506f462..c74cd2369e90 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h @@ -55,7 +55,7 @@ struct octep_vf_mmio { =20 struct octep_vf_hw_ops { void (*setup_iq_regs)(struct octep_vf_device *oct, int q); - void (*setup_oq_regs)(struct octep_vf_device *oct, int q); + int (*setup_oq_regs)(struct octep_vf_device *oct, int q); void (*setup_mbox_regs)(struct octep_vf_device *oct, int mbox); =20 irqreturn_t (*non_ioq_intr_handler)(void *ioq_vector); diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c b/driv= ers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c index d70c8be3cfc4..6446f6bf0b90 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c @@ -171,7 +171,9 @@ static int octep_vf_setup_oq(struct octep_vf_device *oc= t, int q_no) goto oq_fill_buff_err; =20 octep_vf_oq_reset_indices(oq); - oct->hw_ops.setup_oq_regs(oct, q_no); + if (oct->hw_ops.setup_oq_regs(oct, q_no)) + goto oq_fill_buff_err; + oct->num_oqs++; =20 return 0; --=20 2.47.0