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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b05fcfc1b7sm3614954eec.0.2025.12.18.22.59.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 22:59:32 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v9 6/7] qcom-tgu: Add timer/counter functionality for TGU Date: Thu, 18 Dec 2025 22:59:01 -0800 Message-Id: <20251219065902.2296896-7-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> References: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: Uzj7iLaZhSG6xkzQfM98UttXQ_Vk8Ff8 X-Authority-Analysis: v=2.4 cv=A7ph/qWG c=1 sm=1 tr=0 ts=6944f7d6 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=eGDQztGCVwpQsGOtWZEA:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: Uzj7iLaZhSG6xkzQfM98UttXQ_Vk8Ff8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA1NiBTYWx0ZWRfX20kbaAnYESsu q+YxuFGL21kzJ3AF63h+r5FpDTuuvD8+akb3/PG1VzrC/dLmHT5ETQBNxCbY/CoWxxUEEVM0PRJ nP9Ow1DrnEkSM116hqfK15RNINrQNolh0xLO+1jqomzecpgbYpzuXXcDQIP7uHBrAD1udiEayyj zRDe0V5ooDdPFVarmPXz+aYz9Ukd9tyKYqLMPPsGLFVj+JOfJpK48OuP1vw3idxxzWoz11tqn4s HSjPi5zEMEjmwB0HaD0/8Scsq9VZbrnccu87dGIOHLhz5o8/rMcsgvb28eSX7VFDj/Zoi/X6jLJ qWVNog7m7mK0VhOdBdf6gOqvpxzU0GpoNMBeNuyuy9FvQKhvAPgvbvZV5IVXR/x8LQMvIRhfqeO VbwXoGhH023owQkReAWtcpMbM+z2xg+DB+CHJpoHcj4TV6pfp9v2oGo7JyLEjfOlJdkjiWklDpl 31erzVif2gExk9J/pkQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_02,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 malwarescore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190056 Content-Type: text/plain; charset="utf-8" Add counter and timer node for each step which could be programed if they are to be utilized in trigger event/sequence. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 14 ++ drivers/hwtracing/qcom/tgu.c | 120 ++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 54 ++++++++ 3 files changed, 188 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu index 6fbd86592681..010eade0a1c5 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -28,3 +28,17 @@ KernelVersion 6.19 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the next action with specific step for TGU. + +What: /sys/bus/amba/devices//step[0:7]_timer/reg[0:1] +Date: December 2025 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the timer value with specific step for TGU. + +What: /sys/bus/amba/devices//step[0:7]_counter/reg[0:1] +Date: December 2025 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the counter value with specific step for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index 98648ee61a10..d4210869556e 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -37,6 +37,12 @@ static int calculate_array_location(struct tgu_drvdata *= drvdata, ret =3D step_index * (drvdata->max_condition_select) + reg_index; break; + case TGU_COUNTER: + ret =3D step_index * (drvdata->max_counter) + reg_index; + break; + case TGU_TIMER: + ret =3D step_index * (drvdata->max_timer) + reg_index; + break; default: break; } @@ -81,6 +87,12 @@ static ssize_t tgu_dataset_show(struct device *dev, case TGU_CONDITION_SELECT: return sysfs_emit(buf, "0x%x\n", drvdata->value_table->condition_select[index]); + case TGU_TIMER: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->timer[index]); + case TGU_COUNTER: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->counter[index]); default: break; } @@ -126,6 +138,14 @@ static ssize_t tgu_dataset_store(struct device *dev, tgu_drvdata->value_table->condition_select[index] =3D val; ret =3D size; break; + case TGU_TIMER: + tgu_drvdata->value_table->timer[index] =3D val; + ret =3D size; + break; + case TGU_COUNTER: + tgu_drvdata->value_table->counter[index] =3D val; + ret =3D size; + break; default: break; } @@ -168,6 +188,22 @@ static umode_t tgu_node_visible(struct kobject *kobjec= t, drvdata->max_condition_select) ? attr->mode : 0; break; + case TGU_COUNTER: + if (drvdata->max_counter =3D=3D 0) + ret =3D SYSFS_GROUP_INVISIBLE; + else + ret =3D (tgu_attr->reg_num < + drvdata->max_counter) ? + attr->mode : 0; + break; + case TGU_TIMER: + if (drvdata->max_timer =3D=3D 0) + ret =3D SYSFS_GROUP_INVISIBLE; + else + ret =3D (tgu_attr->reg_num < + drvdata->max_timer) ? + attr->mode : 0; + break; default: break; } @@ -219,6 +255,30 @@ static ssize_t tgu_write_all_hw_regs(struct tgu_drvdat= a *drvdata) drvdata->base + CONDITION_SELECT_STEP(i, j)); } } + + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_timer; j++) { + index =3D check_array_location(drvdata, i, TGU_TIMER, j); + + if (index =3D=3D -EINVAL) + goto exit; + + writel(drvdata->value_table->timer[index], + drvdata->base + TIMER_COMPARE_STEP(i, j)); + } + } + + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_counter; j++) { + index =3D check_array_location(drvdata, i, TGU_COUNTER, j); + + if (index =3D=3D -EINVAL) + goto exit; + + writel(drvdata->value_table->counter[index], + drvdata->base + COUNTER_COMPARE_STEP(i, j)); + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); exit: @@ -262,6 +322,31 @@ static void tgu_set_conditions(struct tgu_drvdata *drv= data) drvdata->max_condition_select =3D TGU_DEVID_CONDITIONS(devid) + 1; } =20 +static void tgu_set_timer_counter(struct tgu_drvdata *drvdata) +{ + int num_timers, num_counters; + u32 devid2; + + devid2 =3D readl(drvdata->base + CORESIGHT_DEVID2); + + if (TGU_DEVID2_TIMER0(devid2) && TGU_DEVID2_TIMER1(devid2)) + num_timers =3D 2; + else if (TGU_DEVID2_TIMER0(devid2) || TGU_DEVID2_TIMER1(devid2)) + num_timers =3D 1; + else + num_timers =3D 0; + + if (TGU_DEVID2_COUNTER0(devid2) && TGU_DEVID2_COUNTER1(devid2)) + num_counters =3D 2; + else if (TGU_DEVID2_COUNTER0(devid2) || TGU_DEVID2_COUNTER1(devid2)) + num_counters =3D 1; + else + num_counters =3D 0; + + drvdata->max_timer =3D num_timers; + drvdata->max_counter =3D num_counters; +} + static int tgu_enable(struct device *dev) { int ret =3D 0; @@ -400,6 +485,22 @@ static const struct attribute_group *tgu_attr_groups[]= =3D { CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(5), CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(6), CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(7), + TIMER_ATTRIBUTE_GROUP_INIT(0), + TIMER_ATTRIBUTE_GROUP_INIT(1), + TIMER_ATTRIBUTE_GROUP_INIT(2), + TIMER_ATTRIBUTE_GROUP_INIT(3), + TIMER_ATTRIBUTE_GROUP_INIT(4), + TIMER_ATTRIBUTE_GROUP_INIT(5), + TIMER_ATTRIBUTE_GROUP_INIT(6), + TIMER_ATTRIBUTE_GROUP_INIT(7), + COUNTER_ATTRIBUTE_GROUP_INIT(0), + COUNTER_ATTRIBUTE_GROUP_INIT(1), + COUNTER_ATTRIBUTE_GROUP_INIT(2), + COUNTER_ATTRIBUTE_GROUP_INIT(3), + COUNTER_ATTRIBUTE_GROUP_INIT(4), + COUNTER_ATTRIBUTE_GROUP_INIT(5), + COUNTER_ATTRIBUTE_GROUP_INIT(6), + COUNTER_ATTRIBUTE_GROUP_INIT(7), NULL, }; =20 @@ -425,6 +526,7 @@ static int tgu_probe(struct amba_device *adev, const st= ruct amba_id *id) tgu_set_reg_number(drvdata); tgu_set_steps(drvdata); tgu_set_conditions(drvdata); + tgu_set_timer_counter(drvdata); =20 ret =3D sysfs_create_groups(&dev->kobj, tgu_attr_groups); if (ret) { @@ -464,6 +566,24 @@ static int tgu_probe(struct amba_device *adev, const s= truct amba_id *id) if (!drvdata->value_table->condition_select) return -ENOMEM; =20 + drvdata->value_table->timer =3D devm_kzalloc( + dev, + drvdata->max_step * drvdata->max_timer * + sizeof(*(drvdata->value_table->timer)), + GFP_KERNEL); + + if (!drvdata->value_table->timer) + return -ENOMEM; + + drvdata->value_table->counter =3D devm_kzalloc( + dev, + drvdata->max_step * drvdata->max_counter * + sizeof(*(drvdata->value_table->counter)), + GFP_KERNEL); + + if (!drvdata->value_table->counter) + return -ENOMEM; + drvdata->enable =3D false; =20 pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index 1f46da35b40a..46a4cffedd7b 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -11,11 +11,17 @@ #define TGU_LAR 0xfb0 #define TGU_UNLOCK_OFFSET 0xc5acce55 #define TGU_DEVID 0xfc8 +#define CORESIGHT_DEVID2 0xfc0 =20 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) #define TGU_DEVID_SENSE_INPUT(devid_val) ((int) BMVAL(devid_val, 10, 17)) #define TGU_DEVID_STEPS(devid_val) ((int)BMVAL(devid_val, 3, 6)) #define TGU_DEVID_CONDITIONS(devid_val) ((int)BMVAL(devid_val, 0, 2)) +#define TGU_DEVID2_TIMER0(devid_val) ((int)BMVAL(devid_val, 18, 23)) +#define TGU_DEVID2_TIMER1(devid_val) ((int)BMVAL(devid_val, 13, 17)) +#define TGU_DEVID2_COUNTER0(devid_val) ((int)BMVAL(devid_val, 6, 11)) +#define TGU_DEVID2_COUNTER1(devid_val) ((int)BMVAL(devid_val, 0, 5)) + #define NUMBER_BITS_EACH_SIGNAL 4 #define LENGTH_REGISTER 32 =20 @@ -51,6 +57,8 @@ #define PRIORITY_START_OFFSET 0x0074 #define CONDITION_DECODE_OFFSET 0x0050 #define CONDITION_SELECT_OFFSET 0x0060 +#define TIMER_START_OFFSET 0x0040 +#define COUNTER_START_OFFSET 0x0048 #define PRIORITY_OFFSET 0x60 #define REG_OFFSET 0x4 =20 @@ -62,6 +70,12 @@ #define CONDITION_DECODE_STEP(step, decode) \ (CONDITION_DECODE_OFFSET + REG_OFFSET * decode + STEP_OFFSET * step) =20 +#define TIMER_COMPARE_STEP(step, timer) \ + (TIMER_START_OFFSET + REG_OFFSET * timer + STEP_OFFSET * step) + +#define COUNTER_COMPARE_STEP(step, counter) \ + (COUNTER_START_OFFSET + REG_OFFSET * counter + STEP_OFFSET * step) + #define CONDITION_SELECT_STEP(step, select) \ (CONDITION_SELECT_OFFSET + REG_OFFSET * select + STEP_OFFSET * step) =20 @@ -83,6 +97,12 @@ #define STEP_SELECT(step_index, reg_num) \ tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_SELECT, reg_num) =20 +#define STEP_TIMER(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_TIMER, reg_num) + +#define STEP_COUNTER(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_COUNTER, reg_num) + #define STEP_PRIORITY_LIST(step_index, priority) \ {STEP_PRIORITY(step_index, 0, priority), \ STEP_PRIORITY(step_index, 1, priority), \ @@ -122,6 +142,18 @@ NULL \ } =20 +#define STEP_TIMER_LIST(n) \ + {STEP_TIMER(n, 0), \ + STEP_TIMER(n, 1), \ + NULL \ + } + +#define STEP_COUNTER_LIST(n) \ + {STEP_COUNTER(n, 0), \ + STEP_COUNTER(n, 1), \ + NULL \ + } + #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ (&(const struct attribute_group){\ .attrs =3D (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ @@ -143,6 +175,20 @@ .name =3D "step" #step "_condition_select" \ }) =20 +#define TIMER_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_TIMER_LIST(step),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_timer" \ + }) + +#define COUNTER_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_COUNTER_LIST(step),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_counter" \ + }) + enum operation_index { TGU_PRIORITY0, TGU_PRIORITY1, @@ -150,6 +196,8 @@ enum operation_index { TGU_PRIORITY3, TGU_CONDITION_DECODE, TGU_CONDITION_SELECT, + TGU_TIMER, + TGU_COUNTER }; =20 /* Maximum priority that TGU supports */ @@ -166,6 +214,8 @@ struct value_table { unsigned int *priority; unsigned int *condition_decode; unsigned int *condition_select; + unsigned int *timer; + unsigned int *counter; }; =20 static inline void TGU_LOCK(void __iomem *addr) @@ -197,6 +247,8 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @max_step: Maximum step size * @max_condition_decode: Maximum number of condition_decode * @max_condition_select: Maximum number of condition_select + * @max_timer: Maximum number of timers + * @max_counter: Maximum number of counters * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -213,6 +265,8 @@ struct tgu_drvdata { int max_step; int max_condition_decode; int max_condition_select; + int max_timer; + int max_counter; }; =20 #endif --=20 2.34.1