From nobody Tue Feb 10 00:57:50 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21A9D2DEA6B for ; Fri, 19 Dec 2025 06:59:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127567; cv=none; b=C6U2ZvBwECs4iMklVlgORl6qxx3PMw8UQliQxbFi3bBsZJmx/P4ak+003SmKDaMj+6yMYeHm2VrKAgXgIX2xmZ6Uz4MGLLBim1JZ75G7f1gGXuAeTglCI3rPa2aP//qiGsg4gZ+kJkMT5O58tcA9xrTsp6sJ77ddrtOVAM2411k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127567; c=relaxed/simple; bh=BKxmPAIfDQMipphXpdmD/EV9MfAn1lh12oL7+7IANCg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cfjJWr9cHRytxDeJ5kEroEHT7QOKUh06WKxURP0307WAcepbt33VJmb1m4hHrxQUzUzGNAbuADI+fbFSUD3mgdDoZ+rnEVB6vnv6sTCBy9BlzdH5GcOAIg3rVZau7d+EP+jSkKte9tu9oV8G+3aJpbEXfB8EQVPoidXzcUz+iDc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=i73Fm+4M; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=MQDlffK0; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="i73Fm+4M"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="MQDlffK0" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJ4cQXk1771762 for ; Fri, 19 Dec 2025 06:59:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=gg3gwEOyjqD Do8XAcNT9mbGI0dzn97wIDkd7TasSApU=; b=i73Fm+4MlspXLrUZRqd2ihCFV6j OrRdU+eetmwJo4ZO3fHeplG9u/N9HcETn0nB++YgWTE1yw1kf+6sG3vTKB8xSeoU HLBGHshk0xVBV77LluHUKARPxQt0uxwFo4q1Ig7NODhdmMEfdUG30ESBcwImLjq2 SX9ZuNIj+Dru3dvZ6UaYmwahICGRVCeFbQM3ezdElcsQusoPWqOmOcrfgAUnd4mI 43LYdogKprndNnNPWs4KVa8KuWms4cOHQWJvgFg7voHemjpsRuvRdHrIuuxa8u5A SeVqCFYzK0Iy+WRpaL9IQF+U6aILNxZTEnxhUAkKUZFw0n/f4Dg23QkzEFw== Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r2bhmbn-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 06:59:24 +0000 (GMT) Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-ba4c6ac8406so1256869a12.0 for ; Thu, 18 Dec 2025 22:59:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766127563; x=1766732363; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gg3gwEOyjqDDo8XAcNT9mbGI0dzn97wIDkd7TasSApU=; b=MQDlffK0j3qwdAscJdscsyR7slrhEzueh2lbR9Y57BinAR91moC3P9OPcG8EFK4Prn WfFXQ1mWDg5QRsDtQ9Bm4RLopvBe7sSAyrpFEteDOrRVDPdrOSD6wxOtSsVCaipTsUBJ VybrNVMZ1pGZ8EMG5kVlS8LXOnhSZQ3RgJhPraoFTrvWCaVNt80hw/wHotKqivP2Er8v nbolrtpntOtkjNT4yhBIZQhxGzJwNPlWDhYxsQEfojSi6Hc5CxQH1j7B+uL5Kfl8gl/m bNVOzpMaSt6xUSjbCahka3B3DczOeAKdOXDNMhxsIy8xxTV1lYLiOdJKqiJd8u25Qg28 7a5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766127563; x=1766732363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=gg3gwEOyjqDDo8XAcNT9mbGI0dzn97wIDkd7TasSApU=; b=Z0Y44RwYWQiSxw2lXu/GEK2DlyN2nX1dq9OHvI6LAcf3f2fz6sdSu7bJjViXmd9yRt 68rqsC+IYNEn5NyTx/HtE3P3ABU25quOc9cUjjc3ObE8y+mxNy0xam1t7RtxGSrQDCW+ 1EsIUMHshcR0w7juiozSkNIlL9VBNm+sd2B8IhgxUe0YP2mtWXcUhkIQhyNlehrp01xz oCYPYXYZqNl9UYo2Oo1w4Cmqf1iXQxFT9/xAGi5OkqSD2f9PqEs55/H3VG+KPgN4OBZ9 cRR9mO2pmtkbGQWyi5xGu1+IyGzRgY1bl1KkdnoW0TrI7CbxYwbugvokiCRO9rRYOCRj N5Hg== X-Forwarded-Encrypted: i=1; AJvYcCUY7kzzpPTCHXvXWbt09Ocx8Yd5tzeo0SxjsI8aojT8sxAGm8KTJVW78cEGp4XxqiXDkcI8otq5dKohC+I=@vger.kernel.org X-Gm-Message-State: AOJu0Yx+uaprpv+D9Mp9Lk1YxhdBjmSwrl6weCkTP9lT5cNjI8+mZfnQ dNfAGhtWEHIyv/jdKGwt4+K1IzuoUc5j856DlPNJ6+HdagXg45YdqhYLWvga5VqwrUKrnKf0WN+ 5uH/xNLTYC5CFKy6HQ1rt+FtFD/1mxKdV81lCtQFIG8j0jTSKK4Inq208F4fOnHxFvWE= X-Gm-Gg: AY/fxX7Xlq5WTFqWm51XHP4cnzVzgG5SkH/Hrpu3jrYr7FxBBHLDUmB8ahCDg7yzmsx UdBwsh2Io2rhTSoGtxMT7osTgfqj78w+qj1qYKVN7c4ZFIoa5ij+a0eHZu2MSrD3eIBArXRTaqP 8uHrGIxDKBQHxs7oLsOpfs3/a0lvedNTcZbtD/bABWCGmSOC1tZxWSVgJ+rj8ucXMo3dWxr39sI 2SuI5t/3rJXQn/QNsUFq+mGTC1WoAPh4grvMYdttMIVrRIiVK+ahQrOChOWgFbXqyv8OEHXIx+7 QtEH/JUoVWUkCbktTDZUxRaiuium2ziEi3eg78MUNHbWmRmU/APok2nyJdG4Bj6TwI3PbQr8SpL tVi06tFMFHbg3DODAe0SuBzYncDogyVaylbnsTehZCzgfQb52zL/oVxNrS2Ttxu1B X-Received: by 2002:a05:7301:fa9:b0:2ae:6024:7a49 with SMTP id 5a478bee46e88-2b05ec6b9c4mr1744296eec.30.1766127563296; Thu, 18 Dec 2025 22:59:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IEJYvLZaWSPBDBbbKCP8gOigcENQ7QN2bMNns3ZqbINApzk9Ho2Lh06XOVZ26jmC/iDkr57WQ== X-Received: by 2002:a05:7301:fa9:b0:2ae:6024:7a49 with SMTP id 5a478bee46e88-2b05ec6b9c4mr1744273eec.30.1766127562681; Thu, 18 Dec 2025 22:59:22 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b05fcfc1b7sm3614954eec.0.2025.12.18.22.59.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 22:59:22 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v9 2/7] qcom-tgu: Add TGU driver Date: Thu, 18 Dec 2025 22:58:57 -0800 Message-Id: <20251219065902.2296896-3-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> References: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: t7NmvYeHARHYfvXIK5LUfvGGMVRcO_S2 X-Proofpoint-ORIG-GUID: t7NmvYeHARHYfvXIK5LUfvGGMVRcO_S2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA1NiBTYWx0ZWRfX1LcZ6TkaEUMX YmHetjQT2Q51M8k00eVdE5Vzjn6kSGPSmbtQpuTVSmiQCCMbRFfF7Dr29MC+iQP551ISYsu2bhf h23Doww613ESQ61/poVjaeygw4icjhqjNzdL1L0RI1FLeIn29nrjdJaUOQVWsRjQ6K0JqV7q2BM 2aMWVYlvHWu12CPv4qI4qW5nQfBOpblJGhEyw/UJBMfER7s+y0zD3D9EmML7g1eYNq3JRKhIgTq 5u3AUdB0tiA222HYI2PqHTWoO6TmPKnpu1OUqqnLFJP5v6ri+Vok/AMZMp0cjSKYZYRwkhNky1b z9rJAnDaYvrDjts3Y3Q+YE3Qc6UTvqMa+ZioockvE+kjyBb8ZfGrdGV8GcCbHGpx/6WsvJLX6lh HorLJPy2Wbjz3VHheNbKwp4oQaYKYypyrT08n+iiIzB/9ktYAE7DH34v7sNgxtZTjOmUngtqctB SmAxFb+ZoziMIbM3Isw== X-Authority-Analysis: v=2.4 cv=WYwBqkhX c=1 sm=1 tr=0 ts=6944f7cc cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=h99DN6MNysFgGb7_OMAA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_02,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 phishscore=0 adultscore=0 suspectscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190056 Content-Type: text/plain; charset="utf-8" Add driver to support device TGU (Trigger Generation Unit). TGU is a Data Engine which can be utilized to sense a plurality of signals and create a trigger into the CTI or generate interrupts to processors. Add probe/enable/disable functions for tgu. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 9 + drivers/Makefile | 1 + drivers/hwtracing/Kconfig | 2 + drivers/hwtracing/qcom/Kconfig | 18 ++ drivers/hwtracing/qcom/Makefile | 3 + drivers/hwtracing/qcom/tgu.c | 178 ++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 51 +++++ 7 files changed, 262 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-amba-devices-tgu create mode 100644 drivers/hwtracing/qcom/Kconfig create mode 100644 drivers/hwtracing/qcom/Makefile create mode 100644 drivers/hwtracing/qcom/tgu.c create mode 100644 drivers/hwtracing/qcom/tgu.h diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu new file mode 100644 index 000000000000..24dcdf1d70cc --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -0,0 +1,9 @@ +What: /sys/bus/amba/devices//enable_tgu +Date: December 2025 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the enable/disable status of TGU + Accepts only one of the 2 values - 0 or 1. + 0 : disable TGU. + 1 : enable TGU. diff --git a/drivers/Makefile b/drivers/Makefile index ccc05f1eae3e..9608a3debb1f 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -177,6 +177,7 @@ obj-$(CONFIG_RAS) +=3D ras/ obj-$(CONFIG_USB4) +=3D thunderbolt/ obj-$(CONFIG_CORESIGHT) +=3D hwtracing/coresight/ obj-y +=3D hwtracing/intel_th/ +obj-y +=3D hwtracing/qcom/ obj-$(CONFIG_STM) +=3D hwtracing/stm/ obj-$(CONFIG_HISI_PTT) +=3D hwtracing/ptt/ obj-y +=3D android/ diff --git a/drivers/hwtracing/Kconfig b/drivers/hwtracing/Kconfig index 911ee977103c..8a640218eed8 100644 --- a/drivers/hwtracing/Kconfig +++ b/drivers/hwtracing/Kconfig @@ -7,4 +7,6 @@ source "drivers/hwtracing/intel_th/Kconfig" =20 source "drivers/hwtracing/ptt/Kconfig" =20 +source "drivers/hwtracing/qcom/Kconfig" + endmenu diff --git a/drivers/hwtracing/qcom/Kconfig b/drivers/hwtracing/qcom/Kconfig new file mode 100644 index 000000000000..d6f6d4b0f28e --- /dev/null +++ b/drivers/hwtracing/qcom/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# QCOM specific hwtracing drivers +# +menu "Qualcomm specific hwtracing drivers" + +config QCOM_TGU + tristate "QCOM Trigger Generation Unit driver" + help + This driver provides support for Trigger Generation Unit that is + used to detect patterns or sequences on a given set of signals. + TGU is used to monitor a particular bus within a given region to + detect illegal transaction sequences or slave responses. It is also + used to monitor a data stream to detect protocol violations and to + provide a trigger point for centering data around a specific event + within the trace data buffer. + +endmenu diff --git a/drivers/hwtracing/qcom/Makefile b/drivers/hwtracing/qcom/Makef= ile new file mode 100644 index 000000000000..5a0a868c1ea0 --- /dev/null +++ b/drivers/hwtracing/qcom/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_QCOM_TGU) +=3D tgu.o diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c new file mode 100644 index 000000000000..dbd1acbd2fa5 --- /dev/null +++ b/drivers/hwtracing/qcom/tgu.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tgu.h" + +static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) +{ + TGU_UNLOCK(drvdata->base); + /* Enable TGU to program the triggers */ + writel(1, drvdata->base + TGU_CONTROL); + TGU_LOCK(drvdata->base); +} + +static int tgu_enable(struct device *dev) +{ + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + + guard(spinlock)(&drvdata->lock); + if (drvdata->enable) + return -EBUSY; + + tgu_write_all_hw_regs(drvdata); + drvdata->enable =3D true; + + return 0; +} + +static int tgu_disable(struct device *dev) +{ + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + + guard(spinlock)(&drvdata->lock); + if (drvdata->enable) { + TGU_UNLOCK(drvdata->base); + writel(0, drvdata->base + TGU_CONTROL); + TGU_LOCK(drvdata->base); + + drvdata->enable =3D false; + } + return 0; +} + +static ssize_t enable_tgu_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + bool enabled; + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + + guard(spinlock)(&drvdata->lock); + enabled =3D drvdata->enable; + + return sysfs_emit(buf, "%d\n", enabled); +} + +/* enable_tgu_store - Configure Trace and Gating Unit (TGU) triggers. */ +static ssize_t enable_tgu_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + int ret =3D 0; + unsigned long val; + + ret =3D kstrtoul(buf, 0, &val); + if (ret) + return ret; + + if (val) { + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + ret =3D tgu_enable(dev); + if (ret) + pm_runtime_put(dev); + } else { + ret =3D tgu_disable(dev); + pm_runtime_put(dev); + } + + if (ret) + return ret; + return size; +} +static DEVICE_ATTR_RW(enable_tgu); + +static struct attribute *tgu_common_attrs[] =3D { + &dev_attr_enable_tgu.attr, + NULL, +}; + +static const struct attribute_group tgu_common_grp =3D { + .attrs =3D tgu_common_attrs, + NULL, +}; + +static const struct attribute_group *tgu_attr_groups[] =3D { + &tgu_common_grp, + NULL, +}; + +static int tgu_probe(struct amba_device *adev, const struct amba_id *id) +{ + struct device *dev =3D &adev->dev; + struct tgu_drvdata *drvdata; + int ret; + + drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev =3D &adev->dev; + dev_set_drvdata(dev, drvdata); + + drvdata->base =3D devm_ioremap_resource(dev, &adev->res); + if (IS_ERR(drvdata->base)) + return PTR_ERR(drvdata->base); + + spin_lock_init(&drvdata->lock); + + ret =3D sysfs_create_groups(&dev->kobj, tgu_attr_groups); + if (ret) { + dev_err(dev, "failed to create sysfs groups: %d\n", ret); + return ret; + } + + drvdata->enable =3D false; + + pm_runtime_put(&adev->dev); + return 0; +} + +static void tgu_remove(struct amba_device *adev) +{ + struct device *dev =3D &adev->dev; + + sysfs_remove_groups(&dev->kobj, tgu_attr_groups); + + tgu_disable(dev); + dev_set_drvdata(dev, NULL); +} + +static const struct amba_id tgu_ids[] =3D { + { + .id =3D 0x000f0e00, + .mask =3D 0x000fffff, + }, + { 0, 0, NULL }, +}; + +MODULE_DEVICE_TABLE(amba, tgu_ids); + +static struct amba_driver tgu_driver =3D { + .drv =3D { + .name =3D "qcom-tgu", + .suppress_bind_attrs =3D true, + }, + .probe =3D tgu_probe, + .remove =3D tgu_remove, + .id_table =3D tgu_ids, +}; + +module_amba_driver(tgu_driver); + +MODULE_AUTHOR("Songwei Chai "); +MODULE_AUTHOR("Jinlong Mao "); +MODULE_DESCRIPTION("Qualcomm Trigger Generation Unit driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h new file mode 100644 index 000000000000..abc732f91dfc --- /dev/null +++ b/drivers/hwtracing/qcom/tgu.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#ifndef _QCOM_TGU_H +#define _QCOM_TGU_H + +/* Register addresses */ +#define TGU_CONTROL 0x0000 +#define TGU_LAR 0xfb0 +#define TGU_UNLOCK_OFFSET 0xc5acce55 + +static inline void TGU_LOCK(void __iomem *addr) +{ + do { + /* Wait for things to settle */ + mb(); + writel_relaxed(0x0, addr + TGU_LAR); + } while (0); +} + +static inline void TGU_UNLOCK(void __iomem *addr) +{ + do { + writel_relaxed(TGU_UNLOCK_OFFSET, addr + TGU_LAR); + /* Make sure everyone has seen this */ + mb(); + } while (0); +} + +/** + * struct tgu_drvdata - Data structure for a TGU (Trigger Generator Unit) + * @base: Memory-mapped base address of the TGU device + * @dev: Pointer to the associated device structure + * @lock: Spinlock for handling concurrent access + * @enable: Flag indicating whether the TGU device is enabled + * + * This structure defines the data associated with a TGU device, + * including its base address, device pointers, clock, spinlock for + * synchronization, trigger data pointers, maximum limits for various + * trigger-related parameters, and enable status. + */ +struct tgu_drvdata { + void __iomem *base; + struct device *dev; + spinlock_t lock; + bool enable; +}; + +#endif --=20 2.34.1