From nobody Sun Feb 8 18:56:35 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B9921E520C for ; Fri, 19 Dec 2025 06:59:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127559; cv=none; b=GL5nVWj50aqtDyamiLsDAUcHPacLq4zY8J3XDMmXjbdVw5hhrlSACFt8Hz0cvzQW7LBToWGsgGUQCwuCpszIabGNQd4ux384I0Pxesl6cYS0fcSL6W4qyfVFU0c+bZyGp8hk9cEulBbNF4jZ7LKV9He7RDEMweR5VDTaEUFVLu0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127559; c=relaxed/simple; bh=6VY87t9VghiDLhppTTyGc/EGkt+kVJvSCivK71N+61o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FCDtCZU7IqcKlxgIUsyqQZgUwqybHRwdwDqrbYwimx7dPWtuBrr9ayYjbUqYfKEzOZX9hfOxVo89AgARc5eObZ4eFNQdU2WEgnN9ORRdniDCOBdVlI8RKb0Py0usPzod6ByU8vCRKxXvFHpHC8soFz5u78I5WZgKBaadqJgrRiM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=mGW11hoY; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=HbhFkftf; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="mGW11hoY"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="HbhFkftf" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJ4c83u4154543 for ; Fri, 19 Dec 2025 06:59:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=+nWc4h1iM5D mFVSbqSbzqsFj4rfaS5ymL17azyq0Eek=; b=mGW11hoYuf8oovORYJS0AOnjvkm HPkNqqdH2C0xSoFrjNRMA5LU08NVhGTzZ21Aj5ncaxpcaqxaioJyIRtca4pjea6Y deI3QoMbp94eLcrxdxi4kwHdJ15D4+9uu/NrvIBDVoRZnGm3n6s5x4POoPcaD7rb SW5UP8KXJ33xdMZbscEsuM4p2wA1qiVk32gsxidvxkLJYlLYVcrxUf5E+VQTzctm 5wn9WRhY0vdxghYg/SmtaXVMqjGvyulz7PIAJckAQX6ns8xRrTALDaAA+ZC83/IV N5n2FV77hsdJ4OZASvXVpUtihj1+aMdFVOrOGbg+TZ7dxt5gh6BuNqrnBEg== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r2csmfd-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 06:59:17 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-bc240cdb249so1373651a12.3 for ; Thu, 18 Dec 2025 22:59:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766127556; x=1766732356; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+nWc4h1iM5DmFVSbqSbzqsFj4rfaS5ymL17azyq0Eek=; b=HbhFkftfhiMzQ5SwI3vZbdZnRpQSPmFRhx/vmHekfsYNi6UNORy9+jSJ5SCQ76OdDm Jt8SL1kPwY5TrzalNLye9cvYu0h3NvS9AoikqOoxqC1B38jL6dTthWjr62CppQ0Jl78s AZMbYKhqaNw4sRXHOnuBVXu2uqRRCssgOplP2XnzyYRY4L6qHbOEKUWie/WUXBnLCbgn ZreKn+fSoAdyxgkoat6ZxnRqB3CTuvhZjBTO1fvfSTUpOU0iZOxb/IKZKXQ3ARUxshKq ORrAOPo1FGMcTUZTbnHDQjEckbqu2zukwhlsMNuLlebNxtui55Xa+ugthFz2Vz6CiCxm hQJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766127556; x=1766732356; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=+nWc4h1iM5DmFVSbqSbzqsFj4rfaS5ymL17azyq0Eek=; b=laMdSV+wbAWrG1GEYO+qyFk0LsmmHHNh43i/cq+55385LWYr12ZUHygxuSP/MDEj5j phLFMN4zyPkkTy5ABNEkB+lSUVDgIEIRsHf95jW4aslb3uljtV5vGFjEK6LyXVEcdIGV CLuzOPvZAI98H7HS2NlaLM5CMlotICTn9RDpmIzaGsAqItKu3vPaeyce6w2SR7I/M7Hv gyso9BiH/zi4GmzNwI5JK8jHgqMiZRUQl/CwjgJ14tjwJbpiBGsTtoLEmRul1iGIxg22 vMQiLkONfekCU2ORi1ialdfiS9Z2UmtG1wv41YWRS+FH5MMX8cO4RhlUN0QrSSj8BVIb dx/g== X-Forwarded-Encrypted: i=1; AJvYcCUsUt8N+d0ywsjHP7fy+uLFExEEovUwhHeE+a1w0lgM6WWN7HmaZfYRYWWJvR0DwImU/UqSyg/RuyjoDus=@vger.kernel.org X-Gm-Message-State: AOJu0YzMaaY5Knvi4y+2PDAr4hkU9X9vt0JawUBmg0p1K3JKOSH3nRVA Wy1X8AmpCxfaHQPGW0SwZXdYkV+oT6HfeW2DHJiXl7ShtB8e95ahg/Hx5eIIKIO7MD27r5+nGYU 33HU9j1z91C2L1eDHTsTtExhc5ysyNRy9TKtREEhZclajanTXDvlFOyDuRQCDEqPISao= X-Gm-Gg: AY/fxX7awnu2nfOJCFMAWdZfEXtlcG/9qyDW0DZI0208zpMa/JLedIB3FR8nJeq95Mb /LLzQVYFsbmC2AjZnbYHBKIuITq5xCJQ3GxuJi8HwEhzpq97+TZVu2CN4d+YVGLcqGB/2cmKUGL SphtMAO9I3AibjlKhNex7mAOvcs8gPEaJRZY32x4DxtWtwW5Fy0/eEkbIk0KPG8dKPDdpgDUt7p wfhfVKV63+LO0shVxwvrB0mDFEjAP9s2zoVwG+xA2RaoQyiIAJRPzs3ps4i9T/0rHO+ffW73MZt DK/YUxSrS+X4s03ArJsehCosOvB2BRndoHyjK42H6rpk/VKriJlH/cHU8EJM37aeQ/Sxk6JBhsB mXn9AADVIdc/bGxaLEdyKlSiUXVDnkM7uRQHorc4UMvRf0VklgizwAjquCEgeSi8c X-Received: by 2002:a05:7022:6894:b0:119:e55a:9bff with SMTP id a92af1059eb24-121722dd666mr1906794c88.27.1766127556258; Thu, 18 Dec 2025 22:59:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IF3MkjuJpL3ndfq28woc+DY1x5eft/ObZXlyr5BZCx9Z/dRnigx/T/e88b6txTPhWXxGRLPYQ== X-Received: by 2002:a05:7022:6894:b0:119:e55a:9bff with SMTP id a92af1059eb24-121722dd666mr1906767c88.27.1766127555681; Thu, 18 Dec 2025 22:59:15 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b05fcfc1b7sm3614954eec.0.2025.12.18.22.59.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 22:59:15 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, Rob Herring Subject: [PATCH v9 1/7] dt-bindings: arm: Add support for Qualcomm TGU trace Date: Thu, 18 Dec 2025 22:58:56 -0800 Message-Id: <20251219065902.2296896-2-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> References: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: yw0uEul1QFL8mRu-25jquxBZNW4wdtxS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA1NiBTYWx0ZWRfX040JWJsWId6w NWDhjrITA3cqnzzKofRc7tt0FTPW8KrQUJrwSkcD/V7SgKgtn2LzELVX1dvIO+ROEpKBxalvEyC z7lTbG3CwNeAjX8y7yeEXbr4oyrsRrdfETrSVMRzlnv/rsbwss9dhAlt4hm5ilH2ZbSvci0ASft iwRYpnR+0UPD3H6SnU/J8DFOR1B/K9Kgtqk8XOkzwg6jMIcdYcy43J7woICCsi3etEsgTLc98TH iuW8pIPuiMd+ytNp4vPq8sEpald9m7waak9SNYZyXz14kvgr1u7SBmFURswiNZTWlYipxei2VTY EtjO4o3hWzOlSJSq19+8KasFKe4R1jiQcWqi6y1ARxKiMCI4FuToO+2nPltEgt8lK558nW7MzfJ JKLREOUHDIcfMH6rWLYbwAgxQynWr89FUhNwSHNFlevjKaXxZVIGKpBw/YtBHORhFoclaEe5FxQ xtpCRHE7uvgPoi9nY7g== X-Proofpoint-ORIG-GUID: yw0uEul1QFL8mRu-25jquxBZNW4wdtxS X-Authority-Analysis: v=2.4 cv=Lp2fC3dc c=1 sm=1 tr=0 ts=6944f7c5 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=N3VNWiZ0WD7Ir0aJMQYA:9 a=x9snwWr2DeNwDh03kgHS:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_02,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190056 Content-Type: text/plain; charset="utf-8" The Trigger Generation Unit (TGU) is designed to detect patterns or sequences within a specific region of the System on Chip (SoC). Once configured and activated, it monitors sense inputs and can detect a pre-programmed state or sequence across clock cycles, subsequently producing a trigger. TGU configuration space offset table x-------------------------x | | | | | | Step configuration | | space layout | coresight management | x-------------x | registers | |---> | | | | | | reserve | | | | | | |-------------------------| | |-------------| | | | | priority[3] | | step[7] |<-- | |-------------| |-------------------------| | | | priority[2] | | | | | |-------------| | ... | |Steps region | | priority[1] | | | | | |-------------| |-------------------------| | | | priority[0] | | |<-- | |-------------| | step[0] |--------------------> | | |-------------------------| | condition | | | | | | control and status | x-------------x | space | | | x-------------------------x |Timer/Counter| | | x-------------x TGU Configuration in Hardware The TGU provides a step region for user configuration, similar to a flow chart. Each step region consists of three register clusters: 1.Priority Region: Sets the required signals with priority. 2.Condition Region: Defines specific requirements (e.g., signal A reaches three times) and the subsequent action once the requirement is met. 3.Timer/Counter (Optional): Provides timing or counting functionality. Add a new tgu.yaml file to describe the bindings required to define the TGU in the device trees. Reviewed-by: Rob Herring (Arm) Signed-off-by: Songwei Chai --- .../devicetree/bindings/arm/qcom,tgu.yaml | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,tgu.yaml diff --git a/Documentation/devicetree/bindings/arm/qcom,tgu.yaml b/Document= ation/devicetree/bindings/arm/qcom,tgu.yaml new file mode 100644 index 000000000000..5b6a58ebe691 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,tgu.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,tgu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trigger Generation Unit - TGU + +description: | + The Trigger Generation Unit (TGU) is a Data Engine which can be utilized + to sense a plurality of signals and create a trigger into the CTI or + generate interrupts to processors. The TGU is like the trigger circuit + of a Logic Analyzer. The corresponding trigger logic can be realized by + configuring the conditions for each step after sensing the signal. + Once setup and enabled, it will observe sense inputs and based upon + the activity of those inputs, even over clock cycles, may detect a + preprogrammed state/sequence and then produce a trigger or interrupt. + + The primary use case of the TGU is to detect patterns or sequences on a + given set of signals within some region to identify the issue in time + once there is abnormal behavior in the subsystem. + +maintainers: + - Mao Jinlong + - Songwei Chai + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,tgu + required: + - compatible + +properties: + compatible: + items: + - const: qcom,tgu + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: + The port mechanism here ensures the relationship between TGU and + TPDM, as TPDM is one of the inputs for TGU. It will allow TGU to + function as TPDM's helper and enable TGU when the connected + TPDM is enabled. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + tgu@10b0e000 { + compatible =3D "qcom,tgu", "arm,primecell"; + reg =3D <0x10b0e000 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + tgu_in_tpdm_swao: endpoint{ + remote-endpoint =3D <&tpdm_swao_out_tgu>; + }; + }; + }; + }; +... --=20 2.34.1 From nobody Sun Feb 8 18:56:35 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21A9D2DEA6B for ; Fri, 19 Dec 2025 06:59:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127567; cv=none; b=C6U2ZvBwECs4iMklVlgORl6qxx3PMw8UQliQxbFi3bBsZJmx/P4ak+003SmKDaMj+6yMYeHm2VrKAgXgIX2xmZ6Uz4MGLLBim1JZ75G7f1gGXuAeTglCI3rPa2aP//qiGsg4gZ+kJkMT5O58tcA9xrTsp6sJ77ddrtOVAM2411k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127567; c=relaxed/simple; bh=BKxmPAIfDQMipphXpdmD/EV9MfAn1lh12oL7+7IANCg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cfjJWr9cHRytxDeJ5kEroEHT7QOKUh06WKxURP0307WAcepbt33VJmb1m4hHrxQUzUzGNAbuADI+fbFSUD3mgdDoZ+rnEVB6vnv6sTCBy9BlzdH5GcOAIg3rVZau7d+EP+jSkKte9tu9oV8G+3aJpbEXfB8EQVPoidXzcUz+iDc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=i73Fm+4M; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=MQDlffK0; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="i73Fm+4M"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="MQDlffK0" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJ4cQXk1771762 for ; Fri, 19 Dec 2025 06:59:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=gg3gwEOyjqD Do8XAcNT9mbGI0dzn97wIDkd7TasSApU=; b=i73Fm+4MlspXLrUZRqd2ihCFV6j OrRdU+eetmwJo4ZO3fHeplG9u/N9HcETn0nB++YgWTE1yw1kf+6sG3vTKB8xSeoU HLBGHshk0xVBV77LluHUKARPxQt0uxwFo4q1Ig7NODhdmMEfdUG30ESBcwImLjq2 SX9ZuNIj+Dru3dvZ6UaYmwahICGRVCeFbQM3ezdElcsQusoPWqOmOcrfgAUnd4mI 43LYdogKprndNnNPWs4KVa8KuWms4cOHQWJvgFg7voHemjpsRuvRdHrIuuxa8u5A SeVqCFYzK0Iy+WRpaL9IQF+U6aILNxZTEnxhUAkKUZFw0n/f4Dg23QkzEFw== Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r2bhmbn-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 06:59:24 +0000 (GMT) Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-ba4c6ac8406so1256869a12.0 for ; Thu, 18 Dec 2025 22:59:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766127563; x=1766732363; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gg3gwEOyjqDDo8XAcNT9mbGI0dzn97wIDkd7TasSApU=; b=MQDlffK0j3qwdAscJdscsyR7slrhEzueh2lbR9Y57BinAR91moC3P9OPcG8EFK4Prn WfFXQ1mWDg5QRsDtQ9Bm4RLopvBe7sSAyrpFEteDOrRVDPdrOSD6wxOtSsVCaipTsUBJ VybrNVMZ1pGZ8EMG5kVlS8LXOnhSZQ3RgJhPraoFTrvWCaVNt80hw/wHotKqivP2Er8v nbolrtpntOtkjNT4yhBIZQhxGzJwNPlWDhYxsQEfojSi6Hc5CxQH1j7B+uL5Kfl8gl/m bNVOzpMaSt6xUSjbCahka3B3DczOeAKdOXDNMhxsIy8xxTV1lYLiOdJKqiJd8u25Qg28 7a5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766127563; x=1766732363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=gg3gwEOyjqDDo8XAcNT9mbGI0dzn97wIDkd7TasSApU=; b=Z0Y44RwYWQiSxw2lXu/GEK2DlyN2nX1dq9OHvI6LAcf3f2fz6sdSu7bJjViXmd9yRt 68rqsC+IYNEn5NyTx/HtE3P3ABU25quOc9cUjjc3ObE8y+mxNy0xam1t7RtxGSrQDCW+ 1EsIUMHshcR0w7juiozSkNIlL9VBNm+sd2B8IhgxUe0YP2mtWXcUhkIQhyNlehrp01xz oCYPYXYZqNl9UYo2Oo1w4Cmqf1iXQxFT9/xAGi5OkqSD2f9PqEs55/H3VG+KPgN4OBZ9 cRR9mO2pmtkbGQWyi5xGu1+IyGzRgY1bl1KkdnoW0TrI7CbxYwbugvokiCRO9rRYOCRj N5Hg== X-Forwarded-Encrypted: i=1; AJvYcCUY7kzzpPTCHXvXWbt09Ocx8Yd5tzeo0SxjsI8aojT8sxAGm8KTJVW78cEGp4XxqiXDkcI8otq5dKohC+I=@vger.kernel.org X-Gm-Message-State: AOJu0Yx+uaprpv+D9Mp9Lk1YxhdBjmSwrl6weCkTP9lT5cNjI8+mZfnQ dNfAGhtWEHIyv/jdKGwt4+K1IzuoUc5j856DlPNJ6+HdagXg45YdqhYLWvga5VqwrUKrnKf0WN+ 5uH/xNLTYC5CFKy6HQ1rt+FtFD/1mxKdV81lCtQFIG8j0jTSKK4Inq208F4fOnHxFvWE= X-Gm-Gg: AY/fxX7Xlq5WTFqWm51XHP4cnzVzgG5SkH/Hrpu3jrYr7FxBBHLDUmB8ahCDg7yzmsx UdBwsh2Io2rhTSoGtxMT7osTgfqj78w+qj1qYKVN7c4ZFIoa5ij+a0eHZu2MSrD3eIBArXRTaqP 8uHrGIxDKBQHxs7oLsOpfs3/a0lvedNTcZbtD/bABWCGmSOC1tZxWSVgJ+rj8ucXMo3dWxr39sI 2SuI5t/3rJXQn/QNsUFq+mGTC1WoAPh4grvMYdttMIVrRIiVK+ahQrOChOWgFbXqyv8OEHXIx+7 QtEH/JUoVWUkCbktTDZUxRaiuium2ziEi3eg78MUNHbWmRmU/APok2nyJdG4Bj6TwI3PbQr8SpL tVi06tFMFHbg3DODAe0SuBzYncDogyVaylbnsTehZCzgfQb52zL/oVxNrS2Ttxu1B X-Received: by 2002:a05:7301:fa9:b0:2ae:6024:7a49 with SMTP id 5a478bee46e88-2b05ec6b9c4mr1744296eec.30.1766127563296; Thu, 18 Dec 2025 22:59:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IEJYvLZaWSPBDBbbKCP8gOigcENQ7QN2bMNns3ZqbINApzk9Ho2Lh06XOVZ26jmC/iDkr57WQ== X-Received: by 2002:a05:7301:fa9:b0:2ae:6024:7a49 with SMTP id 5a478bee46e88-2b05ec6b9c4mr1744273eec.30.1766127562681; Thu, 18 Dec 2025 22:59:22 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b05fcfc1b7sm3614954eec.0.2025.12.18.22.59.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 22:59:22 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v9 2/7] qcom-tgu: Add TGU driver Date: Thu, 18 Dec 2025 22:58:57 -0800 Message-Id: <20251219065902.2296896-3-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> References: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: t7NmvYeHARHYfvXIK5LUfvGGMVRcO_S2 X-Proofpoint-ORIG-GUID: t7NmvYeHARHYfvXIK5LUfvGGMVRcO_S2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA1NiBTYWx0ZWRfX1LcZ6TkaEUMX YmHetjQT2Q51M8k00eVdE5Vzjn6kSGPSmbtQpuTVSmiQCCMbRFfF7Dr29MC+iQP551ISYsu2bhf h23Doww613ESQ61/poVjaeygw4icjhqjNzdL1L0RI1FLeIn29nrjdJaUOQVWsRjQ6K0JqV7q2BM 2aMWVYlvHWu12CPv4qI4qW5nQfBOpblJGhEyw/UJBMfER7s+y0zD3D9EmML7g1eYNq3JRKhIgTq 5u3AUdB0tiA222HYI2PqHTWoO6TmPKnpu1OUqqnLFJP5v6ri+Vok/AMZMp0cjSKYZYRwkhNky1b z9rJAnDaYvrDjts3Y3Q+YE3Qc6UTvqMa+ZioockvE+kjyBb8ZfGrdGV8GcCbHGpx/6WsvJLX6lh HorLJPy2Wbjz3VHheNbKwp4oQaYKYypyrT08n+iiIzB/9ktYAE7DH34v7sNgxtZTjOmUngtqctB SmAxFb+ZoziMIbM3Isw== X-Authority-Analysis: v=2.4 cv=WYwBqkhX c=1 sm=1 tr=0 ts=6944f7cc cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=h99DN6MNysFgGb7_OMAA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_02,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 phishscore=0 adultscore=0 suspectscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190056 Content-Type: text/plain; charset="utf-8" Add driver to support device TGU (Trigger Generation Unit). TGU is a Data Engine which can be utilized to sense a plurality of signals and create a trigger into the CTI or generate interrupts to processors. Add probe/enable/disable functions for tgu. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 9 + drivers/Makefile | 1 + drivers/hwtracing/Kconfig | 2 + drivers/hwtracing/qcom/Kconfig | 18 ++ drivers/hwtracing/qcom/Makefile | 3 + drivers/hwtracing/qcom/tgu.c | 178 ++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 51 +++++ 7 files changed, 262 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-amba-devices-tgu create mode 100644 drivers/hwtracing/qcom/Kconfig create mode 100644 drivers/hwtracing/qcom/Makefile create mode 100644 drivers/hwtracing/qcom/tgu.c create mode 100644 drivers/hwtracing/qcom/tgu.h diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu new file mode 100644 index 000000000000..24dcdf1d70cc --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -0,0 +1,9 @@ +What: /sys/bus/amba/devices//enable_tgu +Date: December 2025 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the enable/disable status of TGU + Accepts only one of the 2 values - 0 or 1. + 0 : disable TGU. + 1 : enable TGU. diff --git a/drivers/Makefile b/drivers/Makefile index ccc05f1eae3e..9608a3debb1f 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -177,6 +177,7 @@ obj-$(CONFIG_RAS) +=3D ras/ obj-$(CONFIG_USB4) +=3D thunderbolt/ obj-$(CONFIG_CORESIGHT) +=3D hwtracing/coresight/ obj-y +=3D hwtracing/intel_th/ +obj-y +=3D hwtracing/qcom/ obj-$(CONFIG_STM) +=3D hwtracing/stm/ obj-$(CONFIG_HISI_PTT) +=3D hwtracing/ptt/ obj-y +=3D android/ diff --git a/drivers/hwtracing/Kconfig b/drivers/hwtracing/Kconfig index 911ee977103c..8a640218eed8 100644 --- a/drivers/hwtracing/Kconfig +++ b/drivers/hwtracing/Kconfig @@ -7,4 +7,6 @@ source "drivers/hwtracing/intel_th/Kconfig" =20 source "drivers/hwtracing/ptt/Kconfig" =20 +source "drivers/hwtracing/qcom/Kconfig" + endmenu diff --git a/drivers/hwtracing/qcom/Kconfig b/drivers/hwtracing/qcom/Kconfig new file mode 100644 index 000000000000..d6f6d4b0f28e --- /dev/null +++ b/drivers/hwtracing/qcom/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# QCOM specific hwtracing drivers +# +menu "Qualcomm specific hwtracing drivers" + +config QCOM_TGU + tristate "QCOM Trigger Generation Unit driver" + help + This driver provides support for Trigger Generation Unit that is + used to detect patterns or sequences on a given set of signals. + TGU is used to monitor a particular bus within a given region to + detect illegal transaction sequences or slave responses. It is also + used to monitor a data stream to detect protocol violations and to + provide a trigger point for centering data around a specific event + within the trace data buffer. + +endmenu diff --git a/drivers/hwtracing/qcom/Makefile b/drivers/hwtracing/qcom/Makef= ile new file mode 100644 index 000000000000..5a0a868c1ea0 --- /dev/null +++ b/drivers/hwtracing/qcom/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_QCOM_TGU) +=3D tgu.o diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c new file mode 100644 index 000000000000..dbd1acbd2fa5 --- /dev/null +++ b/drivers/hwtracing/qcom/tgu.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tgu.h" + +static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) +{ + TGU_UNLOCK(drvdata->base); + /* Enable TGU to program the triggers */ + writel(1, drvdata->base + TGU_CONTROL); + TGU_LOCK(drvdata->base); +} + +static int tgu_enable(struct device *dev) +{ + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + + guard(spinlock)(&drvdata->lock); + if (drvdata->enable) + return -EBUSY; + + tgu_write_all_hw_regs(drvdata); + drvdata->enable =3D true; + + return 0; +} + +static int tgu_disable(struct device *dev) +{ + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + + guard(spinlock)(&drvdata->lock); + if (drvdata->enable) { + TGU_UNLOCK(drvdata->base); + writel(0, drvdata->base + TGU_CONTROL); + TGU_LOCK(drvdata->base); + + drvdata->enable =3D false; + } + return 0; +} + +static ssize_t enable_tgu_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + bool enabled; + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + + guard(spinlock)(&drvdata->lock); + enabled =3D drvdata->enable; + + return sysfs_emit(buf, "%d\n", enabled); +} + +/* enable_tgu_store - Configure Trace and Gating Unit (TGU) triggers. */ +static ssize_t enable_tgu_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + int ret =3D 0; + unsigned long val; + + ret =3D kstrtoul(buf, 0, &val); + if (ret) + return ret; + + if (val) { + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + ret =3D tgu_enable(dev); + if (ret) + pm_runtime_put(dev); + } else { + ret =3D tgu_disable(dev); + pm_runtime_put(dev); + } + + if (ret) + return ret; + return size; +} +static DEVICE_ATTR_RW(enable_tgu); + +static struct attribute *tgu_common_attrs[] =3D { + &dev_attr_enable_tgu.attr, + NULL, +}; + +static const struct attribute_group tgu_common_grp =3D { + .attrs =3D tgu_common_attrs, + NULL, +}; + +static const struct attribute_group *tgu_attr_groups[] =3D { + &tgu_common_grp, + NULL, +}; + +static int tgu_probe(struct amba_device *adev, const struct amba_id *id) +{ + struct device *dev =3D &adev->dev; + struct tgu_drvdata *drvdata; + int ret; + + drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev =3D &adev->dev; + dev_set_drvdata(dev, drvdata); + + drvdata->base =3D devm_ioremap_resource(dev, &adev->res); + if (IS_ERR(drvdata->base)) + return PTR_ERR(drvdata->base); + + spin_lock_init(&drvdata->lock); + + ret =3D sysfs_create_groups(&dev->kobj, tgu_attr_groups); + if (ret) { + dev_err(dev, "failed to create sysfs groups: %d\n", ret); + return ret; + } + + drvdata->enable =3D false; + + pm_runtime_put(&adev->dev); + return 0; +} + +static void tgu_remove(struct amba_device *adev) +{ + struct device *dev =3D &adev->dev; + + sysfs_remove_groups(&dev->kobj, tgu_attr_groups); + + tgu_disable(dev); + dev_set_drvdata(dev, NULL); +} + +static const struct amba_id tgu_ids[] =3D { + { + .id =3D 0x000f0e00, + .mask =3D 0x000fffff, + }, + { 0, 0, NULL }, +}; + +MODULE_DEVICE_TABLE(amba, tgu_ids); + +static struct amba_driver tgu_driver =3D { + .drv =3D { + .name =3D "qcom-tgu", + .suppress_bind_attrs =3D true, + }, + .probe =3D tgu_probe, + .remove =3D tgu_remove, + .id_table =3D tgu_ids, +}; + +module_amba_driver(tgu_driver); + +MODULE_AUTHOR("Songwei Chai "); +MODULE_AUTHOR("Jinlong Mao "); +MODULE_DESCRIPTION("Qualcomm Trigger Generation Unit driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h new file mode 100644 index 000000000000..abc732f91dfc --- /dev/null +++ b/drivers/hwtracing/qcom/tgu.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#ifndef _QCOM_TGU_H +#define _QCOM_TGU_H + +/* Register addresses */ +#define TGU_CONTROL 0x0000 +#define TGU_LAR 0xfb0 +#define TGU_UNLOCK_OFFSET 0xc5acce55 + +static inline void TGU_LOCK(void __iomem *addr) +{ + do { + /* Wait for things to settle */ + mb(); + writel_relaxed(0x0, addr + TGU_LAR); + } while (0); +} + +static inline void TGU_UNLOCK(void __iomem *addr) +{ + do { + writel_relaxed(TGU_UNLOCK_OFFSET, addr + TGU_LAR); + /* Make sure everyone has seen this */ + mb(); + } while (0); +} + +/** + * struct tgu_drvdata - Data structure for a TGU (Trigger Generator Unit) + * @base: Memory-mapped base address of the TGU device + * @dev: Pointer to the associated device structure + * @lock: Spinlock for handling concurrent access + * @enable: Flag indicating whether the TGU device is enabled + * + * This structure defines the data associated with a TGU device, + * including its base address, device pointers, clock, spinlock for + * synchronization, trigger data pointers, maximum limits for various + * trigger-related parameters, and enable status. + */ +struct tgu_drvdata { + void __iomem *base; + struct device *dev; + spinlock_t lock; + bool enable; +}; + +#endif --=20 2.34.1 From nobody Sun Feb 8 18:56:35 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98E9B2DE70C for ; Fri, 19 Dec 2025 06:59:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127569; cv=none; b=RwbsAW8rQu1TpJ21jmZj1dsrmsyBvr1jfHRdu44caNj31xCilyF+1Tnrgq+F6Z87PuB0uv1WC7DULfPP7hsxn7IrXrnxcsLiaNHvNn3wIQtDcqA+Vko1sIoIhfI4RPEnobsV6ZaDdSLbJ5rYXIBHYeDDv4b2/5hYyIraQIMltLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127569; c=relaxed/simple; bh=pQNy4GCveN7Qu/ABxK5/OetS7j+SCxN1UcLjrAn7Oow=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FKmFDD5wl9Ty9y6pmw/acZY2xdFXwtVA3/9IOU+jhU+dTfTmIg//jwvn3RbbQxaK7YfxmOpKBDvmw2oLIFtDxUUOBgWzh++ttGc+jp4Ms76duQq+yQW/qcfu+OWJZTSWTUFjs+ghtYcjFHrPp4pKVe/8ND2axN36cy18/ESg0Fc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=P6uxmFKG; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=bOh9pxZ7; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="P6uxmFKG"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="bOh9pxZ7" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJ4cQxQ1771763 for ; Fri, 19 Dec 2025 06:59:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=2QRxGb/StWo v1kSxmuLjC+I9J6Chk+7rXVLQn0qvk8E=; b=P6uxmFKG7KJ4+jROCTPfhw2+EWY jGXhs6S2tHyBlxknqB7hcMHiLcFF42DFQHhjmzJYXemQ2SFm5f/773+4YyuNBnMw Grkneun47NJnLIxS+73OBbYC0yCASwcaeKLGrKhyqhYPZar0hCQSYBWsyflES4gU jA6EkOqHZcv2MddmamrC9s6mxD+3YZmJhFCBqbu+6D5mVoV1apOvIUONTIcxRG4j hpmcf1+pn36Pp+8ugNyqx2CTRnn5YLeiJyuRgdz257YEwBwjCunBxzrLAyDOwzr/ rS42jeisTwLfhBRpc+uD8nzqEaEYHGNoBdV8alPCLPqtJpPUDn69gxVckuQ== Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r2bhmbt-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 06:59:26 +0000 (GMT) Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-bc240cdb249so1373729a12.3 for ; Thu, 18 Dec 2025 22:59:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766127566; x=1766732366; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2QRxGb/StWov1kSxmuLjC+I9J6Chk+7rXVLQn0qvk8E=; b=bOh9pxZ7TXB7UbNo8xz3nN+h/vm9H2OqI8XRXWDM9tC2/6jtVfYtS5h5Hv2VJXuPdo EjhzCUS7mQcbMn/9dr32ufdyzCZ+HC4S0BseDhaUzYWTOu469/8oKfB1y+9yrtloqb1h 4N28ruG5qe9Gq5ut+zmdx3YevgsrSKmMD3fnGSjTLWQkoHY4IEUSbfdkBMdq5Ma9bgoM Tj79ZKRY09ZFVM360KpWt2CWEztLlkv0xltEkl7f3WOsG1Pa+GO0prQ2XqG8PxsaGq3r SXpG4U7g+JClp0er0Lld/ZGABvU7LlilW5N2quTzI2NVVtl77l/huGRYMGb0U+D7pB6K CYsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766127566; x=1766732366; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=2QRxGb/StWov1kSxmuLjC+I9J6Chk+7rXVLQn0qvk8E=; b=YCRPDj1b//kV3zLcZIhDUP20paMfCSxJNzq1c5PIQn+WQUn9SwLyCOW7dnaRJrOFg+ n5VRGAlGvcfQ8G8PB1f3I0uXURrBcTS2j/JKrgFqkgYizkJDbInoArbQXJhglFEzkjQd qo87BEb/NZnMtmrKxWmeTcJ5/b8CotLfeSCS7uTErEO+pz63iixAWlsKU3hsNJVN0TfK k7qrZI6yud1sCaTYCYn0qRrBUNgLY+xJU23bpjXDuzOlMeCXAimPn4KUtvSMW58X98rR 8PKpifWA7hpxXcgfzPCGRNYfD1QxHMwGb/6IUFigpod7H5fmWk26y6hSLctRpXFCJiHv tisA== X-Forwarded-Encrypted: i=1; AJvYcCXlKwanuApEo9unK7SXkaqXZ/t7y7vK3lo9Y/CI7qz5be8jBDCz4J2LHCic9oyqW3gB+8ZNgIXe+ttg5/4=@vger.kernel.org X-Gm-Message-State: AOJu0YzGprxfny/d+efFuJ3NS1hUKwZKUEh9Lm6cvQFcOllUDb9HI+dQ 5TIoIBFpn4jdgmKXQTnfHTPiqMHt5oeDrrzjQIk1JYlXLW0r0aRjmWEVLk4uf0GHG6baYv6JHIr HFInw9VgOis6bc+d5Bah3zyjHJz+msciFYj+0bI/408PXkZq3f4rYa4te+eGVmI3NSCRHNE5g/F lulA== X-Gm-Gg: AY/fxX6YErHq3qqynLE6e2ScvIB2Jyghi6Jxs5cD9ie1hVfTxq3Pni/SFPAZcWgI13n 6HaIF5zDF3XaTnPDDkcYq9/Bzmjkrw6n2+HXGj67YUw6O/OoQEUhD2ZrbkwFg5+V6SBsUxoGtZE sjs5XkQVMcRxmmnKV0nWOXtLxGP8v1BB0vaxnxPNL5kyHyC4miNluQ70t4ySSnUIJyeGZR8HOl7 iGouHwxefvODNTtP78Bikf7Wi3CbGcN1W8JMF8tNlcIXKPd95uH+2RdfJQAofhvkZ1GhDVsDLI1 FHdiwZeZNI1+0Q6uH2xvRMudDkXkxjzd3v7ypsCnEnLUuQA/qEUC+r+O8KgMNsmvDVSkOPCenV6 35hHE9KvKD3W8AzaCtksAqdhK6BEjp8Ek6YAslOaSCd3qGIourj/ekS5Nb3kPc8iN X-Received: by 2002:a05:7300:c3a5:b0:2b0:4c33:8e41 with SMTP id 5a478bee46e88-2b05ec74584mr1793420eec.20.1766127565549; Thu, 18 Dec 2025 22:59:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IESgErNAe1A4QfHdcsRS/GyUFz6yunGjN9UeedKlBakXMgLoPSZCdfW9gRuNf4Qet6cdOMh1Q== X-Received: by 2002:a05:7300:c3a5:b0:2b0:4c33:8e41 with SMTP id 5a478bee46e88-2b05ec74584mr1793395eec.20.1766127564937; Thu, 18 Dec 2025 22:59:24 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b05fcfc1b7sm3614954eec.0.2025.12.18.22.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 22:59:24 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v9 3/7] qcom-tgu: Add signal priority support Date: Thu, 18 Dec 2025 22:58:58 -0800 Message-Id: <20251219065902.2296896-4-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> References: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: gEnyqRwe8VWG9KwUevl7pwi3WmQaizLl X-Proofpoint-ORIG-GUID: gEnyqRwe8VWG9KwUevl7pwi3WmQaizLl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA1NiBTYWx0ZWRfX3nbc53mUURsi KX2lux08+3z0jdHxFBRPAi/VAZfASlRdxZQ633P75wMKAyOlXYYPwPWDmr7nr1PeoGTSZuk6og1 ocZ+IrmN6UuWqHsNApyBAoOe68V08A66maKKHtI3Kcwez5dd96FkVXI5Ho3JKHwhj3ZMuS0fiH/ KB/qLPoNX6aOr4pLHC+qHjzmpvGnlp85vt1uZ+95gXUJpwsUOU5DuXIdRWhdBfMzcPu3kRKYrRk sdtNC/s6k8DJWWZ+5qYkFSO9RvCwWKL866c0y+K8nPQjiC0oeWy4OIrBgkgEZaBJi0YpwMs3Ify etVB+gDOzWEZaeFBCIwlfMYWJTar+AYqjq8QYHO+onNtWS3XXCXpdnp59CUzZVMvmjCoo90+Xb9 TPqBD+odK9ArP/86qEQENh46jJYp3UQagqTFY95MvyH0xRkTMes97WNpkQEiscIWASqfURbJp7g OTWhTuyvukQTifZsM1A== X-Authority-Analysis: v=2.4 cv=WYwBqkhX c=1 sm=1 tr=0 ts=6944f7ce cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=HMmvC-cB1bDe2h_eLOYA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_02,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 phishscore=0 adultscore=0 suspectscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190056 Content-Type: text/plain; charset="utf-8" Like circuit of a Logic analyzer, in TGU, the requirement could be configured in each step and the trigger will be created once the requirements are met. Add priority functionality here to sort the signals into different priorities. The signal which is wanted could be configured in each step's priority node, the larger number means the higher priority and the signal with higher priority will be sensed more preferentially. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 + drivers/hwtracing/qcom/tgu.c | 156 ++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 113 +++++++++++++ 3 files changed, 276 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu index 24dcdf1d70cc..d04a01368089 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -7,3 +7,10 @@ Description: Accepts only one of the 2 values - 0 or 1. 0 : disable TGU. 1 : enable TGU. + +What: /sys/bus/amba/devices//step[0:7]_priority[0:3]/reg[0:17] +Date: December 2025 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the sensed signal with specific step and priority for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index dbd1acbd2fa5..447d7e68d132 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -14,14 +14,121 @@ =20 #include "tgu.h" =20 +static int calculate_array_location(struct tgu_drvdata *drvdata, + int step_index, int operation_index, + int reg_index) +{ + return operation_index * (drvdata->max_step) * (drvdata->max_reg) + + step_index * (drvdata->max_reg) + reg_index; +} + +static ssize_t tgu_dataset_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int index; + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + struct tgu_attribute *tgu_attr =3D + container_of(attr, struct tgu_attribute, attr); + + index =3D calculate_array_location(drvdata, tgu_attr->step_index, + tgu_attr->operation_index, + tgu_attr->reg_num); + + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->priority[index]); +} + +static ssize_t tgu_dataset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int index; + unsigned long val; + + struct tgu_drvdata *tgu_drvdata =3D dev_get_drvdata(dev); + struct tgu_attribute *tgu_attr =3D + container_of(attr, struct tgu_attribute, attr); + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + guard(spinlock)(&tgu_drvdata->lock); + index =3D calculate_array_location(tgu_drvdata, tgu_attr->step_index, + tgu_attr->operation_index, + tgu_attr->reg_num); + + tgu_drvdata->value_table->priority[index] =3D val; + return size; +} + +static umode_t tgu_node_visible(struct kobject *kobject, + struct attribute *attr, + int n) +{ + struct device *dev =3D kobj_to_dev(kobject); + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + int ret =3D SYSFS_GROUP_INVISIBLE; + + struct device_attribute *dev_attr =3D + container_of(attr, struct device_attribute, attr); + struct tgu_attribute *tgu_attr =3D + container_of(dev_attr, struct tgu_attribute, attr); + + if (tgu_attr->step_index < drvdata->max_step) { + ret =3D (tgu_attr->reg_num < drvdata->max_reg) ? + attr->mode : 0; + } + return ret; +} + static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) { + int i, j, k, index; + TGU_UNLOCK(drvdata->base); + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < MAX_PRIORITY; j++) { + for (k =3D 0; k < drvdata->max_reg; k++) { + index =3D calculate_array_location( + drvdata, i, j, k); + + writel(drvdata->value_table->priority[index], + drvdata->base + + PRIORITY_REG_STEP(i, j, k)); + } + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); TGU_LOCK(drvdata->base); } =20 +static void tgu_set_reg_number(struct tgu_drvdata *drvdata) +{ + int num_sense_input; + int num_reg; + u32 devid; + + devid =3D readl(drvdata->base + TGU_DEVID); + + num_sense_input =3D TGU_DEVID_SENSE_INPUT(devid); + if (((num_sense_input * NUMBER_BITS_EACH_SIGNAL) % LENGTH_REGISTER) =3D= =3D 0) + num_reg =3D (num_sense_input * NUMBER_BITS_EACH_SIGNAL) / LENGTH_REGISTE= R; + else + num_reg =3D ((num_sense_input * NUMBER_BITS_EACH_SIGNAL) / LENGTH_REGIST= ER) + 1; + drvdata->max_reg =3D num_reg; + +} + +static void tgu_set_steps(struct tgu_drvdata *drvdata) +{ + u32 devid; + + devid =3D readl(drvdata->base + TGU_DEVID); + + drvdata->max_step =3D TGU_DEVID_STEPS(devid); +} + static int tgu_enable(struct device *dev) { struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); @@ -106,6 +213,38 @@ static const struct attribute_group tgu_common_grp =3D= { =20 static const struct attribute_group *tgu_attr_groups[] =3D { &tgu_common_grp, + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 3), NULL, }; =20 @@ -128,12 +267,29 @@ static int tgu_probe(struct amba_device *adev, const = struct amba_id *id) =20 spin_lock_init(&drvdata->lock); =20 + tgu_set_reg_number(drvdata); + tgu_set_steps(drvdata); + ret =3D sysfs_create_groups(&dev->kobj, tgu_attr_groups); if (ret) { dev_err(dev, "failed to create sysfs groups: %d\n", ret); return ret; } =20 + drvdata->value_table =3D + devm_kzalloc(dev, sizeof(*drvdata->value_table), GFP_KERNEL); + if (!drvdata->value_table) + return -ENOMEM; + + drvdata->value_table->priority =3D devm_kzalloc( + dev, + MAX_PRIORITY * drvdata->max_reg * drvdata->max_step * + sizeof(*(drvdata->value_table->priority)), + GFP_KERNEL); + + if (!drvdata->value_table->priority) + return -ENOMEM; + drvdata->enable =3D false; =20 pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index abc732f91dfc..2cf95c239ee7 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -10,6 +10,113 @@ #define TGU_CONTROL 0x0000 #define TGU_LAR 0xfb0 #define TGU_UNLOCK_OFFSET 0xc5acce55 +#define TGU_DEVID 0xfc8 + +#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) +#define TGU_DEVID_SENSE_INPUT(devid_val) ((int) BMVAL(devid_val, 10, 17)) +#define TGU_DEVID_STEPS(devid_val) ((int)BMVAL(devid_val, 3, 6)) +#define NUMBER_BITS_EACH_SIGNAL 4 +#define LENGTH_REGISTER 32 + +/* + * TGU configuration space Step configuration + * offset table space layout + * x-------------------------x$ x-------------x$ + * | |$ | |$ + * | | | reserve |$ + * | | | |$ + * |coresight management | |-------------|ba= se+n*0x1D8+0x1F4$ + * | registe | |---> |prioroty[3] |$ + * | | | |-------------|ba= se+n*0x1D8+0x194$ + * | | | |prioroty[2] |$ + * |-------------------------| | |-------------|ba= se+n*0x1D8+0x134$ + * | | | |prioroty[1] |$ + * | step[7] | | |-------------|ba= se+n*0x1D8+0xD4$ + * |-------------------------|->base+0x40+7*0x1D8 | |prioroty[0] |$ + * | | | |-------------|ba= se+n*0x1D8+0x74$ + * | ... | | | condition |$ + * | | | | select |$ + * |-------------------------|->base+0x40+1*0x1D8 | |-------------|ba= se+n*0x1D8+0x60$ + * | | | | condition |$ + * | step[0] |--------------------> | decode |$ + * |-------------------------|-> base+0x40 |-------------|ba= se+n*0x1D8+0x50$ + * | | | |$ + * | Control and status space| |Timer/Counter|$ + * | space | | |$ + * x-------------------------x->base x-------------x b= ase+n*0x1D8+0x40$ + * + */ +#define STEP_OFFSET 0x1D8 +#define PRIORITY_START_OFFSET 0x0074 +#define PRIORITY_OFFSET 0x60 +#define REG_OFFSET 0x4 + +/* Calculate compare step addresses */ +#define PRIORITY_REG_STEP(step, priority, reg)\ + (PRIORITY_START_OFFSET + PRIORITY_OFFSET * priority +\ + REG_OFFSET * reg + STEP_OFFSET * step) + +#define tgu_dataset_rw(name, step_index, type, reg_num) \ + (&((struct tgu_attribute[]){ { \ + __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ + step_index, \ + type, \ + reg_num, \ + } })[0].attr.attr) + +#define STEP_PRIORITY(step_index, reg_num, priority) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_PRIORITY##priority, \ + reg_num) + +#define STEP_PRIORITY_LIST(step_index, priority) \ + {STEP_PRIORITY(step_index, 0, priority), \ + STEP_PRIORITY(step_index, 1, priority), \ + STEP_PRIORITY(step_index, 2, priority), \ + STEP_PRIORITY(step_index, 3, priority), \ + STEP_PRIORITY(step_index, 4, priority), \ + STEP_PRIORITY(step_index, 5, priority), \ + STEP_PRIORITY(step_index, 6, priority), \ + STEP_PRIORITY(step_index, 7, priority), \ + STEP_PRIORITY(step_index, 8, priority), \ + STEP_PRIORITY(step_index, 9, priority), \ + STEP_PRIORITY(step_index, 10, priority), \ + STEP_PRIORITY(step_index, 11, priority), \ + STEP_PRIORITY(step_index, 12, priority), \ + STEP_PRIORITY(step_index, 13, priority), \ + STEP_PRIORITY(step_index, 14, priority), \ + STEP_PRIORITY(step_index, 15, priority), \ + STEP_PRIORITY(step_index, 16, priority), \ + STEP_PRIORITY(step_index, 17, priority), \ + NULL \ + } + +#define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_priority" #priority \ + }) + +enum operation_index { + TGU_PRIORITY0, + TGU_PRIORITY1, + TGU_PRIORITY2, + TGU_PRIORITY3, +}; + +/* Maximum priority that TGU supports */ +#define MAX_PRIORITY 4 + +struct tgu_attribute { + struct device_attribute attr; + u32 step_index; + enum operation_index operation_index; + u32 reg_num; +}; + +struct value_table { + unsigned int *priority; +}; =20 static inline void TGU_LOCK(void __iomem *addr) { @@ -35,6 +142,9 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @dev: Pointer to the associated device structure * @lock: Spinlock for handling concurrent access * @enable: Flag indicating whether the TGU device is enabled + * @value_table: Store given value based on relevant parameters. + * @max_reg: Maximum number of registers + * @max_step: Maximum step size * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -46,6 +156,9 @@ struct tgu_drvdata { struct device *dev; spinlock_t lock; bool enable; + struct value_table *value_table; + int max_reg; + int max_step; }; =20 #endif --=20 2.34.1 From nobody Sun Feb 8 18:56:35 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 370512D9EED for ; Fri, 19 Dec 2025 06:59:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127573; cv=none; b=hlvGx/1TLHm0VPSAMnRDkM04K0nfyOqk5mw2dBpBiMTQjiv0/WlitoIJ8+1pwP/3b/aWJnD12V+/7EI4GDMgWYHsstYNc+nScavUcF7AG09FaX3n0A8Riqi/x4TIZ2SE71R3ya1cutoQIVp+KrPGYbT7XP32Gu2ZmQOEdKUOdeo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127573; c=relaxed/simple; bh=IOPGPV7MmoA/0qT89i+KyRMOFH5+t65ggdYuvCX6SRI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WK10Wn9p9RlBFr8Ss+AYcmibtoG1DXRYJzc/4rfeyi3XqXvgpAb0uY+nc8VAsfDrqxy3/7n6eP/VcOq8nnQ8adK6plmd3ZlqfILVqYK6KHjmvx2aaDMuGkIfEzSEAxK3zhgfuT3hDgqTWbB9gbhorVm4jAnXMu449vtPSjdiU44= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=pxWxRxwj; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=M3Pp8yWj; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="pxWxRxwj"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="M3Pp8yWj" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJ4bxL24153900 for ; Fri, 19 Dec 2025 06:59:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=T2gqUfcxUo7 OzT2+W/flRobk/FmSpbVousEo4UlUkZE=; b=pxWxRxwjv3ZRFst8ig87kLvVrHb M6OkyutrIHBldwkUYff5/HDPjNi0sibQZdwTmmTeYFVsq16/8suEmIQAHPk6PA95 C3zXlBNR8Ik+pA647FVWrV0GzylkKUrXiDYaH3sLreohynUl0+jXtHXJCTR998pz eqbEU+26DLNMLKKeAJX29J5XuGoTkvbU/bdwBYSKvdz5p1SIcFGes84ClLTkxblO 1Yr4ruz0aHtM2JlOO2vy8XpbV2GJG7PyrM4s6ta7aomJwZo9Qe02m+Yo4pyyQMk4 xCygBf9h/guAtgHAqTv/Roc6eI3YSBy+rmxAqtsjKRhEYG0OP8hXmCFW/gQ== Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r2csmg5-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 06:59:30 +0000 (GMT) Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-b5edecdf94eso2543324a12.2 for ; Thu, 18 Dec 2025 22:59:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766127570; x=1766732370; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T2gqUfcxUo7OzT2+W/flRobk/FmSpbVousEo4UlUkZE=; b=M3Pp8yWjhGXn3BKx7+JWO+zia1kL8uvXzb9CTRQp9lkW+iAbxpD4L9qG87MzhwjRnR oTZtJZPwos5TPVBlJQg2clKwKrmeZmpO0pGClK+DO2AlnsbU8K5X55SVh+/XhYGyI62z 1OJQ7x3pm1pjG4D4yHQ/MTxiGF/9i5tH+Fd2GF8DtEdencU023AJ8fA6Ul0OPXmuswev R3h6RvQLt8RmEOXspXtJNDl1JVKPkCjAwOJ8kuU/1X2njktSO7nw+izT3Gsi5oCdWg6N vNDVJ5W17UfENctWO/tptM3uBXmRgny/ixr7LXrAx+7sP+IYNQNiCS4X3eWvDvYoMvlk fT1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766127570; x=1766732370; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=T2gqUfcxUo7OzT2+W/flRobk/FmSpbVousEo4UlUkZE=; b=BEKFysuh63wX5LW94dzQVARdxMGxW6irn55QTjbzuOSNKPff7MqdxfezAU86Lytdw8 Al0le64oHejcRJi7T+sSRDvM6Ltd18bXi9P2de/jRzvG8utWqVqzikVmqvXqbXeqdt0l Ve4l8cJiQw/KFJMjqV0RSI4HnMea0ro1YtpiUKJWN7bHOcdDJtg2PcKjvlz3jJYlhAIy EAOeeq6FeN4/uC9NB5c+/TGyunGIwa4LgRmMzLCGFUNMAsaXUw/bFZc4uWbwBtIoHGBX xnWRWj9u8BKh5aWHSfayB1/Lr27wOwNxTK+P9XqrfupI/BSB6fOGlQEY2Nhi3MWxi0mo +X9Q== X-Forwarded-Encrypted: i=1; AJvYcCVezOpisbipZDhFy/w31GsEwJXzIEH/Y5R6IPUxGOBGo8FhBu3p9U7XJ1z6N7WJyZKZs9Nvo5Bo8+ZCZvA=@vger.kernel.org X-Gm-Message-State: AOJu0YybtYRF/MvpChtDmiMAkqpp/GISPT0/7V8Juvdk/iHAKz1NFRnU ckIFaUhOqRBaS5Gx5VBWlr5cWjFfgQlushvXe4VoSESDc9enfuqWaxx/NZAsNQ093U56gkBm8qI LdGmZg9vJmV148tUlVgMLfgEZ9HJEYKTIt7imYebusIE3ve/jfi+38orFa9xeh9A4kYI= X-Gm-Gg: AY/fxX6j8MJbDIL26BB7AEwF0R3huUsSJDbMeqwYwLPwolI+K66z1mvO5jG13EC56S1 Qe4pqeYooaUKYVYvmyy7M351TUDNGl3geDb2p2F8d51eKKoffh9eU24J/XVgr1SeNmlPpkcADv5 v1gEuv+3Yf4ak//yXNLjHKDMgQpQB3dJh92zVC3poUDwTFiQm7VpHIfZWyiIw5gtRnQPPXogT1J nGxXqds34kJX9bMQRMeoYn1nL9CH6BUOs2OyeR19SjcNnEe2HeUoiQCl0Y57ej3LYKvJQ+7OjN6 0o/1VS1TTpZ22fR8tM9KhI1T/GFSJBgrJpahJKFEeUxdvSGtZn2UX9DKDj6+scSZr2ZoucV/4qn NWoTYe4ghIyYdRLiCNoVtLE3AKsXKsheQkRyIHE1MsfLvoVQBJFddcr+mF5PYx4kl X-Received: by 2002:a05:7300:d58b:b0:2b0:4f34:eed3 with SMTP id 5a478bee46e88-2b05ec3d5e0mr1826197eec.27.1766127569532; Thu, 18 Dec 2025 22:59:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IH7swjLusQQIOvIKFd3PQZZgezJc+x5C5ggajZ3DgdWXn3peWCSIOGlOTBo845VJVlqdE3v9A== X-Received: by 2002:a05:7300:d58b:b0:2b0:4f34:eed3 with SMTP id 5a478bee46e88-2b05ec3d5e0mr1826167eec.27.1766127568835; Thu, 18 Dec 2025 22:59:28 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b05fcfc1b7sm3614954eec.0.2025.12.18.22.59.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 22:59:28 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v9 4/7] qcom-tgu: Add TGU decode support Date: Thu, 18 Dec 2025 22:58:59 -0800 Message-Id: <20251219065902.2296896-5-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> References: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: hj3vRPtPdx6LGMbClkCYucNNK2Zq2C40 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA1NiBTYWx0ZWRfX9N3/ZdqTeHnq tqTtumXWwnAB7k+MsFy3lb2QkQb/ed4I3FxKsOeeTj3UMQask38DXpBjZmkoM2SlYm7sJZOEaDW cOS7OBics3UFrgkkutCmuu7ijKk9jhxxabX6p1i8prum+BTc/9nKb+g10cr+oZecJTQV5WQiUgj CHm1E7Bgb5AfIPyBCRO1/tVi6DWpLUQqBdzerbYpqh2ZRY6EPcIg7O6bGsFYDfWVXWEF5ri/nja HaqDMh7VfQQjMUuYbImrWjpDMHQRN7HCoznEZ+ora4u9U8WbLS61Cwx/v+Q5q9WadlS7OuHcJEv H2vTwqRlezZZHYT6myl8vtynFuKoOnByDmJ2WJkaZbI984639ZSYWvzIR7DmbNgLdDeZvI4UIYS Lkx3SYW8E2Vf8P2H4Qvb25U4k9zxocc0qdwZGwmWemqJBKQ5woDgmh2A3MeyBGfqOqYKTgxfmcs zO/heICxXaC6Ne70LaQ== X-Proofpoint-ORIG-GUID: hj3vRPtPdx6LGMbClkCYucNNK2Zq2C40 X-Authority-Analysis: v=2.4 cv=Lp2fC3dc c=1 sm=1 tr=0 ts=6944f7d2 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=cgLhVu-Bd7kgOx2TuvUA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_02,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190056 Content-Type: text/plain; charset="utf-8" Decoding is when all the potential pieces for creating a trigger are brought together for a given step. Example - there may be a counter keeping track of some occurrences and a priority-group that is being used to detect a pattern on the sense inputs. These 2 inputs to condition_decode must be programmed, for a given step, to establish the condition for the trigger, or movement to another steps. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 + drivers/hwtracing/qcom/tgu.c | 156 ++++++++++++++++-- drivers/hwtracing/qcom/tgu.h | 27 +++ 3 files changed, 173 insertions(+), 17 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu index d04a01368089..c0e50ee95839 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -14,3 +14,10 @@ KernelVersion 6.19 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the sensed signal with specific step and priority for TGU. + +What: /sys/bus/amba/devices//step[0:7]_condition_decode/reg[0:3] +Date: December 2025 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the decode mode with specific step for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index 447d7e68d132..4140dc544e5e 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -18,8 +18,36 @@ static int calculate_array_location(struct tgu_drvdata *= drvdata, int step_index, int operation_index, int reg_index) { - return operation_index * (drvdata->max_step) * (drvdata->max_reg) + - step_index * (drvdata->max_reg) + reg_index; + int ret =3D -EINVAL; + + switch (operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + ret =3D operation_index * (drvdata->max_step) * + (drvdata->max_reg) + + step_index * (drvdata->max_reg) + reg_index; + break; + case TGU_CONDITION_DECODE: + ret =3D step_index * (drvdata->max_condition_decode) + + reg_index; + break; + default: + break; + } + return ret; +} + +static int check_array_location(struct tgu_drvdata *drvdata, int step, + int ops, int reg) +{ + int result =3D calculate_array_location(drvdata, step, ops, reg); + + if (result =3D=3D -EINVAL) + dev_err(drvdata->dev, "%s - Fail\n", __func__); + + return result; } =20 static ssize_t tgu_dataset_show(struct device *dev, @@ -30,12 +58,26 @@ static ssize_t tgu_dataset_show(struct device *dev, struct tgu_attribute *tgu_attr =3D container_of(attr, struct tgu_attribute, attr); =20 - index =3D calculate_array_location(drvdata, tgu_attr->step_index, - tgu_attr->operation_index, - tgu_attr->reg_num); + index =3D check_array_location(drvdata, tgu_attr->step_index, + tgu_attr->operation_index, tgu_attr->reg_num); + + if (index =3D=3D -EINVAL) + return -EINVAL; =20 - return sysfs_emit(buf, "0x%x\n", - drvdata->value_table->priority[index]); + switch (tgu_attr->operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->priority[index]); + case TGU_CONDITION_DECODE: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->condition_decode[index]); + default: + break; + } + return -EINVAL; } =20 static ssize_t tgu_dataset_store(struct device *dev, @@ -43,6 +85,7 @@ static ssize_t tgu_dataset_store(struct device *dev, const char *buf, size_t size) { int index; + int ret =3D -EINVAL; unsigned long val; =20 struct tgu_drvdata *tgu_drvdata =3D dev_get_drvdata(dev); @@ -50,15 +93,32 @@ static ssize_t tgu_dataset_store(struct device *dev, container_of(attr, struct tgu_attribute, attr); =20 if (kstrtoul(buf, 0, &val)) - return -EINVAL; + return ret; =20 guard(spinlock)(&tgu_drvdata->lock); - index =3D calculate_array_location(tgu_drvdata, tgu_attr->step_index, + index =3D check_array_location(tgu_drvdata, tgu_attr->step_index, tgu_attr->operation_index, tgu_attr->reg_num); =20 - tgu_drvdata->value_table->priority[index] =3D val; - return size; + if (index =3D=3D -EINVAL) + return ret; + + switch (tgu_attr->operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + tgu_drvdata->value_table->priority[index] =3D val; + ret =3D size; + break; + case TGU_CONDITION_DECODE: + tgu_drvdata->value_table->condition_decode[index] =3D val; + ret =3D size; + break; + default: + break; + } + return ret; } =20 static umode_t tgu_node_visible(struct kobject *kobject, @@ -75,13 +135,27 @@ static umode_t tgu_node_visible(struct kobject *kobjec= t, container_of(dev_attr, struct tgu_attribute, attr); =20 if (tgu_attr->step_index < drvdata->max_step) { - ret =3D (tgu_attr->reg_num < drvdata->max_reg) ? - attr->mode : 0; + switch (tgu_attr->operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + ret =3D (tgu_attr->reg_num < drvdata->max_reg) ? + attr->mode : 0; + break; + case TGU_CONDITION_DECODE: + ret =3D (tgu_attr->reg_num < + drvdata->max_condition_decode) ? + attr->mode : 0; + break; + default: + break; + } } return ret; } =20 -static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) +static ssize_t tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) { int i, j, k, index; =20 @@ -89,8 +163,10 @@ static void tgu_write_all_hw_regs(struct tgu_drvdata *d= rvdata) for (i =3D 0; i < drvdata->max_step; i++) { for (j =3D 0; j < MAX_PRIORITY; j++) { for (k =3D 0; k < drvdata->max_reg; k++) { - index =3D calculate_array_location( + index =3D check_array_location( drvdata, i, j, k); + if (index =3D=3D -EINVAL) + goto exit; =20 writel(drvdata->value_table->priority[index], drvdata->base + @@ -98,9 +174,23 @@ static void tgu_write_all_hw_regs(struct tgu_drvdata *d= rvdata) } } } + + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_condition_decode; j++) { + index =3D check_array_location(drvdata, i, + TGU_CONDITION_DECODE, j); + if (index =3D=3D -EINVAL) + goto exit; + + writel(drvdata->value_table->condition_decode[index], + drvdata->base + CONDITION_DECODE_STEP(i, j)); + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); +exit: TGU_LOCK(drvdata->base); + return index >=3D 0 ? 0 : -EINVAL; } =20 static void tgu_set_reg_number(struct tgu_drvdata *drvdata) @@ -129,18 +219,32 @@ static void tgu_set_steps(struct tgu_drvdata *drvdata) drvdata->max_step =3D TGU_DEVID_STEPS(devid); } =20 +static void tgu_set_conditions(struct tgu_drvdata *drvdata) +{ + u32 devid; + + devid =3D readl(drvdata->base + TGU_DEVID); + drvdata->max_condition_decode =3D TGU_DEVID_CONDITIONS(devid); +} + static int tgu_enable(struct device *dev) { + int ret =3D 0; struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); =20 guard(spinlock)(&drvdata->lock); if (drvdata->enable) return -EBUSY; =20 - tgu_write_all_hw_regs(drvdata); + ret =3D tgu_write_all_hw_regs(drvdata); + + if (ret =3D=3D -EINVAL) + goto exit; + drvdata->enable =3D true; =20 - return 0; +exit: + return ret; } =20 static int tgu_disable(struct device *dev) @@ -245,6 +349,14 @@ static const struct attribute_group *tgu_attr_groups[]= =3D { PRIORITY_ATTRIBUTE_GROUP_INIT(7, 1), PRIORITY_ATTRIBUTE_GROUP_INIT(7, 2), PRIORITY_ATTRIBUTE_GROUP_INIT(7, 3), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(0), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(1), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(2), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(3), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(4), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(5), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(6), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(7), NULL, }; =20 @@ -269,6 +381,7 @@ static int tgu_probe(struct amba_device *adev, const st= ruct amba_id *id) =20 tgu_set_reg_number(drvdata); tgu_set_steps(drvdata); + tgu_set_conditions(drvdata); =20 ret =3D sysfs_create_groups(&dev->kobj, tgu_attr_groups); if (ret) { @@ -290,6 +403,15 @@ static int tgu_probe(struct amba_device *adev, const s= truct amba_id *id) if (!drvdata->value_table->priority) return -ENOMEM; =20 + drvdata->value_table->condition_decode =3D devm_kzalloc( + dev, + drvdata->max_condition_decode * drvdata->max_step * + sizeof(*(drvdata->value_table->condition_decode)), + GFP_KERNEL); + + if (!drvdata->value_table->condition_decode) + return -ENOMEM; + drvdata->enable =3D false; =20 pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index 2cf95c239ee7..732126b896e1 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -15,6 +15,7 @@ #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) #define TGU_DEVID_SENSE_INPUT(devid_val) ((int) BMVAL(devid_val, 10, 17)) #define TGU_DEVID_STEPS(devid_val) ((int)BMVAL(devid_val, 3, 6)) +#define TGU_DEVID_CONDITIONS(devid_val) ((int)BMVAL(devid_val, 0, 2)) #define NUMBER_BITS_EACH_SIGNAL 4 #define LENGTH_REGISTER 32 =20 @@ -48,6 +49,7 @@ */ #define STEP_OFFSET 0x1D8 #define PRIORITY_START_OFFSET 0x0074 +#define CONDITION_DECODE_OFFSET 0x0050 #define PRIORITY_OFFSET 0x60 #define REG_OFFSET 0x4 =20 @@ -56,6 +58,9 @@ (PRIORITY_START_OFFSET + PRIORITY_OFFSET * priority +\ REG_OFFSET * reg + STEP_OFFSET * step) =20 +#define CONDITION_DECODE_STEP(step, decode) \ + (CONDITION_DECODE_OFFSET + REG_OFFSET * decode + STEP_OFFSET * step) + #define tgu_dataset_rw(name, step_index, type, reg_num) \ (&((struct tgu_attribute[]){ { \ __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ @@ -68,6 +73,9 @@ tgu_dataset_rw(reg##reg_num, step_index, TGU_PRIORITY##priority, \ reg_num) =20 +#define STEP_DECODE(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_DECODE, reg_num) + #define STEP_PRIORITY_LIST(step_index, priority) \ {STEP_PRIORITY(step_index, 0, priority), \ STEP_PRIORITY(step_index, 1, priority), \ @@ -90,6 +98,14 @@ NULL \ } =20 +#define STEP_DECODE_LIST(n) \ + {STEP_DECODE(n, 0), \ + STEP_DECODE(n, 1), \ + STEP_DECODE(n, 2), \ + STEP_DECODE(n, 3), \ + NULL \ + } + #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ (&(const struct attribute_group){\ .attrs =3D (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ @@ -97,11 +113,19 @@ .name =3D "step" #step "_priority" #priority \ }) =20 +#define CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_DECODE_LIST(step),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_condition_decode" \ + }) + enum operation_index { TGU_PRIORITY0, TGU_PRIORITY1, TGU_PRIORITY2, TGU_PRIORITY3, + TGU_CONDITION_DECODE, }; =20 /* Maximum priority that TGU supports */ @@ -116,6 +140,7 @@ struct tgu_attribute { =20 struct value_table { unsigned int *priority; + unsigned int *condition_decode; }; =20 static inline void TGU_LOCK(void __iomem *addr) @@ -145,6 +170,7 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @value_table: Store given value based on relevant parameters. * @max_reg: Maximum number of registers * @max_step: Maximum step size + * @max_condition_decode: Maximum number of condition_decode * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -159,6 +185,7 @@ struct tgu_drvdata { struct value_table *value_table; int max_reg; int max_step; + int max_condition_decode; }; =20 #endif --=20 2.34.1 From nobody Sun Feb 8 18:56:35 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0A0F2DCBEC for ; Fri, 19 Dec 2025 06:59:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127576; cv=none; b=cDiDFwE2tG20tdAO607j7xrBMBJ5K7WfEDl7Eu4QIOJ391lqxKe0Cii/7wfpkYGFfjcsm63/2D8qSEFihU/KfXaTxC43MmvMRe0koPoeM3QxL7OFXrix57otaFVj8zSwpXi4hAf8jRZ2djszPMCSZALVKhnPauXW9a5D879D6DQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127576; c=relaxed/simple; bh=QbLUAZtQgffCMuDnIpR56pfDNg0DDIM30IBn6Au9SSM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FYr9y7JK6H/5Dnug2wanFwWVNMe1C+unT9LMRUkXZm3qPbYhnn0JBTQVUxhXQxbZzHU/jG3ubHkV6RYaAC1ErxBlSxl3+v4+gBikWeAzGrRXFxdRgCj2t57p/u3/EqnQiPIh5LhMVdTBiZSKMJinkwKBZWaQ/pSWVfuqpBRsyt0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=JssQsznn; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=VFd9Adio; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="JssQsznn"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="VFd9Adio" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJ4c57x3991028 for ; Fri, 19 Dec 2025 06:59:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=Zh3m6t4hqko q12Tk90+CNng+VNifwIyy+mUekxgxB18=; b=JssQsznn4FkbL+nYpIgQ/8Fi25w T9MxsuAcfRojvch97i6L3dFhE3wCXmYVGqckIagMIzisud8kdSFDLW0H8jQGVobI j1/3NT+5amJ9PRNdlMysSiRlGXjOMmnQwRgJdmLov8v98bkHAjuTFt2jSCXPnQEA IC9AZxPZub1JTE/Zy0hSSxAVhTX9mWcy0vw902xu7XvV7VNdqXXBb+iGQdVNMUAU QtKepgUPJuHtv6u76tJdBH+EQmr9+Ko5v0ZPojQ/6+5uLuWmo+HXKOF4O4d74m5y 9OmobmCDFpR9c/IOtIuLea3y5GVtiElOTbHVcp7jueA41CnTG3q19TkGRzg== Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r2d9kdk-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 06:59:32 +0000 (GMT) Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-bdf47c10220so2472518a12.3 for ; Thu, 18 Dec 2025 22:59:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766127572; x=1766732372; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zh3m6t4hqkoq12Tk90+CNng+VNifwIyy+mUekxgxB18=; b=VFd9AdioC3QcgvSmtvV4853fonS9+TcGvio8l3GJXdR3KyzuRcdvFBcmy4oMAk3vnv 1rghAPkceVRtG3MrM08gpXbPf51TeE8Pa+svKMWWPRJ/TYSDep+7SmYT+S9Km1yveP8A iq5pWGZkxgLPVmtqQG2CQ2dItmgPMiWna2EJv8icYdgeCA5HFGvRc6YIMOCoeC0cRIR8 Ep41denExx/MW5LTCDaU/CdNybnqbFoau8TfWnEjSxRXP0v7bmxIHmEJqT7CZyOH7I1e rYa0xY2z/JewJZ7c5F3SJaSC/i6inFpcvydBIm0aeCZPSa6g4gQVjU/hCtnOd/eQAIN6 tMdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766127572; x=1766732372; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Zh3m6t4hqkoq12Tk90+CNng+VNifwIyy+mUekxgxB18=; b=SQkdNUb5JAjUa1Xoa/cehyzU/Gz6Mp8iMoSMYVITi8ODxogCXv1lSiauxaF6DQKEmM 4O2lAVUoqDWku8L5GOzLGwOh+Acr2B5xllJowfZsqsSi2B8EMqpwNzv5jVLKdkzaveJr FSj+CbjzTte2PGokjaWW61XixrW64nezb9vk+DdwvqYMRcRfwFTz8ptlG4RQiK7yDblI PubI+K639vyRXhLxD4mNsflMDIr9KjaHYmX9oOOeH4lROBnJXVt0d2FuyU8JcBXLUdNH T5IkSMs3iJafn2Q89TURf6yM+CIn3iuayYj55DAImrfwgqt9yJ12jwaXAiRWNi19LAk9 WKNQ== X-Forwarded-Encrypted: i=1; AJvYcCWsVq9gm8J5P3JMl2LL5LWN2+cFsA2CFf6N3HXxVs+AXE2rK2bQAxBETitt2cmlIJkDlfbbr/NbqnYCXrE=@vger.kernel.org X-Gm-Message-State: AOJu0YzZpVbeBfcOdvqgR7ql9HpoNP0ZRYCABCnCH4yVg9s+Qp74KPgG tyAQWGaNPeWPGnKvk0bh/NJZDh5hPO7tJRAglzKYvq+REQX9AVldAliaE74L7FJaDCI5ek/p98o eNqfiDFWB3Q/9uFk4za51GXnhi4i0/nSsOe3v29BDNZDFpz/84McxLC47zq182/wDyeQ= X-Gm-Gg: AY/fxX5qfgHwMENN/MvoDRQN1qlClAwLKMhONCsr8UZiDeNnRTtZyG7lnOCdPmI4Ivj yHr3BsUvYUKy7L51PTQLpHBhEBlkIew0tO/3drRUA633WQyIA/CkklrqY7KZi/ETEF86xWAXzph Q2NIlAIiQtmNhzW3UHGtuXA06WnduBbMDiceK2yvAnoSr5XeWYC47Cr52qy/NflGsixzIYe+H7k QT3nxapz1Zxbxw8w97jBss88ofuQJOEGFxrdHoKWCq82Z0yEABslX6rqA9r90ELRQ482AYz0Rnw 8eOGNL4Demx4Uei6RokvwwSDQjy2J8L30jKQyDpigfp/DfpZvheej3+bWBb4buaEUcwYNKFrnbY uCO0sxfp2G887CPVNx3svOefIzt+vKAp8J9hKdGoJVFSw5Qayc3eRMy/z9TDw4mUK X-Received: by 2002:a05:7300:ac90:b0:2b0:310c:529 with SMTP id 5a478bee46e88-2b05ec050d0mr1901108eec.14.1766127571419; Thu, 18 Dec 2025 22:59:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IEk4i3pEXHNK3uc57gFBQrCOQNxRH86YYdtwt9CtiW3CTXTq5Ja4eeOLjPTa8NiffXrLBPoVg== X-Received: by 2002:a05:7300:ac90:b0:2b0:310c:529 with SMTP id 5a478bee46e88-2b05ec050d0mr1901086eec.14.1766127570835; Thu, 18 Dec 2025 22:59:30 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b05fcfc1b7sm3614954eec.0.2025.12.18.22.59.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 22:59:30 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v9 5/7] qcom-tgu: Add support to configure next action Date: Thu, 18 Dec 2025 22:59:00 -0800 Message-Id: <20251219065902.2296896-6-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> References: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=AcG83nXG c=1 sm=1 tr=0 ts=6944f7d4 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=gOWipDUV9lcXNqIIBpoA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA1NiBTYWx0ZWRfX8rNy1LelJvRb qXzTcb2uO0BmHXQ0MWWI0GoeNG83UaLea/Crw5gqCPLvdnk4LlUZPFXlv6yp7M/YFHnXPjN1T8/ apCqftPtMuVQSyOke+HM1V+33giumPcPdsAbIVMaANW0HrFFBWlBZe/DPuOsAVDr8zKvS3kGgfV bSrGlhiOpLN2RJPy0w6OLXNX8V9Jc6uNJXl/OJS4gqZfaf2Fqxd1oUftlElpAW61ABVcvqOQwED gX8TjwcV9IiPYyTI2SSt/5k2o4jtZQ8xcGoNpGNsuIj+4stRRMTs+V20CgQ2KHUWLdK1HpcHBCW HudYnWUSHqZeD+YQN5WuLcGMiJghpi0MTjJVogb9muCFOUMYyXOQnqJ3aOb8oVasKAcl/fDsWj3 YYU7+TfwdQD3GfTSYP2tl1gqFCY9CRqQBDVJBiAZ84/waCgbE+B0kfkBgxboWOKQk0W4XPFVTac RzXoynFE2/REW8z/HjQ== X-Proofpoint-GUID: UWAcDSIewuwsfLUUwCYBk-gwRNveEPuM X-Proofpoint-ORIG-GUID: UWAcDSIewuwsfLUUwCYBk-gwRNveEPuM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_02,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190056 Content-Type: text/plain; charset="utf-8" Add "select" node for each step to determine if another step is taken, trigger(s) are generated, counters/timers incremented/decremented, etc. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 +++ drivers/hwtracing/qcom/tgu.c | 52 +++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 27 ++++++++++ 3 files changed, 86 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu index c0e50ee95839..6fbd86592681 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -21,3 +21,10 @@ KernelVersion 6.19 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the decode mode with specific step for TGU. + +What: /sys/bus/amba/devices//step[0:7]_condition_select/reg[0:3] +Date: December 2025 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the next action with specific step for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index 4140dc544e5e..98648ee61a10 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -33,6 +33,10 @@ static int calculate_array_location(struct tgu_drvdata *= drvdata, ret =3D step_index * (drvdata->max_condition_decode) + reg_index; break; + case TGU_CONDITION_SELECT: + ret =3D step_index * (drvdata->max_condition_select) + + reg_index; + break; default: break; } @@ -74,6 +78,9 @@ static ssize_t tgu_dataset_show(struct device *dev, case TGU_CONDITION_DECODE: return sysfs_emit(buf, "0x%x\n", drvdata->value_table->condition_decode[index]); + case TGU_CONDITION_SELECT: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->condition_select[index]); default: break; } @@ -115,6 +122,10 @@ static ssize_t tgu_dataset_store(struct device *dev, tgu_drvdata->value_table->condition_decode[index] =3D val; ret =3D size; break; + case TGU_CONDITION_SELECT: + tgu_drvdata->value_table->condition_select[index] =3D val; + ret =3D size; + break; default: break; } @@ -148,6 +159,15 @@ static umode_t tgu_node_visible(struct kobject *kobjec= t, drvdata->max_condition_decode) ? attr->mode : 0; break; + case TGU_CONDITION_SELECT: + /* 'default' register is at the end of 'select' region */ + if (tgu_attr->reg_num =3D=3D + drvdata->max_condition_select - 1) + attr->name =3D "default"; + ret =3D (tgu_attr->reg_num < + drvdata->max_condition_select) ? + attr->mode : 0; + break; default: break; } @@ -186,6 +206,19 @@ static ssize_t tgu_write_all_hw_regs(struct tgu_drvdat= a *drvdata) drvdata->base + CONDITION_DECODE_STEP(i, j)); } } + + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_condition_select; j++) { + index =3D check_array_location(drvdata, i, + TGU_CONDITION_SELECT, j); + + if (index =3D=3D -EINVAL) + goto exit; + + writel(drvdata->value_table->condition_select[index], + drvdata->base + CONDITION_SELECT_STEP(i, j)); + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); exit: @@ -225,6 +258,8 @@ static void tgu_set_conditions(struct tgu_drvdata *drvd= ata) =20 devid =3D readl(drvdata->base + TGU_DEVID); drvdata->max_condition_decode =3D TGU_DEVID_CONDITIONS(devid); + /* select region has an additional 'default' register */ + drvdata->max_condition_select =3D TGU_DEVID_CONDITIONS(devid) + 1; } =20 static int tgu_enable(struct device *dev) @@ -357,6 +392,14 @@ static const struct attribute_group *tgu_attr_groups[]= =3D { CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(5), CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(6), CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(7), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(0), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(1), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(2), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(3), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(4), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(5), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(6), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(7), NULL, }; =20 @@ -412,6 +455,15 @@ static int tgu_probe(struct amba_device *adev, const s= truct amba_id *id) if (!drvdata->value_table->condition_decode) return -ENOMEM; =20 + drvdata->value_table->condition_select =3D devm_kzalloc( + dev, + drvdata->max_condition_select * drvdata->max_step * + sizeof(*(drvdata->value_table->condition_select)), + GFP_KERNEL); + + if (!drvdata->value_table->condition_select) + return -ENOMEM; + drvdata->enable =3D false; =20 pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index 732126b896e1..1f46da35b40a 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -50,6 +50,7 @@ #define STEP_OFFSET 0x1D8 #define PRIORITY_START_OFFSET 0x0074 #define CONDITION_DECODE_OFFSET 0x0050 +#define CONDITION_SELECT_OFFSET 0x0060 #define PRIORITY_OFFSET 0x60 #define REG_OFFSET 0x4 =20 @@ -61,6 +62,9 @@ #define CONDITION_DECODE_STEP(step, decode) \ (CONDITION_DECODE_OFFSET + REG_OFFSET * decode + STEP_OFFSET * step) =20 +#define CONDITION_SELECT_STEP(step, select) \ + (CONDITION_SELECT_OFFSET + REG_OFFSET * select + STEP_OFFSET * step) + #define tgu_dataset_rw(name, step_index, type, reg_num) \ (&((struct tgu_attribute[]){ { \ __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ @@ -76,6 +80,9 @@ #define STEP_DECODE(step_index, reg_num) \ tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_DECODE, reg_num) =20 +#define STEP_SELECT(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_SELECT, reg_num) + #define STEP_PRIORITY_LIST(step_index, priority) \ {STEP_PRIORITY(step_index, 0, priority), \ STEP_PRIORITY(step_index, 1, priority), \ @@ -106,6 +113,15 @@ NULL \ } =20 +#define STEP_SELECT_LIST(n) \ + {STEP_SELECT(n, 0), \ + STEP_SELECT(n, 1), \ + STEP_SELECT(n, 2), \ + STEP_SELECT(n, 3), \ + STEP_SELECT(n, 4), \ + NULL \ + } + #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ (&(const struct attribute_group){\ .attrs =3D (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ @@ -120,12 +136,20 @@ .name =3D "step" #step "_condition_decode" \ }) =20 +#define CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_SELECT_LIST(step),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_condition_select" \ + }) + enum operation_index { TGU_PRIORITY0, TGU_PRIORITY1, TGU_PRIORITY2, TGU_PRIORITY3, TGU_CONDITION_DECODE, + TGU_CONDITION_SELECT, }; =20 /* Maximum priority that TGU supports */ @@ -141,6 +165,7 @@ struct tgu_attribute { struct value_table { unsigned int *priority; unsigned int *condition_decode; + unsigned int *condition_select; }; =20 static inline void TGU_LOCK(void __iomem *addr) @@ -171,6 +196,7 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @max_reg: Maximum number of registers * @max_step: Maximum step size * @max_condition_decode: Maximum number of condition_decode + * @max_condition_select: Maximum number of condition_select * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -186,6 +212,7 @@ struct tgu_drvdata { int max_reg; int max_step; int max_condition_decode; + int max_condition_select; }; =20 #endif --=20 2.34.1 From nobody Sun Feb 8 18:56:35 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD08E2D5A01 for ; Fri, 19 Dec 2025 06:59:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127578; cv=none; b=AaD91/hCvS9lly7qwqh85edqGXdqb+MNKMspkz8dQeOWP9JOc7ynsQZu+Y2TgVeoLvO66jPW4FQV28MMNsDtLwWdvkO8YYunLH/NcmasoZFUcmJ2Nh9yA7SgiYUMwGWm2SPTQZ0jUJ5iAM+kBa0LSzW6hn85TzjylMgT1kJ9JWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127578; c=relaxed/simple; bh=xu/dFtqRmQxWY53gD3+YuovArbLVXXsUAoIvtPXwNqs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=r6dL1hb0WI7X7i1Xsed5L6jKlqDfLLbZeZnCIGMJ1esK1O7dexjbaOOFFs2YQUyIyC75EK8vEWPjp6nYjGetiGzCCtgwZSPMJK6quszxOdEFtms0LNszOARp+7G7kvyNlfrWLyMmGx8SbCx59kTDEF8/5AlfCEpwDSjrS1IyJV4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=dTt+Cr69; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=LTTFgg4D; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="dTt+Cr69"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="LTTFgg4D" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJ4cBUn4145506 for ; Fri, 19 Dec 2025 06:59:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=LNb3PE7PkFb b1OKX7X/dVO7SyYEmsv5UgQIPUG7b+c4=; b=dTt+Cr69q+2OjmahuZQHwxjRpPi T4YWUtr0M74vgKWruP6x2deL0IIRYm2pe2h/cDOJHksCnzYLSlIoiTexxaYj4KZo h0ik3rEtuMufJR1+w85nc0qoAz4fv3dS3iKXtwtkxePJjw0HPFrmYv7ROL8QWsql dKc2IU0TsClBGsseQNCbn1smID+6vpdeKVyb+Jj+44O2XrBOm1v8FkFK6JrIqpK+ 4V+eT/GD07YCk4ZF1yHzDAsHQQpw00Kxk3t0UK7cKZ4qeW83zgSPwGYAgDzuChH2 L2feyeDHEZgepSqt7GnUX3PVs+GvMtbMMf0M0cQAkkQ7cjfwQ02l4vADALQ== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r2dsmqm-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 06:59:34 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-bdf47c10220so2472572a12.3 for ; Thu, 18 Dec 2025 22:59:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766127573; x=1766732373; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LNb3PE7PkFbb1OKX7X/dVO7SyYEmsv5UgQIPUG7b+c4=; b=LTTFgg4DOiDSP+gUyzZ6NUfe+rwZNpAJaKyWp4S0E+Y3aplOJWBHlzLUDYiFOJhGI/ toPd5BNxDHBP4Izu8uLvfQhfwf2ria6VxxX7NpQHow4SxQjkkjaD7YlgaCq1M4BOQx7R dlZvwTsmL+oranb0wxlyNQXbExpoX+cmc/WpcF9iqYuYCdvIh+ZlgKmWEJlUurdJUry2 X2hOHYogEmFhR4MZ5kqF/KqHnMVsD0/PKQk4R7xFTi4AKTycO9XjB2Hqm/LB9QZI/ByP wqU+QRGewzVwhXROKwWqldl7UefwmnRImjtWx01TzuHuvUQ8n6WqauzHryerW8AMvcpc KCWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766127573; x=1766732373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=LNb3PE7PkFbb1OKX7X/dVO7SyYEmsv5UgQIPUG7b+c4=; b=rKvR9/uPLMy6TP9Y5DHKl4NwpQ0oox7h1zjgS227EZ+Myd3S821qPfbjGtBvi0trRj CmXw/BvT1L7sDB6p116nJfvEWaUaXZhbJXhDYFfzINnDKxfRcE8MJbMCbOTMZLfKeHGO kHU2gq6mOSdTbAGY8tmXsCUzEYBWDpfdRcQMMB31vpl9KdzWmwe0e/QcxgDid8y8dO3V Cw5frtDGpD6U2PTW6Ekr8OgwYGfxKZ1XZTo2at3Qd+9bZXtIJTOyAQmkDGMYpGWipjji D9ZhrxIrqvbS+aovl3nqh1bcNL16dWJyZqA8an2gQPuWV9LEAzYkMvteUbNvi0LzHjiO VvDg== X-Forwarded-Encrypted: i=1; AJvYcCUDtAJjwYpAqpruDOIbjgeTwCOkmnctCJZcHQhOvMjaq7RAco6HIB1nEMPPJdAiOwHkQORkYYJmY9IJe3g=@vger.kernel.org X-Gm-Message-State: AOJu0YxQbXj9wE6jFFWDpmc9LcFmsAuC9yVpKUyA8gLbNiFe4btbxnwX X8T9X/3FOwX6H19y0wpXx/ffLU/BGNjzT4p3J36yJX0nuCOKSCdMeg/vin+vgyGtZHoB0o2uFqL gFJLrB7+unJa4ks45+eSbcxtrQihs2zmg2mWAx5mrjGPUVN96QbugnDBpRY/ZonxGcj4= X-Gm-Gg: AY/fxX5HWul4SxuXmIktNWm+RgELnPI0Q0qshvikmdUhhn27wrTar7wC1fDO87QyQ0Y Gdi4BbNfqS6e41RMOb+rgsrBwNx1tv4dZPCUJqjNLobo8Cig4NwFrWXolL3dyTp6mxQ3saUOSDx eonAy2lLjfvGfmSsxe9jgnvIUtOYYsH3+OUhVKHkNK/blQpn1uIvHQK7XX0xJ11zAPjZVLEtw3V sc/eG5f6TpqhkVrh589YdqCuUh6gg9RhCTg8st8D1ttAx8n45yjI7bU9Gk3TSbQ2o6EZNDoTV4S FYhjUZRuLdHDuuCYySQzLnu/DptKFPp9+miRo1cv5aeXEgXZv9x39I+opHG9l7khl7AgfEdkbok Z1lByzSRYj3B50sY0yuXFxKyUuivkNXzvzLMnSCJphD2wt4zUYOF6b2DcSZKQCG0w X-Received: by 2002:a05:7301:18ab:b0:2ae:2c27:fc0e with SMTP id 5a478bee46e88-2b05ec7454dmr2104000eec.22.1766127573219; Thu, 18 Dec 2025 22:59:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IHu2mdPZB4X+UtG0W0ArtTRl+v42P20I8dyzAkElasiwIyRyirg+VeMxOThfyPRGEuydEsafw== X-Received: by 2002:a05:7301:18ab:b0:2ae:2c27:fc0e with SMTP id 5a478bee46e88-2b05ec7454dmr2103973eec.22.1766127572618; Thu, 18 Dec 2025 22:59:32 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b05fcfc1b7sm3614954eec.0.2025.12.18.22.59.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 22:59:32 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v9 6/7] qcom-tgu: Add timer/counter functionality for TGU Date: Thu, 18 Dec 2025 22:59:01 -0800 Message-Id: <20251219065902.2296896-7-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> References: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: Uzj7iLaZhSG6xkzQfM98UttXQ_Vk8Ff8 X-Authority-Analysis: v=2.4 cv=A7ph/qWG c=1 sm=1 tr=0 ts=6944f7d6 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=eGDQztGCVwpQsGOtWZEA:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: Uzj7iLaZhSG6xkzQfM98UttXQ_Vk8Ff8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA1NiBTYWx0ZWRfX20kbaAnYESsu q+YxuFGL21kzJ3AF63h+r5FpDTuuvD8+akb3/PG1VzrC/dLmHT5ETQBNxCbY/CoWxxUEEVM0PRJ nP9Ow1DrnEkSM116hqfK15RNINrQNolh0xLO+1jqomzecpgbYpzuXXcDQIP7uHBrAD1udiEayyj zRDe0V5ooDdPFVarmPXz+aYz9Ukd9tyKYqLMPPsGLFVj+JOfJpK48OuP1vw3idxxzWoz11tqn4s HSjPi5zEMEjmwB0HaD0/8Scsq9VZbrnccu87dGIOHLhz5o8/rMcsgvb28eSX7VFDj/Zoi/X6jLJ qWVNog7m7mK0VhOdBdf6gOqvpxzU0GpoNMBeNuyuy9FvQKhvAPgvbvZV5IVXR/x8LQMvIRhfqeO VbwXoGhH023owQkReAWtcpMbM+z2xg+DB+CHJpoHcj4TV6pfp9v2oGo7JyLEjfOlJdkjiWklDpl 31erzVif2gExk9J/pkQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_02,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 malwarescore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190056 Content-Type: text/plain; charset="utf-8" Add counter and timer node for each step which could be programed if they are to be utilized in trigger event/sequence. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 14 ++ drivers/hwtracing/qcom/tgu.c | 120 ++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 54 ++++++++ 3 files changed, 188 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu index 6fbd86592681..010eade0a1c5 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -28,3 +28,17 @@ KernelVersion 6.19 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the next action with specific step for TGU. + +What: /sys/bus/amba/devices//step[0:7]_timer/reg[0:1] +Date: December 2025 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the timer value with specific step for TGU. + +What: /sys/bus/amba/devices//step[0:7]_counter/reg[0:1] +Date: December 2025 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the counter value with specific step for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index 98648ee61a10..d4210869556e 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -37,6 +37,12 @@ static int calculate_array_location(struct tgu_drvdata *= drvdata, ret =3D step_index * (drvdata->max_condition_select) + reg_index; break; + case TGU_COUNTER: + ret =3D step_index * (drvdata->max_counter) + reg_index; + break; + case TGU_TIMER: + ret =3D step_index * (drvdata->max_timer) + reg_index; + break; default: break; } @@ -81,6 +87,12 @@ static ssize_t tgu_dataset_show(struct device *dev, case TGU_CONDITION_SELECT: return sysfs_emit(buf, "0x%x\n", drvdata->value_table->condition_select[index]); + case TGU_TIMER: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->timer[index]); + case TGU_COUNTER: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->counter[index]); default: break; } @@ -126,6 +138,14 @@ static ssize_t tgu_dataset_store(struct device *dev, tgu_drvdata->value_table->condition_select[index] =3D val; ret =3D size; break; + case TGU_TIMER: + tgu_drvdata->value_table->timer[index] =3D val; + ret =3D size; + break; + case TGU_COUNTER: + tgu_drvdata->value_table->counter[index] =3D val; + ret =3D size; + break; default: break; } @@ -168,6 +188,22 @@ static umode_t tgu_node_visible(struct kobject *kobjec= t, drvdata->max_condition_select) ? attr->mode : 0; break; + case TGU_COUNTER: + if (drvdata->max_counter =3D=3D 0) + ret =3D SYSFS_GROUP_INVISIBLE; + else + ret =3D (tgu_attr->reg_num < + drvdata->max_counter) ? + attr->mode : 0; + break; + case TGU_TIMER: + if (drvdata->max_timer =3D=3D 0) + ret =3D SYSFS_GROUP_INVISIBLE; + else + ret =3D (tgu_attr->reg_num < + drvdata->max_timer) ? + attr->mode : 0; + break; default: break; } @@ -219,6 +255,30 @@ static ssize_t tgu_write_all_hw_regs(struct tgu_drvdat= a *drvdata) drvdata->base + CONDITION_SELECT_STEP(i, j)); } } + + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_timer; j++) { + index =3D check_array_location(drvdata, i, TGU_TIMER, j); + + if (index =3D=3D -EINVAL) + goto exit; + + writel(drvdata->value_table->timer[index], + drvdata->base + TIMER_COMPARE_STEP(i, j)); + } + } + + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_counter; j++) { + index =3D check_array_location(drvdata, i, TGU_COUNTER, j); + + if (index =3D=3D -EINVAL) + goto exit; + + writel(drvdata->value_table->counter[index], + drvdata->base + COUNTER_COMPARE_STEP(i, j)); + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); exit: @@ -262,6 +322,31 @@ static void tgu_set_conditions(struct tgu_drvdata *drv= data) drvdata->max_condition_select =3D TGU_DEVID_CONDITIONS(devid) + 1; } =20 +static void tgu_set_timer_counter(struct tgu_drvdata *drvdata) +{ + int num_timers, num_counters; + u32 devid2; + + devid2 =3D readl(drvdata->base + CORESIGHT_DEVID2); + + if (TGU_DEVID2_TIMER0(devid2) && TGU_DEVID2_TIMER1(devid2)) + num_timers =3D 2; + else if (TGU_DEVID2_TIMER0(devid2) || TGU_DEVID2_TIMER1(devid2)) + num_timers =3D 1; + else + num_timers =3D 0; + + if (TGU_DEVID2_COUNTER0(devid2) && TGU_DEVID2_COUNTER1(devid2)) + num_counters =3D 2; + else if (TGU_DEVID2_COUNTER0(devid2) || TGU_DEVID2_COUNTER1(devid2)) + num_counters =3D 1; + else + num_counters =3D 0; + + drvdata->max_timer =3D num_timers; + drvdata->max_counter =3D num_counters; +} + static int tgu_enable(struct device *dev) { int ret =3D 0; @@ -400,6 +485,22 @@ static const struct attribute_group *tgu_attr_groups[]= =3D { CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(5), CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(6), CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(7), + TIMER_ATTRIBUTE_GROUP_INIT(0), + TIMER_ATTRIBUTE_GROUP_INIT(1), + TIMER_ATTRIBUTE_GROUP_INIT(2), + TIMER_ATTRIBUTE_GROUP_INIT(3), + TIMER_ATTRIBUTE_GROUP_INIT(4), + TIMER_ATTRIBUTE_GROUP_INIT(5), + TIMER_ATTRIBUTE_GROUP_INIT(6), + TIMER_ATTRIBUTE_GROUP_INIT(7), + COUNTER_ATTRIBUTE_GROUP_INIT(0), + COUNTER_ATTRIBUTE_GROUP_INIT(1), + COUNTER_ATTRIBUTE_GROUP_INIT(2), + COUNTER_ATTRIBUTE_GROUP_INIT(3), + COUNTER_ATTRIBUTE_GROUP_INIT(4), + COUNTER_ATTRIBUTE_GROUP_INIT(5), + COUNTER_ATTRIBUTE_GROUP_INIT(6), + COUNTER_ATTRIBUTE_GROUP_INIT(7), NULL, }; =20 @@ -425,6 +526,7 @@ static int tgu_probe(struct amba_device *adev, const st= ruct amba_id *id) tgu_set_reg_number(drvdata); tgu_set_steps(drvdata); tgu_set_conditions(drvdata); + tgu_set_timer_counter(drvdata); =20 ret =3D sysfs_create_groups(&dev->kobj, tgu_attr_groups); if (ret) { @@ -464,6 +566,24 @@ static int tgu_probe(struct amba_device *adev, const s= truct amba_id *id) if (!drvdata->value_table->condition_select) return -ENOMEM; =20 + drvdata->value_table->timer =3D devm_kzalloc( + dev, + drvdata->max_step * drvdata->max_timer * + sizeof(*(drvdata->value_table->timer)), + GFP_KERNEL); + + if (!drvdata->value_table->timer) + return -ENOMEM; + + drvdata->value_table->counter =3D devm_kzalloc( + dev, + drvdata->max_step * drvdata->max_counter * + sizeof(*(drvdata->value_table->counter)), + GFP_KERNEL); + + if (!drvdata->value_table->counter) + return -ENOMEM; + drvdata->enable =3D false; =20 pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index 1f46da35b40a..46a4cffedd7b 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -11,11 +11,17 @@ #define TGU_LAR 0xfb0 #define TGU_UNLOCK_OFFSET 0xc5acce55 #define TGU_DEVID 0xfc8 +#define CORESIGHT_DEVID2 0xfc0 =20 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) #define TGU_DEVID_SENSE_INPUT(devid_val) ((int) BMVAL(devid_val, 10, 17)) #define TGU_DEVID_STEPS(devid_val) ((int)BMVAL(devid_val, 3, 6)) #define TGU_DEVID_CONDITIONS(devid_val) ((int)BMVAL(devid_val, 0, 2)) +#define TGU_DEVID2_TIMER0(devid_val) ((int)BMVAL(devid_val, 18, 23)) +#define TGU_DEVID2_TIMER1(devid_val) ((int)BMVAL(devid_val, 13, 17)) +#define TGU_DEVID2_COUNTER0(devid_val) ((int)BMVAL(devid_val, 6, 11)) +#define TGU_DEVID2_COUNTER1(devid_val) ((int)BMVAL(devid_val, 0, 5)) + #define NUMBER_BITS_EACH_SIGNAL 4 #define LENGTH_REGISTER 32 =20 @@ -51,6 +57,8 @@ #define PRIORITY_START_OFFSET 0x0074 #define CONDITION_DECODE_OFFSET 0x0050 #define CONDITION_SELECT_OFFSET 0x0060 +#define TIMER_START_OFFSET 0x0040 +#define COUNTER_START_OFFSET 0x0048 #define PRIORITY_OFFSET 0x60 #define REG_OFFSET 0x4 =20 @@ -62,6 +70,12 @@ #define CONDITION_DECODE_STEP(step, decode) \ (CONDITION_DECODE_OFFSET + REG_OFFSET * decode + STEP_OFFSET * step) =20 +#define TIMER_COMPARE_STEP(step, timer) \ + (TIMER_START_OFFSET + REG_OFFSET * timer + STEP_OFFSET * step) + +#define COUNTER_COMPARE_STEP(step, counter) \ + (COUNTER_START_OFFSET + REG_OFFSET * counter + STEP_OFFSET * step) + #define CONDITION_SELECT_STEP(step, select) \ (CONDITION_SELECT_OFFSET + REG_OFFSET * select + STEP_OFFSET * step) =20 @@ -83,6 +97,12 @@ #define STEP_SELECT(step_index, reg_num) \ tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_SELECT, reg_num) =20 +#define STEP_TIMER(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_TIMER, reg_num) + +#define STEP_COUNTER(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_COUNTER, reg_num) + #define STEP_PRIORITY_LIST(step_index, priority) \ {STEP_PRIORITY(step_index, 0, priority), \ STEP_PRIORITY(step_index, 1, priority), \ @@ -122,6 +142,18 @@ NULL \ } =20 +#define STEP_TIMER_LIST(n) \ + {STEP_TIMER(n, 0), \ + STEP_TIMER(n, 1), \ + NULL \ + } + +#define STEP_COUNTER_LIST(n) \ + {STEP_COUNTER(n, 0), \ + STEP_COUNTER(n, 1), \ + NULL \ + } + #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ (&(const struct attribute_group){\ .attrs =3D (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ @@ -143,6 +175,20 @@ .name =3D "step" #step "_condition_select" \ }) =20 +#define TIMER_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_TIMER_LIST(step),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_timer" \ + }) + +#define COUNTER_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_COUNTER_LIST(step),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_counter" \ + }) + enum operation_index { TGU_PRIORITY0, TGU_PRIORITY1, @@ -150,6 +196,8 @@ enum operation_index { TGU_PRIORITY3, TGU_CONDITION_DECODE, TGU_CONDITION_SELECT, + TGU_TIMER, + TGU_COUNTER }; =20 /* Maximum priority that TGU supports */ @@ -166,6 +214,8 @@ struct value_table { unsigned int *priority; unsigned int *condition_decode; unsigned int *condition_select; + unsigned int *timer; + unsigned int *counter; }; =20 static inline void TGU_LOCK(void __iomem *addr) @@ -197,6 +247,8 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @max_step: Maximum step size * @max_condition_decode: Maximum number of condition_decode * @max_condition_select: Maximum number of condition_select + * @max_timer: Maximum number of timers + * @max_counter: Maximum number of counters * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -213,6 +265,8 @@ struct tgu_drvdata { int max_step; int max_condition_decode; int max_condition_select; + int max_timer; + int max_counter; }; =20 #endif --=20 2.34.1 From nobody Sun Feb 8 18:56:35 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 627F22DD60E for ; Fri, 19 Dec 2025 06:59:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127579; cv=none; b=P3I2eUJ+CSIv2/5nqOjf+hTRNYpbHny2FLoztEaelphrWbYwLxbO9KM2IHkTwYU4ttOS0Ipzw6ABBQ26zEVwQO5lwrIlCbq7+MojK7KOleonViAIo0287wDhtVls/yDQ8FfgsDOorGmgaEMyhxFa+s5WRLtTizQhmU5H35kK+8M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766127579; c=relaxed/simple; bh=qcSPqyQePvUXF45qTdxuZaj+bUdH+6NMxljSGrnB4cE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JylBJ5yuSXG8duy46346DFwJcp3u9bPE2ybcCQmsHgnp4k3TU/HVx8lwL1iWgnVXhiMAVXC24BHolfAOZBon7LnMkwcG2RiM8O5kxPdEa/aAo5H7f/PXNgAqh8/EDzQpRDuUdat6lFSVP0/weAkzc58eyiHZcB+scW+FQv0WtCY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=CZbqotfi; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=SIv7trGL; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="CZbqotfi"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="SIv7trGL" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJ4cNm4091968 for ; Fri, 19 Dec 2025 06:59:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=AAHoK3E/1oe cqQ3t5XeeP2NOaVanUmmIQWh+9SYZv/s=; b=CZbqotfisGUedtKVnyjdzWM26kG TJRqYgeuqqIOJ3lmji0er+nstl0+5ZjrI4kMKolBL/aO+GTpysK4Q0fNvpeqvQxo vMxdZoRZrcwxyvnpuI1NtkbaOcOVafdvbDf0Z7Yn+TYFeWNdWLozCtIzUtrzUolQ Zd7/udCixYrbpXQNoE70Jh2gDORAbqImgXuRmPGvhCK5bYiOgBgaHErzpHW4kEk9 g6yNoyTpSViieoEHJejzSWOPvczlQqXMtchdebYFRaNNT0swxiNFooQ/lpyUEyG4 r4Sjz0gA4xOMMily+WV/5O6nXkDRg4EcFxR45lOSgLhq+JXFfjJjns1UGcw== Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r2e9m6u-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 06:59:36 +0000 (GMT) Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-bddf9ce4935so1417105a12.1 for ; Thu, 18 Dec 2025 22:59:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766127575; x=1766732375; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AAHoK3E/1oecqQ3t5XeeP2NOaVanUmmIQWh+9SYZv/s=; b=SIv7trGLixkeHmF+CT52agWbDKz53udNoqwKS5JXzZYsWrZc6OoEvN06jZHaD2iRt6 FzgaePSGudQmgVV57IJYP7caFyDAvLh0k5SQQA+/LZEtMqg2JTbRlrbYXaNKjz93JRu1 FV3nnWmNgF4TdvKK1PdfTUF5gxBWUqV386yzdK/HtKG0hm1Pm02f9cytRmsoHHa5U1Sp arT18Gmt89Vu13F/LDUjLl7zpph58yniEcBBAFc1o6XPCjfzEaqLeqchtCAF+2I7EMmE T9NGRoTNVcBKcuX8XBVDeDJtWIq5VugDSiX4x6hzzK3MlBFsWY9BP480pRVC+fsKVaTt zW+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766127575; x=1766732375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=AAHoK3E/1oecqQ3t5XeeP2NOaVanUmmIQWh+9SYZv/s=; b=JMM6AjjuKC2vWbn1wh2DIh+/U2V2IbF6ukmZCtzBPzvcFm9JnTKOoV1eHo6fxJ2jkX ed+Ilr4GBD0rWxtrHVZ9RbziiK5ZuY5H+FCCCvnulOYTfWJQ38cYAm9xVB0OHkqfGHXe sv0Pdfu+Lb8/RHNNFYOn7pjq6qe/vu3gsHagUF376YPgpmk3qjbYm51PKZbUicOAaDPQ ql6ogVqB1SKgUuml/YTtiCgLeQ4YRJEWhhR7INxtzLS/EM3NRl9W5+Zj//sJAidTCcsf GjzWa/cT08k1oOaVGsvmnkfBYlDjnGzTqRxd4/9wSxL4s16pa5USj7HgV1bnl6EBJv3f Xjpg== X-Forwarded-Encrypted: i=1; AJvYcCV4eiYQKQ8Br28u1QuhafrTAW79mkz2QXRwhtIxfzissqjAQV1a2xc/mZZcQo3c1jqZnEP2mzkx6VJB/zo=@vger.kernel.org X-Gm-Message-State: AOJu0YwVN75j3BkFefgYzjyzKCBKud6n0sm5KlI24VCFGOrq0tQ0vaS3 iW4L+iWouQI5/wcueD0TrMgKiWqr8fB+R63JfuHa/ywA15jpkFQOSPGNkuGoBM7oQnd+sPlzI+0 ZBLTZ2sMtTo9yHr/M2EWPl9ORTdUI+vP4uep8vDH/4TLTC7kNitunfvPqoGbZOUYWAhU= X-Gm-Gg: AY/fxX45IoMxSx/CHCNfclAXyPVHCNWddcuMBqRRzuRIav+ldcxuev3OJ4RgFh8h+fZ k46L81boHCsN96AjAQK4uJltiErCViQvXMQxxVuo/JX8PTAWWfG1xhjDcJZgfoZ/Wh9Ww3PKdUw rCvIoyGoq1qHIzDdLnNyDHZ/ls/boA3B4PhZYRG1ddD9VvzRaergllODFXtpj0qL6PoIffbwcsm sJ17LAe5Nxf+kFdBz6s5FrKqW/opnfFMo1YKaperxFkGfsH6j7fZAt51IjSbbFTB8X0FO4H1fkY MWjzqSndw2zNUs3D/f5+yLgjx9HYb04McRwW8p5JzyHRHRp0ii5nCQT1YQNLBg9nrNBXCJINglq 2+QPflYVeExkOP/oG3piEFuC86DlXADbGT5gJRrJ8coiAOoF2CZ+gMQ/oqc6nnkPD X-Received: by 2002:a05:7300:7994:b0:2b0:59da:f794 with SMTP id 5a478bee46e88-2b05ec745ddmr1683896eec.24.1766127575250; Thu, 18 Dec 2025 22:59:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IGHFZQ55XLG0hhz+Du5So6Zh30gXpnThAA+Zru3wBF9ghRk08A705BlyynLTBuO1EMWAHVI2A== X-Received: by 2002:a05:7300:7994:b0:2b0:59da:f794 with SMTP id 5a478bee46e88-2b05ec745ddmr1683876eec.24.1766127574671; Thu, 18 Dec 2025 22:59:34 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b05fcfc1b7sm3614954eec.0.2025.12.18.22.59.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 22:59:34 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v9 7/7] qcom-tgu: Add reset node to initialize Date: Thu, 18 Dec 2025 22:59:02 -0800 Message-Id: <20251219065902.2296896-8-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> References: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA1NiBTYWx0ZWRfX259ClFRKKVIK S34iDR0V5enOmBHDhH9kcWnlfW9KMnojO8MkaAcZkDKoIROPSaWmcmJ0Ptibvwn6oV90sVRZoWV i2nu9GtOolwkyuSSzOU43RGlDp/gIz4NxL7Xdy0r+YYa0dZxbVYuSEqlNo6OLTGZ0bp0+XKiVkL OtXuqRlGNU0N+OQDNX+pNRUhQfGestIq4cZiqHFlgyVisW+2N0DnfY/3ps8C6IKAgxA9JzJdnp/ qduGipD7Cpzs4pmewoXsZxkTKiyKvEMA3RQTAkBFygnN3cLv3yIgxASAwPkKBgTe1UcULhqv1hO P5vznF0wI4e/JoSUcHGyj1Z115swjdk7xZXa9Noz+qjwx2jnXjxRaWdVKYUmnYy/atN20jw2jl6 WsHBe8O2XuuRWKPAHIqK3NJC71+c24bA1llzhJrBv6ebABPuxFcWsElvKomZOwO5+fxD8iP3W48 1/AG0FNg/kw1kpS2ssw== X-Authority-Analysis: v=2.4 cv=W+c1lBWk c=1 sm=1 tr=0 ts=6944f7d8 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=IgPCHI2mAnvcCQI4J_AA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: OUIOEL9JpzX3YIuMedNbhaeF4uVvxvgR X-Proofpoint-GUID: OUIOEL9JpzX3YIuMedNbhaeF4uVvxvgR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_02,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 bulkscore=0 impostorscore=0 spamscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190056 Content-Type: text/plain; charset="utf-8" Add reset node to initialize the value of priority/condition_decode/condition_select/timer/counter nodes. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 ++ drivers/hwtracing/qcom/tgu.c | 74 +++++++++++++++++++ 2 files changed, 81 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu index 010eade0a1c5..0733b3e07b45 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -42,3 +42,10 @@ KernelVersion 6.19 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the counter value with specific step for TGU. + +What: /sys/bus/amba/devices//reset_tgu +Date: December 2025 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (Write) Write 1 to reset the dataset for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index d4210869556e..5a8c6af9b719 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -425,8 +425,82 @@ static ssize_t enable_tgu_store(struct device *dev, } static DEVICE_ATTR_RW(enable_tgu); =20 +/* reset_tgu_store - Reset Trace and Gating Unit (TGU) configuration. */ +static ssize_t reset_tgu_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t size) +{ + unsigned long value; + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + int i, j, ret; + + if (kstrtoul(buf, 0, &value) || value =3D=3D 0) + return -EINVAL; + + if (!drvdata->enable) { + ret =3D pm_runtime_get_sync(drvdata->dev); + if (ret < 0) { + pm_runtime_put(drvdata->dev); + return ret; + } + } + + guard(spinlock)(&drvdata->lock); + TGU_UNLOCK(drvdata->base); + + writel(0, drvdata->base + TGU_CONTROL); + + if (drvdata->value_table->priority) + memset(drvdata->value_table->priority, 0, + MAX_PRIORITY * drvdata->max_step * + drvdata->max_reg * sizeof(unsigned int)); + + if (drvdata->value_table->condition_decode) + memset(drvdata->value_table->condition_decode, 0, + drvdata->max_condition_decode * drvdata->max_step * + sizeof(unsigned int)); + + /* Initialize all condition registers to NOT(value=3D0x1000000) */ + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_condition_decode; j++) { + drvdata->value_table + ->condition_decode[calculate_array_location( + drvdata, i, TGU_CONDITION_DECODE, j)] =3D + 0x1000000; + } + } + + if (drvdata->value_table->condition_select) + memset(drvdata->value_table->condition_select, 0, + drvdata->max_condition_select * drvdata->max_step * + sizeof(unsigned int)); + + if (drvdata->value_table->timer) + memset(drvdata->value_table->timer, 0, + (drvdata->max_step) * + (drvdata->max_timer) * + sizeof(unsigned int)); + + if (drvdata->value_table->counter) + memset(drvdata->value_table->counter, 0, + (drvdata->max_step) * + (drvdata->max_counter) * + sizeof(unsigned int)); + + dev_dbg(dev, "Coresight-TGU reset complete\n"); + + TGU_LOCK(drvdata->base); + + drvdata->enable =3D false; + pm_runtime_put(drvdata->dev); + + return size; +} +static DEVICE_ATTR_WO(reset_tgu); + static struct attribute *tgu_common_attrs[] =3D { &dev_attr_enable_tgu.attr, + &dev_attr_reset_tgu.attr, NULL, }; =20 --=20 2.34.1