From nobody Mon Feb 9 13:58:39 2026 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFEEC2C0287 for ; Fri, 19 Dec 2025 05:37:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766122651; cv=none; b=FQvmxjK/7lg5Mu6bPqIcjVi9rqRSsjrBI4cIZ+ZNfuG5OTfduYstE5mbeyVIAzzm6sDSeONOiq8/hWCnHNHDB8VVVeVc1/TwjrMDguHbeQAhS0Um9nbn7MJUR556o0Lrbe3f5eKA4CGPMbY4Av6VeX9jLMdnFCsa1G3ACYZ8VpM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766122651; c=relaxed/simple; bh=hlJGkag1/m+BajHKxwSoDZk8vWfVJUTYJ+ASwnoAf04=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rLJtFipGoCzuJHGgStIgWIErxHXGPMi0T247vlUVklFY6+MmMLmo/hlVBE2COsOj2OEIoc1saN81J1DgJL8qh7FinidUguI30c5fdivwRbef0igWy4JkX3PrZZvGvdVdP6YS1BLUC56/FVszklAzyYDgegLWppDpWQNrDrA+IZA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=SUqR0xLz; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SUqR0xLz" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-29f0f875bc5so19075865ad.3 for ; Thu, 18 Dec 2025 21:37:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1766122649; x=1766727449; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+BUB05Xw0z/21o0FdpEbUVLloFvEcORujjQKbT7R+Vg=; b=SUqR0xLzLSBiFcvJMSTZDzNK7u+XCnGICkXG3KQCF41vAt4HFklJmcSlKoTM1G6xW+ nr8YTfWMTDPFBVVmfKJI+FjDxrN3FvYBfvXch2FXwIZF5FIoROUSqIEN2LKJjEEm6yPx Jpr0B3lsgnZNXsmaUOg9eSBLpgilxHONkBxyXePTfyG6Dwn8PTxNMO+laXlxMboSvWEP s5WmwUpLHbn6JTYJ3c4qAWsn6PD1nDQg/arqV5f51tbDtUejuJjsob7WnRRN0BKQJceh azfBbJE+7HK2V7SJpOMGVy8ErzHBWOHsGe5XkMRDnmcsbiHVGjvrz28UCGBER1spbTOB efJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766122649; x=1766727449; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=+BUB05Xw0z/21o0FdpEbUVLloFvEcORujjQKbT7R+Vg=; b=OXQqChWNGqk9dU7bIXxs2cX+fpbonwS/ZYN0fiIzG1bIk6p8qtftvRNn49LvYxA2QQ U3ge5QOwLqTc8ZoLkIiCZ0fLYj2AjKlBDl6dfOjWeCRGng43lsJHKeRJrfWYvYjR5Vzh 0+p2+wb2wZqTRhnSfrO6GnZHGZ9JSxjPtlgP7MS1sxaalSuLzyPN7A36E+72hiHAj2UN Ed8jXRB1TqejH3Q0Huc+eUd6gDdl7rlyRK5RySgPhc3wWhfeinMIxjkXhFVxCdWenhoS Zcea6d3ZydgtjdCgV3SUmZ2N/0tpbKJwik4QUczDsMPQvVfCTXTXMZZ/OyPxlP7UqIcB 798w== X-Forwarded-Encrypted: i=1; AJvYcCU/v1aZU4tEtQIiUeYQm7DolOl3njvw0kEEaBkCUZqEpDgiaz3FL2n5swjX4MSPV5OvrHIczv46kLXof/8=@vger.kernel.org X-Gm-Message-State: AOJu0YyPQR/lXqrO8oxUBGVLvkVUk3YsX8jokL4c6OgfXzH+y6fVAOKw FW+GiTMe77nyPSp0WwniURdlqf74M3XlcTmY95puoqBkeig1oqQxXB2H X-Gm-Gg: AY/fxX4x0hjR0GEoGdRVwTE+lAfcJ7SRnkDrk13Ach6+5TpdHCD+KrAMPlkpJCB7Cdt Y29GeSN32tTywO8iXN04f2vyEAwvNz02DfPqKNFjEEN3tHgAnhq5Zks2XVgwX+R1ljjOS4vUosy 8fQ6QAqyXGqnNxIuXFNHxashBUL5vZPxLOxnt47wKmSDWMnf+O3kzzdHb0kjAKf23DpGM+BjD+x XE1pQyI2L04PfljJYh/lhuA7A3aSIzBOg1qk50yu827iPv2s/n1xqnfzzmPF49iSzxpuzACXa92 qtSb44rWDBWA3/AA4K9DPclB7uI44TElJ0dZpyvxoK/kh2vrUgK5rAMhWGXQMGNeJ/J7104CM68 MGBDzgBVGK8FxD6birYl4HXQfVgxOdbW7mpuLnz/hDbx7bPukhvT3FN+S1Nid2UuwicqTmj/fbr OBLgqgBIwyF4dIikayKNA= X-Google-Smtp-Source: AGHT+IGkQWfCACbqbbuCCFNQ2qKU8A9EFKMEKsAn+SUo7Bb1nABCAXucZJ/1Sbvypne34EZsM9fjtA== X-Received: by 2002:a17:902:f552:b0:297:c71d:851c with SMTP id d9443c01a7336-2a2f2736bc0mr15326595ad.36.1766122648538; Thu, 18 Dec 2025 21:37:28 -0800 (PST) Received: from Barrys-MBP.hub ([47.72.129.29]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3d4d895sm9930215ad.54.2025.12.18.21.37.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Dec 2025 21:37:28 -0800 (PST) From: Barry Song <21cnbao@gmail.com> To: catalin.marinas@arm.com, m.szyprowski@samsung.com, robin.murphy@arm.com, will@kernel.org Cc: ada.coupriediaz@arm.com, anshuman.khandual@arm.com, ardb@kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maz@kernel.org, ryan.roberts@arm.com, surenb@google.com, v-songbaohua@oppo.com, zhengtangquan@oppo.com Subject: [PATCH 3/6] arm64: Provide dcache_inval_poc_nosync helper Date: Fri, 19 Dec 2025 13:36:55 +0800 Message-Id: <20251219053658.84978-4-21cnbao@gmail.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20251219053658.84978-1-21cnbao@gmail.com> References: <20251219053658.84978-1-21cnbao@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Barry Song dcache_inval_poc_nosync does not wait for the data cache invalidation to complete. Later, we defer the synchronization so we can wait for all SG entries together. Cc: Catalin Marinas Cc: Will Deacon Cc: Marek Szyprowski Cc: Robin Murphy Cc: Ada Couprie Diaz Cc: Ard Biesheuvel Cc: Marc Zyngier Cc: Anshuman Khandual Cc: Ryan Roberts Cc: Suren Baghdasaryan Cc: Tangquan Zheng Signed-off-by: Barry Song --- arch/arm64/include/asm/cacheflush.h | 1 + arch/arm64/mm/cache.S | 43 +++++++++++++++++++++-------- 2 files changed, 33 insertions(+), 11 deletions(-) diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/c= acheflush.h index 9b6d0a62cf3d..382b4ac3734d 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -74,6 +74,7 @@ extern void icache_inval_pou(unsigned long start, unsigne= d long end); extern void dcache_clean_inval_poc(unsigned long start, unsigned long end); extern void dcache_inval_poc(unsigned long start, unsigned long end); extern void dcache_clean_poc(unsigned long start, unsigned long end); +extern void dcache_inval_poc_nosync(unsigned long start, unsigned long end= ); extern void dcache_clean_poc_nosync(unsigned long start, unsigned long end= ); extern void dcache_clean_pop(unsigned long start, unsigned long end); extern void dcache_clean_pou(unsigned long start, unsigned long end); diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 4a7c7e03785d..8c1043c9b9e5 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -132,17 +132,7 @@ alternative_else_nop_endif ret SYM_FUNC_END(dcache_clean_pou) =20 -/* - * dcache_inval_poc(start, end) - * - * Ensure that any D-cache lines for the interval [start, end) - * are invalidated. Any partial lines at the ends of the interval are - * also cleaned to PoC to prevent data loss. - * - * - start - kernel start address of region - * - end - kernel end address of region - */ -SYM_FUNC_START(__pi_dcache_inval_poc) +.macro _dcache_inval_poc_impl, do_sync dcache_line_size x2, x3 sub x3, x2, #1 tst x1, x3 // end cache line aligned? @@ -158,11 +148,42 @@ SYM_FUNC_START(__pi_dcache_inval_poc) 3: add x0, x0, x2 cmp x0, x1 b.lo 2b +.if \do_sync dsb sy +.endif ret +.endm + +/* + * dcache_inval_poc(start, end) + * + * Ensure that any D-cache lines for the interval [start, end) + * are invalidated. Any partial lines at the ends of the interval are + * also cleaned to PoC to prevent data loss. + * + * - start - kernel start address of region + * - end - kernel end address of region + */ +SYM_FUNC_START(__pi_dcache_inval_poc) + _dcache_inval_poc_impl 1 SYM_FUNC_END(__pi_dcache_inval_poc) SYM_FUNC_ALIAS(dcache_inval_poc, __pi_dcache_inval_poc) =20 +/* + * dcache_inval_poc_nosync(start, end) + * + * Issue the instructions of D-cache lines for the interval [start, end) + * for invalidation. Not necessarily cleaned to PoC till an explicit dsb + * sy later + * + * - start - kernel start address of region + * - end - kernel end address of region + */ +SYM_FUNC_START(__pi_dcache_inval_poc_nosync) + _dcache_inval_poc_impl 0 +SYM_FUNC_END(__pi_dcache_inval_poc_nosync) +SYM_FUNC_ALIAS(dcache_inval_poc_nosync, __pi_dcache_inval_poc_nosync) + /* * dcache_clean_poc(start, end) * --=20 2.39.3 (Apple Git-146)