From nobody Mon Feb 9 04:02:49 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0422F337680 for ; Fri, 19 Dec 2025 14:47:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766155656; cv=none; b=ADdXNCP2WGwyq7BrvEvUpEBihQzWV8f72oBvTF/NNBU8L+YjVQu4WIEv4zvJ+lRHXLK6ZZZQuaJH2SiPVQU8iZM5rAmsgbK86AQQQ9pMjUy8X8wfkgxS91LpETkkg2FoW5eDBa2zkso4wLBOSjbjScDgwTDM0DftOFKX6LfNDJw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766155656; c=relaxed/simple; bh=tvnF6b6bmdFNtT9eNlHsTHBdpRoglpPCbrEKqVihJrI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=d/iMiepN/hymCoTltYgU8c1XMwW4SfWD/wX/+HpaOCPuYa/V1PJckl7KHeHjrIEezZGb/9wHIN8ByH6d/fYR9f3C3RkvZ9qQh57C8jyZ67FTpExnWWzS4JE4q8ZjMNn1GWHXcZ+UVPfPrcyJZVkh55WYb+9kxIoBxneMreNcpsw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=kn8iOO5+; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=IpoPnRI3; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="kn8iOO5+"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="IpoPnRI3" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJAqwEv3999441 for ; Fri, 19 Dec 2025 14:47:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= xSOvkrCQO6Ag1SPdS9SjxXj3fHZBIceCMll5gHyoV+c=; b=kn8iOO5+q9clOlUl BdRAlujtH6Ag7madWJb9IdxXtbSgsoZEjLynmEtJTsZM98by7C1ORVA+oYEeNsEf iJFFoGMqHXbpWpuTx+S5IZcLIv4td/B9PPod3MFyIOIKO1mao+QTSke19sOSTb3f StoBkLI52lVrvscSbT/OJWe0hi4/Hzcqnec9NWOAiuWzwywo4Qdyg2JdEkhPK3ze nzXTwPbpNy5gQroL6yh+1rrt5bkMLVwSbQ8afyp3KTHTVGV+yYc2RwOIvOYn0428 sJAqf5MRb/BP5jQFJSjMZ3Dvjd6D+lTmzL2g1CMjr3ief6AddxUAnm3ihTqVzRGk 1nmzoA== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r29k0uf-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 14:47:34 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2a0d43fcb2fso48915915ad.3 for ; Fri, 19 Dec 2025 06:47:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766155654; x=1766760454; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xSOvkrCQO6Ag1SPdS9SjxXj3fHZBIceCMll5gHyoV+c=; b=IpoPnRI3lNu784Kt2V5DrnFpLowm1VRjGJaeKow34xEyEpX+JBDs5BXIFE59P/w829 SP5XjHmpBB45RTZ0QrepTHBtngRRyGvQ5txgIp051JfgMhTT9BiBsO37YyAYofxPwCT/ eky3+CjfBwBW7dcoTD6UXhnCsxz31w2bNuiVdPOBtTvl66VHaiwEBNMnMDnI1FZ1metE POBg4/JHpzZEDkwYGvo7g/MbAJymWPSzHobuAWDYXDaA/S2r/3aj2AWjliLNCT+lnF7L USn9Q0GNIEafgSB1531Q60mDbgsdvosf8liGcBQhgkKQ10bzddnrZqzbZ0uMLsZTwgIt q7bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766155654; x=1766760454; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=xSOvkrCQO6Ag1SPdS9SjxXj3fHZBIceCMll5gHyoV+c=; b=ElDj5GS8EX1//jxJrqvZmA/q2FyGCB64fUNiPdznXzXf2A9YK2Ln0Y2IXTtsYIMR9i rQvPP9rAfxqtdhYhArl/2sAD21Ot2z8Nrrw5or5FARdgXX7KrJUBUkuQyjcEjrUIhKTo dzyWjoB1xUYvyuTWVX0TMUYsS8+L3kf17rmRiYodUQSLNpCSMwBhCaxz2u5hN+j62h3v OolFHCTcsDDsNS0KMP+naaX6oB1/nUAB0Za4t7Em4n/sEuhBp9aF3Qg+yXFYs5yHsGFJ UTcn5vizBLeA7Dn71nAK/TJJw0w6DCjBgznSDnEE4sQ9nvKrHG7NYjr6htBo5pmkSYvG jDQQ== X-Forwarded-Encrypted: i=1; AJvYcCUBnm/MgwyVzRbJUkUGSqBzkvXCarD81fMB8RsjEm8TWhsPZZZ9bao9769NOhzpibbfQJxgA25+s/QKtb0=@vger.kernel.org X-Gm-Message-State: AOJu0Yynd+N6DWqDTsBRxXaCaoGY4OgU3Z2g73vWnaYPNtCbMmhDUgBe tm4v73HwazrKMUZFRhIcseBvx/iM/zX9r3hRLGT+qo1aGxUASN67fCqimboNQ6jpi8Of2v4CGDh 1FDXLH1vjkhzkwnGcCylujd4z/2YIfom28HgoUMl9CDv5dwgEDfuUf05p75PoG8scYRg= X-Gm-Gg: AY/fxX7RyueZAIFW8Q5zSuvMjjrRt/Q1vrhIn0wev7N4D15RGXEnM7pDjKbaoU56xht Ss9MAin2aCG1D0ozExequd/WXsW4fpLkaPOV2kmDZis0t/H/d0SWIeBGZG7wMvKQ7COa1AaS5HP Vi9TCo44xejDjxP4fU6jhijrDmi9y+XUrmpxpOk0g7gU7EAduV8NkuKFFuB43dVs1dlT1Wd3uch sG1iFQgVUgfnKp9Wme8mUl1X6K06AreTydNXJbrJ5AKXI5Mvl337/r9ZBWaB8zra8swvaQ9z89P INpcDKKhm657bXTykqi86b4YjRPw4pdsvCjqM4OKibm3XVxmdXKBlEkMvkz639G0fcjAwJ0H2DQ nON42InoYrLTyTVLVlW1J9bj7vJW7C5HqkWRxb29uOrXyjzSf6peLJIcgsD5WGeNn3QGX/jm0FG 0wPCfRXzrSjqL4WwUPApm0ej4gu1QU1A== X-Received: by 2002:a17:902:e552:b0:2a2:caca:35d2 with SMTP id d9443c01a7336-2a2f22273a7mr29329795ad.16.1766155653578; Fri, 19 Dec 2025 06:47:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IHtnLKvWRG3pUCwzqHCv+5MQZo6/M486Fc51APt819jom0Xlk+IlUR0S+CC/VXIn21R5e/+Fw== X-Received: by 2002:a17:902:e552:b0:2a2:caca:35d2 with SMTP id d9443c01a7336-2a2f22273a7mr29329425ad.16.1766155653050; Fri, 19 Dec 2025 06:47:33 -0800 (PST) Received: from hu-pankpati-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3c8286esm25433855ad.33.2025.12.19.06.47.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 06:47:32 -0800 (PST) From: Pankaj Patil Date: Fri, 19 Dec 2025 20:16:54 +0530 Subject: [PATCH v3 1/4] dt-bindings: arm: qcom: Document Glymur SoC and board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-upstream_v3_glymur_introduction-v3-1-32271f1f685d@oss.qualcomm.com> References: <20251219-upstream_v3_glymur_introduction-v3-0-32271f1f685d@oss.qualcomm.com> In-Reply-To: <20251219-upstream_v3_glymur_introduction-v3-0-32271f1f685d@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pankaj Patil , rajendra.nayak@oss.qualcomm.com, sibi.sankar@oss.qualcomm.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766155644; l=801; i=pankaj.patil@oss.qualcomm.com; s=20251121; h=from:subject:message-id; bh=tvnF6b6bmdFNtT9eNlHsTHBdpRoglpPCbrEKqVihJrI=; b=Vp7nU0Qpmu8QNy/GMP6Es90wP7U+Tkg8a4a8LtexFxSMBJE4HnjZNkMV6cv9B8sekK4gE0j5B fgTcXwvfzcTCta8l1FvnyKOEr1QqHNeEMy/yqH0+SqK9pId+RNBE90e X-Developer-Key: i=pankaj.patil@oss.qualcomm.com; a=ed25519; pk=pWpEq/tlX6TaKH1UQolvxjRD+Vdib/sEkb8bH8AL6gc= X-Authority-Analysis: v=2.4 cv=P6c3RyAu c=1 sm=1 tr=0 ts=69456586 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=KVNckf8Hb-gWPUCTgC0A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: 2o5E3XVrVKc4DGZRtBoRYqBK7QcuqSaY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDEyNCBTYWx0ZWRfX9wHf/8F7V+/j Sxxn+klSzGHmEB9UEvkRiI+VFrkafks2fI6ke0dF/ptVXflQUe0Xpy3CiBiUzFxsNR4OOsjfKbq Tsh9/fAlJs9nt1q9ksEYeJ1p1aurwd23+7EKT+fBCSH85mMMShUHBtsyWeD0Zh+8TCaj1awjfab elH4U2E74H+ivRScwH89lwv2JbXfIWULqeh8xT+hZ3RKEBADGBDO/zZdTLCgbsa9/3ZUJe3KqQj p589H8LGvMKWCgMbszzKesG3wj15aoZiRxUpTE0vH8G6xLjQTdMxHjZhkpNZbYjoNGImoDqEhw+ JUyWBDfNhTkBZEooD5QwfDg+B9m7sN6XbhjMw3UOTjw+PGe06qqxH2zGSJ+LoQqJsHakQfDRTEv sOF5h92g87e+NBxP0t0IztO7OZV9ry3ZPxvD5oTaDQHLb46EQrKI/JaMy3N93O8vl5Zzv2AE3eb 8QTQRD0acf23aBXuuHA== X-Proofpoint-GUID: 2o5E3XVrVKc4DGZRtBoRYqBK7QcuqSaY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_05,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 phishscore=0 priorityscore=1501 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190124 Document Glymur SoC bindings and Compute Reference Device (CRD) board id Signed-off-by: Pankaj Patil --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index d84bd3bca201..b6398bc8c588 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -61,6 +61,11 @@ properties: - qcom,apq8084-sbc - const: qcom,apq8084 =20 + - items: + - enum: + - qcom,glymur-crd + - const: qcom,glymur + - items: - enum: - microsoft,dempsey --=20 2.34.1 From nobody Mon Feb 9 04:02:49 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7421133A71F for ; Fri, 19 Dec 2025 14:47:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766155660; cv=none; b=RZEHn6tY50T+dQDuoX5zRz81f9+84LxN2a04VEIYkP2XoR4gFoiiyKS/ujrn04QcZormq5geqcN53Ch6pgUe9fmFfTBW8+aG6c6Ro65PszpgX01L1KQqDHrITxmP+z3DnHOvvlrTNJFg7Z4YIU1fS99VGNmdM5K4X+AroLb9ob0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766155660; c=relaxed/simple; bh=REbU3xbh4FhgmPEXDqlxy22tlOdJMrBnjksJAi1Cfuw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HPjIJr2acQ0G6s/RA4vJGR1wHuGEnUI4d0Udx220FU7lAg2ZqwU9Bf0mu/DuZAIQFvuqKRUrLNsayM3bLf6oo47AZIPLvQchZq7cm/HCe7n9uGHX4nhiWluM1ibUX/GB1h1MjJgiT8yCTot5LojCbi2cvDLJdSDtss9q+HwaDlU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=NaJ0+wa8; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=T/3inuWH; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="NaJ0+wa8"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="T/3inuWH" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJAvHJh3559188 for ; Fri, 19 Dec 2025 14:47:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= YvyklULcBWONHB6zHUzf6hIC7VGn5yKC57kVjZLZUrQ=; b=NaJ0+wa8mq+8xVGB nueinR9AlcG+JmTzvY5kIlUEDlSDjAwGRe6bEaNuFYZQSCFkJPhHEJFu59EYsXB1 J5pa3kIqErYESI+NCtbzRz3U9UAyO2zEvmma32h3RKFob9MvISRDRjOeHB+HWdU1 DVtGUZLbVnPXWVO+yAhfklCTVsg394yk3kg+LXCSd4tejOwc/q2TvOLM7qA0lAu8 uLWFivRlamOTEmb8gZQYhgfP3rv5LKkcErXe4N7JQOHdAc/uBlShzhJzAW6hBT2R sMX+T5+QfQsP7n/f0wIpEEEoqOrEf8Vr1k9XjroKBXeaxkNUzcDqkq+25/NeitD3 NLsgxQ== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r2cb17s-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 14:47:37 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2a0e952f153so50519585ad.0 for ; Fri, 19 Dec 2025 06:47:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766155657; x=1766760457; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YvyklULcBWONHB6zHUzf6hIC7VGn5yKC57kVjZLZUrQ=; b=T/3inuWHt0Zc8NBA7uEdoQ6qH96bT0HcOqonVDgUsPmoysaZy8N72REFTxaUVWXGcC q8/Fspi3TAkm3GMpmyq5pmfLzlIdJWVB97UzyOcNozVB3csIYju9N8hXmv/TjGIRzRmg q9Ked+CP/Xke0hh52sNZ52RvMwdry7y3MXYOHrggREej3tNsdaNtryJKt0nu0AZohe5K I2U9NkUnoXFGCqm7S39cd6WhriZPZF+5BVCcQ2ePLs10CeXAnEJX0F2CN5byuiEMtQCr V/0gNAv2Tap1tuNZuxF3pZkvtlt62rfIKD+XjG1yhMyo0pLpo9UGyfqjWqf5Y63EcmZl qUkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766155657; x=1766760457; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=YvyklULcBWONHB6zHUzf6hIC7VGn5yKC57kVjZLZUrQ=; b=bPBbXveARTUh9TCV6JdNGADEkVZ5JmSnPs22fBkoP/dISmLIIoCuRpFC/BTxjep3Lc yqgPiSgByJEKwSbcNc8Qytpq6O/aXycEIJJQZNr79hu2thRkM8/bDy2/Mi0X/oJBxalR E2uOZE8ag0PIepXiHDNTB18yAibZ8gohBEGcS4jfdpuU+qf2MhZe0yrXxE1lr4fA3rDJ Ys31XAJYLEu4s7lk4RKZj3gjjcTpfz5SJIHgs7LvFLUcPbL2psAwoMc3icQ41AshvhZI vLiFK0qXbLq6Vgqpe+1ei8dI/9YwD8nazUf80nlXDay7rF8oerc9SbxMoUO6kzgl7uQ+ UDng== X-Forwarded-Encrypted: i=1; AJvYcCVpF+16v9DCRCwQ3rpLpMYVGBc8w2OMaLDiKfWY0Ee6y1Zihy31caPmLSMPx4rwghleV1/MDJlcnzTsRLk=@vger.kernel.org X-Gm-Message-State: AOJu0Yy6O8McDkcC4poiKDWSMkM7rA+CQ+NL54YFAFv7SGhECnb+XnYP bFwxtLXYCETX4/oi4BjYNgkaUhCa3fXf+n2ZjJFgQcIQ/72uhKgpAgPCBCX2YDIUJYXNCynWVqW OEtrM6X/2JFC10h+5+SEywSE3u0I8TBmWw5/9eF4NoNlk/ocjV/JX2JrAEOo0ll/CCfY= X-Gm-Gg: AY/fxX4kjI9TRYmnA7pp9Pes0VHS8wrf/SOT7SEYkJSwtoihzkFZ80e7iXuA/j2r3Yx CMn69Fqr+OoLDvMCYYkBgpMPnBwHvaYTscjkVJQ+UKtdCDW/7/OnFTyKpBnI+hHnxZ9wv+nGlbW bRePkLW4X15iCT9AE34q5Q1hkbdkCuHeTuJcSQ0InzFYQGP1TDu6S/L0hP3MCJlHpbb5AttB/os +p3nfjT/m9tcVQ0dPGj5XIWx2BxaX/lZx076vFxKa/5FeftTGniKbuaBKGz1SQ/KrXuuQuOyzD6 9xrAt0DR3qSG/vn/IztiEYkzv/RfYMbAJk5DzMS92aFGJWgsnIF9SNXJzfvASuTAMAquOlNexPt ImXTMTktiT+ED16Q3VfOoLdwyFPd7Mnkr/S+6EfQtB/Dgx7xntZdTjhkxXv0x5zh7iXern3oTdq TLbATJRPOW11bv/Fy7ZyMIVDoKxBqq3Q== X-Received: by 2002:a17:902:ce82:b0:2a0:c1ed:d0d9 with SMTP id d9443c01a7336-2a2f29359b3mr33327525ad.46.1766155656872; Fri, 19 Dec 2025 06:47:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IFU/iBbketQynSkW5giGh3TgnwEV/xNF/jMruv4fU3BZmlZCud6GMasORULASLC2d3XegdmiA== X-Received: by 2002:a17:902:ce82:b0:2a0:c1ed:d0d9 with SMTP id d9443c01a7336-2a2f29359b3mr33327115ad.46.1766155656325; Fri, 19 Dec 2025 06:47:36 -0800 (PST) Received: from hu-pankpati-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3c8286esm25433855ad.33.2025.12.19.06.47.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 06:47:36 -0800 (PST) From: Pankaj Patil Date: Fri, 19 Dec 2025 20:16:55 +0530 Subject: [PATCH v3 2/4] arm64: defconfig: Enable Glymur configs for boot to shell Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-upstream_v3_glymur_introduction-v3-2-32271f1f685d@oss.qualcomm.com> References: <20251219-upstream_v3_glymur_introduction-v3-0-32271f1f685d@oss.qualcomm.com> In-Reply-To: <20251219-upstream_v3_glymur_introduction-v3-0-32271f1f685d@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pankaj Patil , rajendra.nayak@oss.qualcomm.com, sibi.sankar@oss.qualcomm.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766155644; l=1510; i=pankaj.patil@oss.qualcomm.com; s=20251121; h=from:subject:message-id; bh=REbU3xbh4FhgmPEXDqlxy22tlOdJMrBnjksJAi1Cfuw=; b=gMQ0yi5n9c4RyldA44ZJieq/ULb41pM0Dv14bCeLu0YMKnJGdxbzQbHAxAvl599L1dvo0QoPy KarCiGx1DBGDMwjJL/5XoNbKJmrWzypQB5XNQ0E26eE1ap+luu+rMrL X-Developer-Key: i=pankaj.patil@oss.qualcomm.com; a=ed25519; pk=pWpEq/tlX6TaKH1UQolvxjRD+Vdib/sEkb8bH8AL6gc= X-Authority-Analysis: v=2.4 cv=cpSWUl4i c=1 sm=1 tr=0 ts=69456589 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=G4s3PgB1coGp2Q1p4bUA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDEyNCBTYWx0ZWRfX3ovFde692m9Z 8m5JuacwXAvZ5wryScdsttzbQLQXRa9E5Vvc8TpXep5vvNZMKaR6aYY9bPA0YdZy4xtsLQckKZ5 hwwx7AsKmG4d3fRZ7UVpaF5U91BxGN55K5XboeR2DoWtiH+qnmQFx2zNp2mIrVKFm3t22POrbDo Y7lJsZzcpvKbzG7PBKfxJjeaVyJK3LMiRgoh7Ze6K6chil+aCEH0Ao4AAdahcbUrf6ON9cMEwGi h6i6+kZS+Na3xhzvdO8qZFWJunjJ0LshmIrFb6ZMMgG2vVoc4SQV+uLZ+jxvchX5JiY66shsrRK 4x0gEsOvSys+iWt4oHf282o/MXe09OeEYt5o5TZORl4lO5ifsACwdH8iLGm0rPeib+sUJls4/BL c4XgIIAT1opsjr316DBbt8+J2Do7GAI2/QULpgBaLTOMO3zr1dFU9dztcCO8DKztiLB7YCX6Tzn j4pptwUL32NBdBk5jLQ== X-Proofpoint-GUID: FTXUGK1IHI-ZDQUct20L6X8HaqCfb1aM X-Proofpoint-ORIG-GUID: FTXUGK1IHI-ZDQUct20L6X8HaqCfb1aM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_05,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 suspectscore=0 bulkscore=0 phishscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190124 The serial engine must be properly setup before kernel reaches "init",so UART driver and its dependencies needs to be built in. Enable its dependency clocks,interconnect and pinctrl as built-in to boot Glymur CRD board to UART console with rootfs on nvme storage. DISPCC enabled as module, used for display. Signed-off-by: Pankaj Patil --- arch/arm64/configs/defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index cdb7d69e3b24..1272422eb727 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -636,6 +636,7 @@ CONFIG_PINCTRL_IMX91=3Dy CONFIG_PINCTRL_IMX93=3Dy CONFIG_PINCTRL_IMX_SCMI=3Dy CONFIG_PINCTRL_MSM=3Dy +CONFIG_PINCTRL_GLYMUR=3Dy CONFIG_PINCTRL_IPQ5018=3Dy CONFIG_PINCTRL_IPQ5332=3Dy CONFIG_PINCTRL_IPQ5424=3Dy @@ -1425,6 +1426,9 @@ CONFIG_COMMON_CLK_MT8192_SCP_ADSP=3Dy CONFIG_COMMON_CLK_MT8192_VDECSYS=3Dy CONFIG_COMMON_CLK_MT8192_VENCSYS=3Dy CONFIG_COMMON_CLK_QCOM=3Dy +CONFIG_CLK_GLYMUR_DISPCC=3Dm +CONFIG_CLK_GLYMUR_GCC=3Dy +CONFIG_CLK_GLYMUR_TCSRCC=3Dy CONFIG_CLK_X1E80100_CAMCC=3Dm CONFIG_CLK_X1E80100_DISPCC=3Dm CONFIG_CLK_X1E80100_GCC=3Dy @@ -1801,6 +1805,7 @@ CONFIG_INTERCONNECT_IMX8MN=3Dm CONFIG_INTERCONNECT_IMX8MQ=3Dm CONFIG_INTERCONNECT_IMX8MP=3Dy CONFIG_INTERCONNECT_QCOM=3Dy +CONFIG_INTERCONNECT_QCOM_GLYMUR=3Dy CONFIG_INTERCONNECT_QCOM_MSM8916=3Dm CONFIG_INTERCONNECT_QCOM_MSM8953=3Dy CONFIG_INTERCONNECT_QCOM_MSM8996=3Dy --=20 2.34.1 From nobody Mon Feb 9 04:02:49 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E305327C0C for ; Fri, 19 Dec 2025 14:47:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766155673; cv=none; b=UYYChUlWKgUbtnJv7mrQPdTmmdvknrcFvPP67LvHhIcxDLqNlAg//900zXmk7JbHVYUbZ7v2GDN+VexfZCbBa6SsujiWEkqBzC+a2C9TBEdC9hksLkJApbuiMBFduE8vrEmdUClQWXSQAXVWhRbYuZVB1zUsrLNnMu6jl35XQkc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766155673; c=relaxed/simple; bh=UxTsAKTc2+SH+Hg0aZVqnZyB0AGSYJZzfrFCppiMHZo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cQe/zaq77elJdmVNmGQbYBe8M5tHUz5bublp6bp+RBvCKBUJkfZhroNyz7T86APIcMdSiHRa7Nb1vCq3ZR5XHxZTsxxc3LHj0Uz/UG1xK5RqGhc3uYdp0tBaojt7uZcG4Lmb0MI2+GEY7Roh262PctSsujnNShl8gUKYdZ1CpaQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=JQ3V6vjI; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=aVyS3x+v; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="JQ3V6vjI"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="aVyS3x+v" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJB1ETi4154540 for ; Fri, 19 Dec 2025 14:47:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ZBZVYWMlcrhumQUSMx8YBXefvwIxFTXhnI7p1hI1ZD8=; b=JQ3V6vjIL9urKPTG hJ8tbCI+h0TU0+XXkSFyL8UlbZi8v3zU0l0SLWUIiWTfRF/vg/qZKBvOIgFlMue7 xYX0UZMl50uxhG6c1cS9ZC9/9OdHqB6AAqqpMPIj0IDOL7rnOa4UAFkRhyv/nUMZ rVDApbnvOURJbeW/RTAiop3+yt+P0YssN7oH7a/vs5YkD4t6LNFxkfLCpqLgDbHp wvTpRgxhV0O0lLWOznDQzwz7lzMEWpW9BycpfAty4Jxe3UUUKHJawDhDV90zkiq5 2maEswMip7Bw+vu6ROUfKsAs/I/mom8DIGYVW8YxfQlXzq6gZGnPz4nisz+4q8Gp Am7B6Q== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r2cu11x-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 14:47:45 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2a0e952f153so50522545ad.0 for ; Fri, 19 Dec 2025 06:47:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766155665; x=1766760465; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ZBZVYWMlcrhumQUSMx8YBXefvwIxFTXhnI7p1hI1ZD8=; b=aVyS3x+v31fzhbhH/pa/0WEONX8bAjxBCX7fOeP7RzyUXr8LxMtsRQqdsySSxD9jty kPkdh6taxHZXGklXY5LC7+ykQmTSLc9SuqYap3Lqi5Mw/G0uCrddNM9lUTxGm91tWdQE d+6/UL/ZtBRzOIAER4KFUf7TvzHtojB+Gu+DylVXxQ1fEAGvRz/viZoeQ6Jr3obdzMN2 KAxvRVSAdq0dkcsbBmvCbZ2DuZKSKCs481EQcqJIdHUi3asFw/bdHglzTsuj7t4UMz/u M7xL/Y+IVAb8UpAjyfiGjgw0u3x8CMdATanrRONdkZCjDlOq+dJ/Nejc0Zu7p9R7inwm ubYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766155665; x=1766760465; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ZBZVYWMlcrhumQUSMx8YBXefvwIxFTXhnI7p1hI1ZD8=; b=fSm/Q4MD7kbG4RwiaAPuGJ1Zd3LmhGGXaaJoLcMWq/5HqA84N0Jvsl01tektpnIp0j dz1QHwkBfbNU+fDe7VrWMX06XwLZgDfhOIlJH03gaD1d2DsYXwvsK8jxJMeeifIFPi7R 9KAs3DWPcTP1ZhVP9fwUENp40Ix+E1XUYNSEk/EJk/GLTGa+T6jJ351V15a1QDzlw3dp Vh3hQ0AtHK5kI93JlaCGWDzMCjyrvYQf5QlmCeaLSLxACF/9Y+rosKIQwB01uYT0Wpxv dxY1cnjV6pdwdc6jJW27HSwUBoOAKY8xIF1QuK9WNXXHgcb3xNP8S2RB+AzZMOkBOkzv QKfw== X-Forwarded-Encrypted: i=1; AJvYcCUr5Av2xfUopcxo+GPcBCVZWXcpGs4QcYnK+Pd6+YRUIKLd4Dg8jZls7HIGqFDHVV9v0zvJeHCURHQyvkc=@vger.kernel.org X-Gm-Message-State: AOJu0Yx/danD6zUTRmcHDE/ViIV+nOdz0AtfheMwp9KkqkI3PCHjUGFr HP4q3bRZtMPmQ1yk01K7qXyAS5FwqzsriJAzi/U2M6clvwBkU+f5dAFeHiqHxipt/xu1apG835s Wod1fTd2BxzZqIR6cC4+DPMDTE/JR2UC1qCkNg7aukILA5UNv8ZOd3OiowQ2EolbVcOk= X-Gm-Gg: AY/fxX4D2rZwAML7b9WEVTxT70czzS0CRI0QaBkH/a7V7IRStTxWxO70nuvZqVCCa2S dn9aJcw2xS1E4lRTnXXjdfSjQcpxzDMzjANp4z4VHumVUj5xszjkjCYCihFj/ZxmrWGl1SVwSTs Gk8OL8lT2LmgxcTmhoKR6DQ+lCGAQVplKwCj1cjDVOLQDorvCTKzsQZTv7pR5REN1lRgvM6BM2v Yoy6blvubf/qeUjvDF4p0oT30GyHoI6QIkzI0AOsImD7//9W4mFAE001iqh32/3rhRgXKvWVw6l jJhoj43AhUgOXnlAA9Jt0sCJLYsqgVhFEvZUE/kIb1DYSRAiVKzukkNvSmCimjLZQAUtjQGKfnM N7WaiXEZ6o5xt7Pki59rsfYTnoeshDTAlVeNgJQZqfOy5w6+rjGayHKPw/h/q0Dt51xvSB9BR+v x8h3VFM8QHFjyagHCXLTIZRSbocG+T6w== X-Received: by 2002:a17:903:2448:b0:2a0:8be7:e3d7 with SMTP id d9443c01a7336-2a2f2a4609amr30869795ad.57.1766155663407; Fri, 19 Dec 2025 06:47:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IGztc7916DyzHfdE1+oMmcizI5BCcuphGSaGj0IWaodzSEulSnsxLxn7QPpfU01DG/KSfN0Xw== X-Received: by 2002:a17:903:2448:b0:2a0:8be7:e3d7 with SMTP id d9443c01a7336-2a2f2a4609amr30869145ad.57.1766155662257; Fri, 19 Dec 2025 06:47:42 -0800 (PST) Received: from hu-pankpati-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3c8286esm25433855ad.33.2025.12.19.06.47.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 06:47:41 -0800 (PST) From: Pankaj Patil Date: Fri, 19 Dec 2025 20:16:56 +0530 Subject: [PATCH v3 3/4] arm64: dts: qcom: Introduce Glymur base dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-upstream_v3_glymur_introduction-v3-3-32271f1f685d@oss.qualcomm.com> References: <20251219-upstream_v3_glymur_introduction-v3-0-32271f1f685d@oss.qualcomm.com> In-Reply-To: <20251219-upstream_v3_glymur_introduction-v3-0-32271f1f685d@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pankaj Patil , rajendra.nayak@oss.qualcomm.com, sibi.sankar@oss.qualcomm.com, Jyothi Kumar Seerapu , Maulik Shah , Taniya Das , Kamal Wadhwa , Prudhvi Yarlagadda , Qiang Yu , Manaf Meethalavalappu Pallikunhi , Jishnu Prakash , Abel Vesa X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766155644; l=171771; i=pankaj.patil@oss.qualcomm.com; s=20251121; h=from:subject:message-id; bh=UxTsAKTc2+SH+Hg0aZVqnZyB0AGSYJZzfrFCppiMHZo=; b=CWVaUUkf2Z8nbqgdpS9zDnBoK3ILGU2wtBgWcVFi8LnCg06mYjcYBk9iVbnnZuVeS7jxi52Xz oC59A1hKNchAxKfm03aNJCgW25mYT35AmL7a/BOPGwHwM20uUQSeIsI X-Developer-Key: i=pankaj.patil@oss.qualcomm.com; a=ed25519; pk=pWpEq/tlX6TaKH1UQolvxjRD+Vdib/sEkb8bH8AL6gc= X-Proofpoint-GUID: NFGUcdl-3pvhuQFoG8RXiP_LLfPvYFoO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDEyNCBTYWx0ZWRfX1LuzmEOsdWwg 2TqTrvTLjKprgdFFoqLiyA2VEQAhp+ndaDj+4mHkmNd+VnTPrnTCnpZaMl+WBSnggcGr7Yd9yEb UWrvWz40PigDpmhyLbxjtC0cws/GpvMZoJHF9tAPKfy1BjJ4qmUDoNKUyftDIIF3ncVLXVO1Lcd lQuQXxiBtckU0+5LEtQt0KKfkuUbbPTf4ggrZx6zSNKXRYbEwaUreApKyQ+iQpv2CdADe6LUd8a witiAX3eDRDQTsHq9ql3wyj+9ULUWZjKA/KbEcsALMh4i3ErKBeJEVQAZ7bEjlXfQGIdNeZF4ou hGmY/X3bf22VZIaCoY2A8AS+WRJex19hdHC/QLjzSATUCO+S2gCZn/jrrYQlf8FHZvv5JSE7nAV /oxKsyCfUU7+A7DTbAwu1QBm0vSXabngJEpNFUehqiZ7ThtJJRvuvTTfu2uHsRdNfHN4+6buYXx 8fgBwd0NzCi2qpX8b4A== X-Proofpoint-ORIG-GUID: NFGUcdl-3pvhuQFoG8RXiP_LLfPvYFoO X-Authority-Analysis: v=2.4 cv=Lp2fC3dc c=1 sm=1 tr=0 ts=69456591 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=Q_niEXVsVk0kqZ-VUI8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_05,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190124 Introduce the base device tree support for Glymur =E2=80=93 Qualcomm's next-generation compute SoC. The new glymur.dtsi describes the core SoC components, including: - CPUs and CPU topology - Interrupt controller and TLMM - GCC,DISPCC and RPMHCC clock controllers - Reserved memory and interconnects - SMMU and firmware SCM - Watchdog, RPMHPD, APPS RSC and SRAM - PSCI and PMU nodes - QUPv3 serial engines - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS - PDP0 mailbox, IPCC and AOSS - Display clock controller - SPMI PMIC arbiter with SPMI0/1/2 buses - SMP2P nodes - TSENS and thermal zones (8 instances, 92 sensors) Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104, PMH0110 along with temp-alarm and GPIO nodes needed on Glymur Add glmur-pmics.dtsi file for all the pmics enabled Enabled PCIe controllers and associated PHY to support boot to shell with nvme storage, List of PCIe instances enabled: - PCIe3b - PCIe4 - PCIe5 - PCIe6 Co-developed-by: Jyothi Kumar Seerapu Signed-off-by: Jyothi Kumar Seerapu Co-developed-by: Maulik Shah Signed-off-by: Maulik Shah Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Co-developed-by: Taniya Das Signed-off-by: Taniya Das Co-developed-by: Kamal Wadhwa Signed-off-by: Kamal Wadhwa Co-developed-by: Prudhvi Yarlagadda Signed-off-by: Prudhvi Yarlagadda Co-developed-by: Qiang Yu Signed-off-by: Qiang Yu Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Co-developed-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Manaf Meethalavalappu Pallikunhi Co-developed-by: Jishnu Prakash Signed-off-by: Jishnu Prakash Signed-off-by: Pankaj Patil --- arch/arm64/boot/dts/qcom/glymur-pmics.dtsi | 11 + arch/arm64/boot/dts/qcom/glymur.dtsi | 5700 ++++++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 132 + arch/arm64/boot/dts/qcom/pmh0101.dtsi | 45 + arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 83 + arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi | 83 + arch/arm64/boot/dts/qcom/pmk8850.dtsi | 70 + arch/arm64/boot/dts/qcom/smb2370.dtsi | 45 + 8 files changed, 6169 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-pmics.dtsi b/arch/arm64/boot/d= ts/qcom/glymur-pmics.dtsi new file mode 100644 index 000000000000..677dd1b74db0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-pmics.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "pmk8850.dtsi" /* SPMI0: SID-0 */ +#include "pmh0101.dtsi" /* SPMI0: SID-1 */ +#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ +#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ +#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */ +#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi new file mode 100644 index 000000000000..eb042541cfe1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -0,0 +1,5700 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "glymur-ipcc.h" + +/ { + interrupt-parent =3D <&intc>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd0>, <&scmi_perf 0>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_0>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd1>, <&scmi_perf 0>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_0>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd2>, <&scmi_perf 0>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_0>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd3>, <&scmi_perf 0>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_0>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x400>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd4>, <&scmi_perf 0>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_0>; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x500>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd5>, <&scmi_perf 0>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_0>; + }; + + cpu6: cpu@10000 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x10000>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd6>, <&scmi_perf 1>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_1>; + + l2_1: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + cpu7: cpu@10100 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x10100>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd7>, <&scmi_perf 1>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_1>; + }; + + cpu8: cpu@10200 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x10200>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd8>, <&scmi_perf 1>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_1>; + }; + + cpu9: cpu@10300 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x10300>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd9>, <&scmi_perf 1>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_1>; + }; + + cpu10: cpu@10400 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x10400>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd10>, <&scmi_perf 1>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_1>; + }; + + cpu11: cpu@10500 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x10500>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd11>, <&scmi_perf 1>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_1>; + }; + + cpu12: cpu@20000 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x20000>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd12>, <&scmi_perf 2>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_2>; + + l2_2: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + cpu13: cpu@20100 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x20100>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd13>, <&scmi_perf 2>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_2>; + }; + + cpu14: cpu@20200 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x20200>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd14>, <&scmi_perf 2>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_2>; + }; + + cpu15: cpu@20300 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x20300>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd15>, <&scmi_perf 2>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_2>; + }; + + cpu16: cpu@20400 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x20400>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd16>, <&scmi_perf 2>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_2>; + }; + + cpu17: cpu@20500 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x20500>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd17>, <&scmi_perf 2>; + power-domain-names =3D "psci", "perf"; + cpu-idle-states =3D <&cpu_c4>; + next-level-cache =3D <&l2_2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu6>; + }; + + core1 { + cpu =3D <&cpu7>; + }; + + core2 { + cpu =3D <&cpu8>; + }; + + core3 { + cpu =3D <&cpu9>; + }; + + core4 { + cpu =3D <&cpu10>; + }; + + core5 { + cpu =3D <&cpu11>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu12>; + }; + + core1 { + cpu =3D <&cpu13>; + }; + + core2 { + cpu =3D <&cpu14>; + }; + + core3 { + cpu =3D <&cpu15>; + }; + + core4 { + cpu =3D <&cpu16>; + }; + + core5 { + cpu =3D <&cpu17>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_c4: cpu-sleep-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "ret"; + arm,psci-suspend-param =3D <0x00000004>; + entry-latency-us =3D <180>; + exit-latency-us =3D <320>; + min-residency-us =3D <1000>; + }; + }; + + domain-idle-states { + cluster_cl5: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x01000054>; + entry-latency-us =3D <2000>; + exit-latency-us =3D <2000>; + min-residency-us =3D <9000>; + }; + + domain_ss3: domain-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x0200c354>; + entry-latency-us =3D <2800>; + exit-latency-us =3D <4400>; + min-residency-us =3D <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-glymur", "qcom,scm"; + qcom,dload-mode =3D <&tcsr 0x4000>; + interconnects =3D <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + }; + + scmi { + compatible =3D "arm,scmi"; + mboxes =3D <&pdp0_mbox 0>, <&pdp0_mbox 1>; + mbox-names =3D "tx", "rx"; + shmem =3D <&cpu_scp_lpri1>, <&cpu_scp_lpri0>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_perf: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + }; + }; + + clk_virt: interconnect-0 { + compatible =3D "qcom,glymur-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible =3D "qcom,glymur-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster0_pd>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + }; + + cpu_pd8: power-domain-cpu8 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + }; + + cpu_pd9: power-domain-cpu9 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + }; + + cpu_pd10: power-domain-cpu10 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + }; + + cpu_pd11: power-domain-cpu11 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster1_pd>; + }; + + cpu_pd12: power-domain-cpu12 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + }; + + cpu_pd13: power-domain-cpu13 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + }; + + cpu_pd14: power-domain-cpu14 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + }; + + cpu_pd15: power-domain-cpu15 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + }; + + cpu_pd16: power-domain-cpu16 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + }; + + cpu_pd17: power-domain-cpu17 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster2_pd>; + }; + + cluster0_pd: power-domain-cpu-cluster0 { + #power-domain-cells =3D <0>; + power-domains =3D <&system_pd>; + domain-idle-states =3D <&cluster_cl5>; + }; + + cluster1_pd: power-domain-cpu-cluster1 { + #power-domain-cells =3D <0>; + power-domains =3D <&system_pd>; + domain-idle-states =3D <&cluster_cl5>; + }; + + cluster2_pd: power-domain-cpu-cluster2 { + #power-domain-cells =3D <0>; + power-domains =3D <&system_pd>; + domain-idle-states =3D <&cluster_cl5>; + }; + + system_pd: power-domain-system { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&domain_ss3>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + pdp_mem: pdp@81400000 { + reg =3D <0x0 0x81400000 0x0 0x100000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@81c60000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + pdp_ns_shared_mem: pdp-ns-shared@81e00000 { + reg =3D <0x0 0x81e00000 0x0 0x200000>; + no-map; + }; + + oobdaretag_mem: oobdaretag@86e10000 { + reg =3D <0x0 0x86e10000 0x0 0x360000>; + no-map; + }; + + oob_secure_mem: oob-secure@87170000 { + reg =3D <0x0 0x87170000 0x0 0xbc0000>; + no-map; + }; + + oobdtbqc_mem: oobdtbqc@87d30000 { + reg =3D <0x0 0x87d30000 0x0 0x20000>; + no-map; + }; + + oobdtboem_mem: oobdtboem@87d50000 { + reg =3D <0x0 0x87d50000 0x0 0x20000>; + no-map; + }; + + oob_nonsecure_mem: oob-nonsecure@87e00000 { + reg =3D <0x0 0x87e00000 0x0 0xc00000>; + no-map; + }; + + spss_region_mem: spss@88a00000 { + reg =3D <0x0 0x88a00000 0x0 0x400000>; + no-map; + }; + + soccpdtb_mem: soccpdtb@892e0000 { + reg =3D <0x0 0x892e0000 0x0 0x20000>; + no-map; + }; + + soccp_mem: soccp@89300000 { + reg =3D <0x0 0x89300000 0x0 0x400000>; + no-map; + }; + + cvp_mem: cvp@89700000 { + reg =3D <0x0 0x89700000 0x0 0x700000>; + no-map; + }; + + adspslpi_mem: adspslpi@89e00000 { + reg =3D <0x0 0x89e00000 0x0 0x3a00000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb@8d800000 { + reg =3D <0x0 0x8d800000 0x0 0x80000>; + no-map; + }; + + cdsp_mem: cdsp@8d900000 { + reg =3D <0x0 0x8d900000 0x0 0x4000000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb@91900000 { + reg =3D <0x0 0x91900000 0x0 0x80000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@919fe000 { + reg =3D <0x0 0x919fe000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera@91a00000 { + reg =3D <0x0 0x91a00000 0x0 0x800000>; + no-map; + }; + + av1_encoder_mem: av1-encoder@92200000 { + reg =3D <0x0 0x92200000 0x0 0x700000>; + no-map; + }; + + video_mem: video@92900000 { + reg =3D <0x0 0x92900000 0x0 0xc00000>; + no-map; + }; + + smem_mem: smem@ffe00000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0xffe00000 0x0 0x200000>; + hwlocks =3D <&tcsr_mutex 3>; + no-map; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + + interrupts-extended =3D <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem =3D <443>, <429>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-cdsp { + compatible =3D "qcom,smp2p"; + + interrupts-extended =3D <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem =3D <94>, <432>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-soccp { + compatible =3D "qcom,smp2p"; + + interrupts-extended =3D <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem =3D <617>, <616>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <19>; + + soccp_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + soccp_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x0 0x100 0x0>; + dma-ranges =3D <0x0 0x0 0x0 0x0 0x100 0x0>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,glymur-gcc"; + reg =3D <0x0 0x00100000 0x0 0x1f9000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&pcie3b_phy>, + <&pcie4_phy>, + <&pcie5_phy>, + <&pcie6_phy>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + gpi_dma2: dma-controller@800000 { + compatible =3D "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00800000 0x0 0x60000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels =3D <16>; + dma-channel-mask =3D <0x3f>; + #dma-cells =3D <3>; + iommus =3D <&apps_smmu 0xd76 0x0>; + status =3D "disabled"; + }; + + qupv3_2: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x008c0000 0x0 0x3000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + iommus =3D <&apps_smmu 0xd63 0x0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + i2c16: i2c@880000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c16_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi16: spi@880000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi16_data_clk>, <&qup_spi16_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c17: i2c@884000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c17_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi17: spi@884000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi17_data_clk>, <&qup_spi17_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c18: i2c@888000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c18_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi18: spi@888000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi18_data_clk>, <&qup_spi18_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c19: i2c@88c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c19_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi19: spi@88c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi19_data_clk>, <&qup_spi19_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart19: serial@88c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 =3D <&qup_uart19_default>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + i2c20: i2c@890000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c20_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi20: spi@890000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi20_data_clk>, <&qup_spi20_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c21: i2c@894000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00894000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c21_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi21: spi@894000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00894000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi21_data_clk>, <&qup_spi21_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart21: serial@894000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x00894000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + pinctrl-0 =3D <&qup_uart21_default>; + pinctrl-names =3D "default"; + }; + + i2c22: i2c@898000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00898000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 6 QCOM_GPI_I2C>, + <&gpi_dma2 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c22_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi22: spi@898000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00898000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi22_data_clk>, <&qup_spi22_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart22: serial@898000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00898000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + pinctrl-0 =3D <&qup_uart22_default>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + i2c23: i2c@89c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x0089c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 7 QCOM_GPI_I2C>, + <&gpi_dma2 1 7 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c23_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi23: spi@89c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x0089c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma2 0 7 QCOM_GPI_SPI>, + <&gpi_dma2 1 7 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi23_data_clk>, <&qup_spi23_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible =3D "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00a00000 0x0 0x60000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels =3D <16>; + dma-channel-mask =3D <0x3f>; + #dma-cells =3D <3>; + iommus =3D <&apps_smmu 0xcb6 0x0>; + status =3D "disabled"; + }; + + qupv3_1: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x00ac0000 0x0 0x3000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + iommus =3D <&apps_smmu 0xca3 0x0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + i2c8: i2c@a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c8_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi8: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c9: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c9_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi9: spi@a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c10: i2c@a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a88000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c10_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi10: spi@a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a88000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c11_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi11: spi@a8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi11_data_clk>, <&qup_spi11_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c12: i2c@a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c12_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi12: spi@a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi12_data_clk>, <&qup_spi12_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c13: i2c@a94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c13_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi13: spi@a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi13_data_clk>, <&qup_spi13_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c14: i2c@a98000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c14_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi14: spi@a98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart14: serial@a98000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + pinctrl-0 =3D <&qup_uart14_default>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a9c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c15_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi15: spi@a9c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a9c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + gpi_dma0: dma-controller@b00000 { + compatible =3D "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00b00000 0x0 0x60000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels =3D <16>; + dma-channel-mask =3D <0x3f>; + #dma-cells =3D <3>; + iommus =3D <&apps_smmu 0xd36 0x0>; + status =3D "disabled"; + }; + + qupv3_0: geniqup@bc0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x00bc0000 0x0 0x3000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + iommus =3D <&apps_smmu 0xd23 0x0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + i2c0: i2c@b80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00b80000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c0_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi0: spi@b80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00b80000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c1: i2c@b84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00b84000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c1_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi1: spi@b84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00b84000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@b88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00b88000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c2_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi2: spi@b88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00b88000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart2: serial@b88000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00b88000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + pinctrl-0 =3D <&qup_uart2_default>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + i2c3: i2c@b8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00b8c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c3_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi3: spi@b8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00b8c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@b90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00b90000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c4_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi4: spi@b90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00b90000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c5: i2c@b94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00b94000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c5_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi5: spi@b94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00b94000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c6: i2c@b98000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00b98000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c6_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi6: spi@b98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00b98000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c7: i2c@b9c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00b9c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_i2c7_data_clk>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi7: spi@b9c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00b9c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + dmas =3D <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&qup_spi7_data_clk>, <&qup_spi7_cs>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + cnoc_main: interconnect@1500000 { + compatible =3D "qcom,glymur-cnoc-main"; + reg =3D <0x0 0x01500000 0x0 0x17080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + config_noc: interconnect@1600000 { + compatible =3D "qcom,glymur-cnoc-cfg"; + reg =3D <0x0 0x01600000 0x0 0x6600>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,glymur-system-noc"; + reg =3D <0x0 0x01680000 0x0 0x1c080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + pcie_west_anoc: interconnect@16c0000 { + compatible =3D "qcom,glymur-pcie-west-anoc"; + reg =3D <0x0 0x016c0000 0x0 0xf580>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; + }; + + pcie_east_anoc: interconnect@16d0000 { + compatible =3D "qcom,glymur-pcie-east-anoc"; + reg =3D <0x0 0x016d0000 0x0 0xf300>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible =3D "qcom,glymur-aggre1-noc"; + reg =3D <0x0 0x016e0000 0x0 0x14400>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + aggre2_noc: interconnect@1720000 { + compatible =3D "qcom,glymur-aggre2-noc"; + reg =3D <0x0 0x01720000 0x0 0x14400>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_2_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + }; + + aggre3_noc: interconnect@1700000 { + compatible =3D "qcom,glymur-aggre3-noc"; + reg =3D <0x0 0x01700000 0x0 0x1d400>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + aggre4_noc: interconnect@1740000 { + compatible =3D "qcom,glymur-aggre4-noc"; + reg =3D <0x0 0x01740000 0x0 0x14400>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; + }; + + mmss_noc: interconnect@1780000 { + compatible =3D "qcom,glymur-mmss-noc"; + reg =3D <0x0 0x01780000 0x0 0x5b800>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + pcie_east_slv_noc: interconnect@1900000 { + compatible =3D "qcom,glymur-pcie-east-slv-noc"; + reg =3D <0x0 0x01900000 0x0 0xe080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + pcie_west_slv_noc: interconnect@1920000 { + compatible =3D "qcom,glymur-pcie-west-slv-noc"; + reg =3D <0x0 0x01920000 0x0 0xf180>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + pcie4: pci@1bf0000 { + device_type =3D "pci"; + compatible =3D "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg =3D <0x0 0x01bf0000 0x0 0x3000>, + <0x0 0x78000000 0x0 0xf20>, + <0x0 0x78000f40 0x0 0xa8>, + <0x0 0x78001000 0x0 0x4000>, + <0x0 0x78005000 0x0 0x100000>, + <0x0 0x01bf3000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>, + <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>, + <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>; + bus-range =3D <0 0xff>; + + dma-coherent; + + linux,pci-domain =3D <4>; + num-lanes =3D <2>; + + operating-points-v2 =3D <&pcie4_opp_table>; + + msi-map =3D <0x0 &gic_its 0xc0000 0x10000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 513 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 514 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 515 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 516 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks =3D <&gcc GCC_PCIE_4_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + resets =3D <&gcc GCC_PCIE_4_BCR>, + <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc GCC_PCIE_4_GDSC>; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55>; + + status =3D "disabled"; + + pcie4_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1969000 1>; + }; + + /* GEN 4 x2 */ + opp-32000000 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <3938000 1>; + }; + + }; + + pcie4_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie4_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie4_phy: phy@1bf6000 { + compatible =3D "qcom,glymur-qmp-gen4x2-pcie-phy"; + reg =3D <0x0 0x01bf6000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE_PHY_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_2_CLKREF_EN>, + <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_4_PIPE_CLK>, + <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets =3D <&gcc GCC_PCIE_4_PHY_BCR>, + <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr"; + + assigned-clocks =3D <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + power-domains =3D <&gcc GCC_PCIE_4_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie4_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + pcie5: pci@1b40000 { + device_type =3D "pci"; + compatible =3D "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg =3D <0x0 0x01b40000 0x0 0x3000>, + <0x0 0x7a000000 0x0 0xf20>, + <0x0 0x7a000f40 0x0 0xa8>, + <0x0 0x7a001000 0x0 0x4000>, + <0x0 0x7a100000 0x0 0x100000>, + <0x0 0x01b43000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x7a200000 0x0 0x100000>, + <0x02000000 0x0 0x7a300000 0x0 0x7a300000 0x0 0x3d00000>, + <0x03000000 0x7 0xa0000000 0x7 0xa0000000 0x0 0x40000000>; + bus-range =3D <0 0xff>; + + dma-coherent; + + linux,pci-domain =3D <5>; + num-lanes =3D <4>; + + operating-points-v2 =3D <&pcie5_opp_table>; + + msi-map =3D <0x0 &gic_its 0xd0000 0x10000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 526 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 428 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 429 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_5_SLV_AXI_CLK>, + <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks =3D <&gcc GCC_PCIE_5_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + resets =3D <&gcc GCC_PCIE_5_BCR>, + <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc GCC_PCIE_5_GDSC>; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55>; + eq-presets-32gts =3D /bits/ 8 <0x55 0x55 0x55 0x55>; + + status =3D "disabled"; + + pcie5_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + }; + + /* GEN 1 x4 and GEN 2 x2 */ + opp-10000000 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + }; + + /* GEN 2 x4 */ + opp-20000000 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <1969000 1>; + }; + + /* GEN 3 x4, GEN 4 x2 and GEN5 x1*/ + opp-32000000 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <3938000 1>; + }; + + /* GEN 4 x4 and GEN 5 x2 */ + opp-64000000 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <7876000 1>; + }; + + /* GEN 5 x4 */ + opp-128000000 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <15753000 1>; + }; + }; + + pcie5_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie5_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie5_phy: phy@1b50000 { + compatible =3D "qcom,glymur-qmp-gen5x4-pcie-phy"; + reg =3D <0x0 0x01b50000 0x0 0x10000>; + + clocks =3D <&gcc GCC_PCIE_PHY_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_5_PIPE_CLK>, + <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets =3D <&gcc GCC_PCIE_5_PHY_BCR>, + <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr"; + + assigned-clocks =3D <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + power-domains =3D <&gcc GCC_PCIE_5_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie5_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + pcie6: pci@1c00000 { + device_type =3D "pci"; + compatible =3D "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg =3D <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x7e000000 0x0 0xf20>, + <0x0 0x7e000f40 0x0 0xa8>, + <0x0 0x7e001000 0x0 0x4000>, + <0x0 0x7e100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, + <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>, + <0x03000000 0x7 0xe0000000 0x7 0xe0000000 0x0 0x20000000>; + bus-range =3D <0 0xff>; + + dma-coherent; + + linux,pci-domain =3D <6>; + num-lanes =3D <2>; + + operating-points-v2 =3D <&pcie6_opp_table>; + + msi-map =3D <0x0 &gic_its 0xe0000 0x10000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 472 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 473 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 474 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 475 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_6_AUX_CLK>, + <&gcc GCC_PCIE_6_CFG_AHB_CLK>, + <&gcc GCC_PCIE_6_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_6_SLV_AXI_CLK>, + <&gcc GCC_PCIE_6_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks =3D <&gcc GCC_PCIE_6_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_west_anoc MASTER_PCIE_6 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_6 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + resets =3D <&gcc GCC_PCIE_6_BCR>, + <&gcc GCC_PCIE_6_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc GCC_PCIE_6_GDSC>; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55>; + + status =3D "disabled"; + + pcie6_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1969000 1>; + }; + + /* GEN 4 x2 */ + opp-32000000 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <3938000 1>; + }; + + }; + + pcie6_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie6_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie6_phy: phy@1c06000 { + compatible =3D "qcom,glymur-qmp-gen4x2-pcie-phy"; + reg =3D <0x0 0x01c06000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE_PHY_6_AUX_CLK>, + <&gcc GCC_PCIE_6_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_4_CLKREF_EN>, + <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_6_PIPE_CLK>, + <&gcc GCC_PCIE_6_PIPE_DIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets =3D <&gcc GCC_PCIE_6_PHY_BCR>, + <&gcc GCC_PCIE_6_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr"; + + assigned-clocks =3D <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + power-domains =3D <&gcc GCC_PCIE_6_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie6_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + pcie3b: pci@1b80000 { + device_type =3D "pci"; + compatible =3D "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg =3D <0x0 0x01b80000 0x0 0x3000>, + <0x0 0x74000000 0x0 0xf20>, + <0x0 0x74000f40 0x0 0xa8>, + <0x0 0x74001000 0x0 0x4000>, + <0x0 0x74100000 0x0 0x100000>, + <0x0 0x01b83000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x74200000 0x0 0x100000>, + <0x02000000 0x0 0x74300000 0x0 0x74300000 0x0 0x3d00000>, + <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; + bus-range =3D <0 0xff>; + + dma-coherent; + + linux,pci-domain =3D <7>; + num-lanes =3D <4>; + + operating-points-v2 =3D <&pcie3b_opp_table>; + + msi-map =3D <0x0 &gic_its 0xf0000 0x10000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 831 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 832 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 833 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 834 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks =3D <&gcc GCC_PCIE_3B_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_west_anoc MASTER_PCIE_3B QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_3B QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + resets =3D <&gcc GCC_PCIE_3B_BCR>, + <&gcc GCC_PCIE_3B_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc GCC_PCIE_3B_GDSC>; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55>; + eq-presets-32gts =3D /bits/ 8 <0x55 0x55 0x55 0x55>; + + status =3D "disabled"; + + pcie3b_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + }; + + /* GEN 1 x4 and GEN 2 x2 */ + opp-10000000 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + }; + + /* GEN 2 x4 */ + opp-20000000 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <1969000 1>; + }; + + /* GEN 3 x4, GEN 4 x2 and GEN5 x1*/ + opp-32000000 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <3938000 1>; + }; + + /* GEN 4 x4 and GEN 5 x2 */ + opp-64000000 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <7876000 1>; + }; + + /* GEN 5 x4 */ + opp-128000000 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <15753000 1>; + }; + }; + + pcie3b_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie3b_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie3b_phy: phy@f10000 { + compatible =3D "qcom,glymur-qmp-gen5x4-pcie-phy"; + reg =3D <0x0 0x00f10000 0x0 0x10000>; + + clocks =3D <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PIPE_CLK>, + <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets =3D <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr"; + + assigned-clocks =3D <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + power-domains =3D <&gcc GCC_PCIE_3B_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie3b_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + + #hwlock-cells =3D <1>; + }; + + tcsr: clock-controller@1fd5000 { + compatible =3D "qcom,glymur-tcsr", + "syscon"; + reg =3D <0x0 0x1fd5000 0x0 0x21000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + hsc_noc: interconnect@2000000 { + compatible =3D "qcom,glymur-hscnoc"; + reg =3D <0x0 0x02000000 0x0 0x93a080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + ipcc: mailbox@3e04000 { + compatible =3D "qcom,glymur-ipcc", "qcom,ipcc"; + reg =3D <0x0 0x03e04000 0x0 0x1000>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + + #mbox-cells =3D <2>; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible =3D "qcom,glymur-lpass-lpiaon-noc"; + reg =3D <0x0 0x07400000 0x0 0x19080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + lpass_lpicx_noc: interconnect@7420000 { + compatible =3D "qcom,glymur-lpass-lpicx-noc"; + reg =3D <0x0 0x07420000 0x0 0x44080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible =3D "qcom,glymur-lpass-ag-noc"; + reg =3D <0x0 0x07e40000 0x0 0xe080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + dispcc: clock-controller@af00000 { + compatible =3D "qcom,glymur-dispcc"; + reg =3D <0x0 0x0af00000 0x0 0x20000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, /* dp0 */ + <0>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>, + <0>, /* dsi0 */ + <0>, + <0>, /* dsi1 */ + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + required-opps =3D <&rpmhpd_opp_turbo>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,glymur-pdc", "qcom,pdc"; + reg =3D <0x0 0x0b220000 0x0 0x10000>; + qcom,pdc-ranges =3D <0 745 51>, + <51 527 47>, + <98 609 32>, + <130 717 12>, + <142 251 5>, + <147 796 16>, + <171 4104 36>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c22c000 { + compatible =3D "qcom,glymur-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22c000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + + #qcom,sensors =3D <13>; + + #thermal-sensor-cells =3D <1>; + }; + + tsens1: thermal-sensor@c22d000 { + compatible =3D "qcom,glymur-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22d000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + + #qcom,sensors =3D <9>; + + #thermal-sensor-cells =3D <1>; + }; + + tsens2: thermal-sensor@c22e000 { + compatible =3D "qcom,glymur-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22e000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + + #qcom,sensors =3D <13>; + + #thermal-sensor-cells =3D <1>; + }; + + tsens3: thermal-sensor@c22f000 { + compatible =3D "qcom,glymur-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22f000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + + #qcom,sensors =3D <8>; + + #thermal-sensor-cells =3D <1>; + }; + + tsens4: thermal-sensor@c230000 { + compatible =3D "qcom,glymur-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c230000 0x0 0x1000>, + <0x0 0x0c226000 0x0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + + #qcom,sensors =3D <13>; + + #thermal-sensor-cells =3D <1>; + }; + + tsens5: thermal-sensor@c231000 { + compatible =3D "qcom,glymur-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c231000 0x0 0x1000>, + <0x0 0x0c227000 0x0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + + #qcom,sensors =3D <8>; + + #thermal-sensor-cells =3D <1>; + }; + + tsens6: thermal-sensor@c232000 { + compatible =3D "qcom,glymur-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c232000 0x0 0x1000>, + <0x0 0x0c228000 0x0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + + #qcom,sensors =3D <13>; + + #thermal-sensor-cells =3D <1>; + }; + + tsens7: thermal-sensor@c233000 { + compatible =3D "qcom,glymur-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c233000 0x0 0x1000>, + <0x0 0x0c229000 0x0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + + #qcom,sensors =3D <15>; + + #thermal-sensor-cells =3D <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible =3D "qcom,glymur-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0x0 0x0c300000 0x0 0x400>; + interrupt-parent =3D <&ipcc>; + interrupts-extended =3D <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_Q= MP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells =3D <0>; + }; + + sram@c30f000 { + compatible =3D "qcom,rpmh-stats"; + reg =3D <0x0 0x0c30f000 0x0 0x400>; + }; + + arbiter@c400000 { + compatible =3D "qcom,glymur-spmi-pmic-arb"; + reg =3D <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c900000 0x0 0x400000>, + <0x0 0x0c4c0000 0x0 0x400000>, + <0x0 0x0c403000 0x0 0x8000>; + reg-names =3D "core", + "chnls", + "obsrvr", + "chnl_map"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + qcom,channel =3D <0>; + qcom,ee =3D <0>; + + spmi_bus0: spmi@c426000 { + reg =3D <0x0 0x0c426000 0x0 0x4000>, + <0x0 0x0c8c0000 0x0 0x10000>, + <0x0 0x0c42a000 0x0 0x8000>; + reg-names =3D "cnfg", + "intr", + "chnl_owner"; + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "periph_irq"; + interrupt-controller; + #interrupt-cells =3D <4>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + spmi_bus1: spmi@c437000 { + reg =3D <0x0 0x0c437000 0x0 0x4000>, + <0x0 0x0c8d0000 0x0 0x10000>, + <0x0 0x0c43b000 0x0 0x8000>; + reg-names =3D "cnfg", + "intr", + "chnl_owner"; + interrupts-extended =3D <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "periph_irq"; + interrupt-controller; + #interrupt-cells =3D <4>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + spmi_bus2: spmi@c48000 { + reg =3D <0x0 0x0c448000 0x0 0x4000>, + <0x0 0x0c8e0000 0x0 0x10000>, + <0x0 0x0c44c000 0x0 0x8000>; + reg-names =3D "cnfg", + "intr", + "chnl_owner"; + interrupts-extended =3D <&pdc 72 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "periph_irq"; + interrupt-controller; + #interrupt-cells =3D <4>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + }; + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,glymur-tlmm"; + reg =3D <0x0 0x0f100000 0x0 0xf00000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 249>; + wakeup-parent =3D <&pdc>; + + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio0", "gpio1"; + function =3D "qup0_se0"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio4", "gpio5"; + function =3D "qup0_se1"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio8", "gpio9"; + function =3D "qup0_se2"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio12", "gpio13"; + function =3D "qup0_se3"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio16", "gpio17"; + function =3D "qup0_se4"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio20", "gpio21"; + function =3D "qup0_se5"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio6", "gpio7"; + function =3D "qup0_se6"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio14", "gpio15"; + function =3D "qup0_se7"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio32", "gpio33"; + function =3D "qup1_se0"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio36", "gpio37"; + function =3D "qup1_se1"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio40", "gpio41"; + function =3D "qup1_se2"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio44", "gpio45"; + function =3D "qup1_se3"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio48", "gpio49"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio52", "gpio53"; + function =3D "qup1_se5"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio56", "gpio57"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio54", "gpio55"; + function =3D "qup1_se7"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c16_data_clk: qup-i2c16-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio64", "gpio65"; + function =3D "qup2_se0"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c17_data_clk: qup-i2c17-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio68", "gpio69"; + function =3D "qup2_se1"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c18_data_clk: qup-i2c18-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio72", "goio73"; + function =3D "qup2_se2"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c19_data_clk: qup-i2c19-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio76", "gpio77"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c20_data_clk: qup-i2c20-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio80", "gpio81"; + function =3D "qup2_se4"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c21_data_clk: qup-i2c21-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio84", "gpio85"; + function =3D "qup2_se5"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c22_data_clk: qup-i2c22-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio88", "gpio89"; + function =3D "qup2_se6"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c23_data_clk: qup-i2c23-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio80", "gpio81"; + function =3D "qup2_se7"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins =3D "gpio3"; + function =3D "qup0_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio0", "gpio1", "gpio2"; + function =3D "qup0_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins =3D "gpio7"; + function =3D "qup0_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio4", "gpio5", "gpio6"; + function =3D "qup0_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins =3D "gpio11"; + function =3D "qup0_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio8", "gpio9", "gpio10"; + function =3D "qup0_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins =3D "gpio15"; + function =3D "qup0_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio12", "gpio13", "gpio14"; + function =3D "qup0_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins =3D "gpio19"; + function =3D "qup0_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio16", "gpio17", "gpio18"; + function =3D "qup0_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins =3D "gpio23"; + function =3D "qup0_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio20", "gpio21", "gpio22"; + function =3D "qup0_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins =3D "gpio5"; + function =3D "qup0_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio6", "gpio7", "gpio4"; + function =3D "qup0_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi7_cs: qup-spi7-cs-state { + pins =3D "gpio13"; + function =3D "qup0_se7"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi7_data_clk: qup-spi7-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio14", "gpio15", "gpio12"; + function =3D "qup0_se7"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins =3D "gpio35"; + function =3D "qup1_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio32", "gpio33", "gpio34"; + function =3D "qup1_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins =3D "gpio39"; + function =3D "qup1_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio36", "gpio37", "gpio38"; + function =3D "qup1_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins =3D "gpio43"; + function =3D "qup1_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio40", "gpio41", "gpio42"; + function =3D "qup1_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins =3D "gpio47"; + function =3D "qup1_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + pins =3D "gpio44", "gpio45", "gpio46"; + function =3D "qup1_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi12_cs: qup-spi12-cs-state { + pins =3D "gpio51"; + function =3D "qup1_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio48", "gpio49", "gpio50"; + function =3D "qup1_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi13_cs: qup-spi13-cs-state { + pins =3D "gpio55"; + function =3D "qup1_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi13_data_clk: qup-spi13-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio52", "gpio53", "gpio54"; + function =3D "qup1_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins =3D "gpio59"; + function =3D "qup1_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio56", "gpio57", "gpio58"; + function =3D "qup1_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins =3D "gpio53"; + function =3D "qup1_se7"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio54", "gpio55", "gpio52"; + function =3D "qup1_se7"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi16_cs: qup-spi16-cs-state { + pins =3D "gpio67"; + function =3D "qup2_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi16_data_clk: qup-spi16-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio64", "gpio65", "gpio66"; + function =3D "qup2_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi17_cs: qup-spi17-cs-state { + pins =3D "gpio71"; + function =3D "qup2_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi17_data_clk: qup-spi17-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio68", "gpio69", "gpio70"; + function =3D "qup2_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi18_cs: qup-spi18-cs-state { + pins =3D "gpio75"; + function =3D "qup2_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi18_data_clk: qup-spi18-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio72", "gpio73", "gpio74"; + function =3D "qup2_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi19_cs: qup-spi19-cs-state { + pins =3D "gpio79"; + function =3D "qup2_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi19_data_clk: qup-spi19-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio76", "gpio77", "gpio78"; + function =3D "qup2_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi20_cs: qup-spi20-cs-state { + pins =3D "gpio83"; + function =3D "qup2_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi20_data_clk: qup-spi20-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio80", "gpio81", "gpio82"; + function =3D "qup2_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi21_cs: qup-spi21-cs-state { + pins =3D "gpio87"; + function =3D "qup2_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi21_data_clk: qup-spi21-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio84", "gpio85", "gpio86"; + function =3D "qup2_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi22_cs: qup-spi22-cs-state { + pins =3D "gpio91"; + function =3D "qup2_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi22_data_clk: qup-spi22-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio88", "gpio89", "gpio90"; + function =3D "qup2_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi23_cs: qup-spi23-cs-state { + pins =3D "gpio83"; + function =3D "qup2_se7"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi23_data_clk: qup-spi23-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio80", "gpio81", "gpio82"; + function =3D "qup2_se7"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart2_default: qup-uart2-default-state { + tx-pins { + pins =3D "gpio10"; + function =3D "qup0_se2"; + drive-strength =3D <2>; + bias-disable; + }; + + rx-pins { + pins =3D "gpio11"; + function =3D "qup0_se2"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_uart14_default: qup-uart14-default-state { + cts-pins { + pins =3D "gpio56"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-disable; + }; + + rts-pins { + pins =3D "gpio57"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-disable; + }; + + tx-pins { + pins =3D "gpio58"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-disable; + }; + + rx-pins { + pins =3D "gpio59"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_uart19_default: qup-uart19-default-state { + cts-pins { + pins =3D "gpio76"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-disable; + }; + + rts-pins { + pins =3D "gpio77"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-disable; + }; + + tx-pins { + pins =3D "gpio78"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-disable; + }; + + rx-pins { + pins =3D "gpio79"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_uart21_default: qup-uart21-default-state { + tx-pins { + pins =3D "gpio86"; + function =3D "qup2_se5"; + drive-strength =3D <2>; + bias-disable; + }; + + rx-pins { + pins =3D "gpio87"; + function =3D "qup2_se5"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + qup_uart22_default: qup-uart22-default-state { + tx-pins { + pins =3D "gpio90"; + function =3D "qup2_se6"; + drive-strength =3D <2>; + bias-disable; + }; + + rx-pins { + pins =3D "gpio91"; + function =3D "qup2_se6"; + drive-strength =3D <2>; + bias-disable; + }; + }; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,glymur-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg =3D <0x0 0x15000000 0x0 0x100000>; + + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + dma-coherent; + }; + + intc: interrupt-controller@17000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17000000 0x0 0x10000>, + <0x0 0x17080000 0x0 0x480000>; + + interrupts =3D ; + + #interrupt-cells =3D <3>; + interrupt-controller; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic_its: gic-its@17040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x17040000 0x0 0x40000>; + + msi-controller; + #msi-cells =3D <1>; + }; + }; + + watchdog@17600000 { + compatible =3D "qcom,kpss-wdt"; + reg =3D <0x0 0x17600000 0x0 0x1000>; + clocks =3D <&sleep_clk>; + interrupts =3D ; + }; + + pdp0_mbox: mailbox@17610000 { + compatible =3D "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg =3D <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; + interrupts =3D ; + #mbox-cells =3D <1>; + }; + + timer@17810000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17810000 0x0 0x1000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + frame@17811000 { + reg =3D <0x0 0x17811000 0x0 0x1000>, + <0x0 0x17812000 0x0 0x1000>; + + interrupts =3D , + ; + + frame-number =3D <0>; + }; + + frame@17813000 { + reg =3D <0x0 0x17813000 0x0 0x1000>; + + interrupts =3D ; + + frame-number =3D <1>; + + status =3D "disabled"; + }; + + frame@17815000 { + reg =3D <0x0 0x17815000 0x0 0x1000>; + + interrupts =3D ; + + frame-number =3D <2>; + + status =3D "disabled"; + }; + + frame@17817000 { + reg =3D <0x0 0x17817000 0x0 0x1000>; + + interrupts =3D ; + + frame-number =3D <3>; + + status =3D "disabled"; + }; + + frame@17819000 { + reg =3D <0x0 0x17819000 0x0 0x1000>; + + interrupts =3D ; + + frame-number =3D <4>; + + status =3D "disabled"; + }; + + frame@1781b000 { + reg =3D <0x0 0x1781b000 0x0 0x1000>; + + interrupts =3D ; + + frame-number =3D <5>; + + status =3D "disabled"; + }; + + frame@1781d000 { + reg =3D <0x0 0x1781d000 0x0 0x1000>; + + interrupts =3D ; + + frame-number =3D <6>; + + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@18900000 { + compatible =3D "qcom,rpmh-rsc"; + label =3D "apps_rsc"; + reg =3D <0x0 0x18900000 0x0 0x10000>, + <0x0 0x18910000 0x0 0x10000>, + <0x0 0x18920000 0x0 0x10000>; + reg-names =3D "drv-0", + "drv-1", + "drv-2"; + interrupts =3D , + , + ; + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , + , + , + ; + power-domains =3D <&system_pd>; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,glymur-rpmh-clk"; + + clocks =3D <&xo_board>; + clock-names =3D "xo"; + + #clock-cells =3D <1>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,glymur-rpmhpd"; + + operating-points-v2 =3D <&rpmhpd_opp_table>; + + #power-domain-cells =3D <1>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp-48 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l0: opp-144 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level =3D ; + }; + }; + }; + }; + + nsi_noc: interconnect@1d600000 { + compatible =3D "qcom,glymur-nsinoc"; + reg =3D <0x0 0x1d600000 0x0 0x14080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + oobm_ss_noc: interconnect@1f300000 { + compatible =3D "qcom,glymur-oobm-ss-noc"; + reg =3D <0x0 0x1f300000 0x0 0x49a00>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + system-cache-controller@20400000 { + compatible =3D "qcom,glymur-llcc"; + reg =3D <0x0 0x21800000 0x0 0x100000>, + <0x0 0x21a00000 0x0 0x100000>, + <0x0 0x21c00000 0x0 0x100000>, + <0x0 0x21e00000 0x0 0x100000>, + <0x0 0x22800000 0x0 0x100000>, + <0x0 0x22a00000 0x0 0x100000>, + <0x0 0x22c00000 0x0 0x100000>, + <0x0 0x22e00000 0x0 0x100000>, + <0x0 0x23800000 0x0 0x100000>, + <0x0 0x23a00000 0x0 0x100000>, + <0x0 0x23c00000 0x0 0x100000>, + <0x0 0x23e00000 0x0 0x100000>, + <0x0 0x20400000 0x0 0x100000>, + <0x0 0x20600000 0x0 0x100000>; + + reg-names =3D "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc4_base", + "llcc5_base", + "llcc6_base", + "llcc7_base", + "llcc8_base", + "llcc9_base", + "llcc10_base", + "llcc11_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; + + interrupts =3D ; + }; + + nsp_noc: interconnect@320c0000 { + compatible =3D "qcom,glymur-nsp-noc"; + reg =3D <0x0 0x320c0000 0x0 0x21280>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + imem: sram@81e08000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x81e08600 0x0 0x300>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x81e08600 0x300>; + + cpu_scp_lpri0: scp-sram-section@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x180>; + }; + + cpu_scp_lpri1: scp-sram-section@180 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x180 0x180>; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + }; + + thermal_zones: thermal-zones { + aoss-0-thermal { + thermal-sensors =3D <&tsens0 0>; + + trips { + aoss-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-0-0-thermal { + thermal-sensors =3D <&tsens0 1>; + + trips { + cpu-0-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-0-1-thermal { + thermal-sensors =3D <&tsens0 2>; + + trips { + cpu-0-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-1-0-thermal { + thermal-sensors =3D <&tsens0 3>; + + trips { + cpu-0-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-1-1-thermal { + thermal-sensors =3D <&tsens0 4>; + + trips { + cpu-0-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-2-0-thermal { + thermal-sensors =3D <&tsens0 5>; + + trips { + cpu-0-2-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-2-1-thermal { + thermal-sensors =3D <&tsens0 6>; + + trips { + cpu-0-2-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-3-0-thermal { + thermal-sensors =3D <&tsens0 7>; + + trips { + cpu-0-3-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-3-1-thermal { + thermal-sensors =3D <&tsens0 8>; + + trips { + cpu-0-3-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-4-0-thermal { + thermal-sensors =3D <&tsens0 9>; + + trips { + cpu-0-4-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-4-1-thermal { + thermal-sensors =3D <&tsens0 10>; + + trips { + cpu-0-4-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-5-0-thermal { + thermal-sensors =3D <&tsens0 11>; + + trips { + cpu-0-5-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-5-1-thermal { + thermal-sensors =3D <&tsens0 12>; + + trips { + cpu-0-5-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-1-thermal { + thermal-sensors =3D <&tsens1 0>; + + trips { + aoss-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpullc-0-0-thermal { + thermal-sensors =3D <&tsens1 1>; + + trips { + cpullc-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpullc-0-1-thermal { + thermal-sensors =3D <&tsens1 2>; + + trips { + cpullc-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-0-0-thermal { + thermal-sensors =3D <&tsens1 3>; + + trips { + qmx-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-0-1-thermal { + thermal-sensors =3D <&tsens1 4>; + + trips { + qmx-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-0-2-thermal { + thermal-sensors =3D <&tsens1 5>; + + trips { + qmx-0-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + ddr-0-thermal { + thermal-sensors =3D <&tsens1 6>; + + trips { + ddr-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + video-0-thermal { + thermal-sensors =3D <&tsens1 7>; + + trips { + video-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + video-1-thermal { + thermal-sensors =3D <&tsens1 8>; + + trips { + video-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-2-thermal { + thermal-sensors =3D <&tsens2 0>; + + trips { + aoss-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-0-0-thermal { + thermal-sensors =3D <&tsens2 1>; + + trips { + cpu-1-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-0-1-thermal { + thermal-sensors =3D <&tsens2 2>; + + trips { + cpu-1-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-1-0-thermal { + thermal-sensors =3D <&tsens2 3>; + + trips { + cpu-1-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-1-1-thermal { + thermal-sensors =3D <&tsens2 4>; + + trips { + cpu-1-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-2-0-thermal { + thermal-sensors =3D <&tsens2 5>; + + trips { + cpu-1-2-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-2-1-thermal { + thermal-sensors =3D <&tsens2 6>; + + trips { + cpu-1-2-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-3-0-thermal { + thermal-sensors =3D <&tsens2 7>; + + trips { + cpu-1-3-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-3-1-thermal { + thermal-sensors =3D <&tsens2 8>; + + trips { + cpu-1-3-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-4-0-thermal { + thermal-sensors =3D <&tsens2 9>; + + trips { + cpu-1-4-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-4-1-thermal { + thermal-sensors =3D <&tsens2 10>; + + trips { + cpu-1-4-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-5-0-thermal { + thermal-sensors =3D <&tsens2 11>; + + trips { + cpu-1-5-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-5-1-thermal { + thermal-sensors =3D <&tsens2 12>; + + trips { + cpu-1-5-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-3-thermal { + thermal-sensors =3D <&tsens3 0>; + + trips { + aoss-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpullc-1-0-thermal { + thermal-sensors =3D <&tsens3 1>; + + trips { + cpullc-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpullc-1-1-thermal { + thermal-sensors =3D <&tsens3 2>; + + trips { + cpullc-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-0-thermal { + thermal-sensors =3D <&tsens3 3>; + + trips { + qmx-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-1-thermal { + thermal-sensors =3D <&tsens3 4>; + + trips { + qmx-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-2-thermal { + thermal-sensors =3D <&tsens3 5>; + + trips { + qmx-1-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-3-thermal { + thermal-sensors =3D <&tsens3 6>; + + trips { + qmx-1-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-4-thermal { + thermal-sensors =3D <&tsens3 7>; + + trips { + qmx-1-4-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-4-thermal { + thermal-sensors =3D <&tsens4 0>; + + trips { + aoss-4-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-2-0-0-thermal { + thermal-sensors =3D <&tsens4 1>; + + trips { + cpu-2-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-2-0-1-thermal { + thermal-sensors =3D <&tsens4 2>; + + trips { + cpu-2-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-2-1-0-thermal { + thermal-sensors =3D <&tsens4 3>; + + trips { + cpu-2-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-2-1-1-thermal { + thermal-sensors =3D <&tsens4 4>; + + trips { + cpu-2-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-2-2-0-thermal { + thermal-sensors =3D <&tsens4 5>; + + trips { + cpu-2-2-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-2-2-1-thermal { + thermal-sensors =3D <&tsens4 6>; + + trips { + cpu-2-2-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-2-3-0-thermal { + thermal-sensors =3D <&tsens4 7>; + + trips { + cpu-2-3-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-2-3-1-thermal { + thermal-sensors =3D <&tsens4 8>; + + trips { + cpu-2-3-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-2-4-0-thermal { + thermal-sensors =3D <&tsens4 9>; + + trips { + cpu-2-4-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-2-4-1-thermal { + thermal-sensors =3D <&tsens4 10>; + + trips { + cpu-2-4-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-2-5-0-thermal { + thermal-sensors =3D <&tsens4 11>; + + trips { + cpu-2-5-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-2-5-1-thermal { + thermal-sensors =3D <&tsens4 12>; + + trips { + cpu-2-5-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-5-thermal { + thermal-sensors =3D <&tsens5 0>; + + trips { + aoss-5-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpullc-2-0-thermal { + thermal-sensors =3D <&tsens5 1>; + + trips { + cpullc-2-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpuillc-2-1-thermal { + thermal-sensors =3D <&tsens5 2>; + + trips { + cpullc-2-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-2-0-thermal { + thermal-sensors =3D <&tsens5 3>; + + trips { + qmx-2-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-2-1-thermal { + thermal-sensors =3D <&tsens5 4>; + + trips { + qmx-2-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-2-2-thermal { + thermal-sensors =3D <&tsens5 5>; + + trips { + qmx-2-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-2-3-thermal { + thermal-sensors =3D <&tsens5 6>; + + trips { + qmx-2-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-2-4-thermal { + thermal-sensors =3D <&tsens5 7>; + + trips { + qmx-2-4-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-6-thermal { + thermal-sensors =3D <&tsens6 0>; + + trips { + aoss-6-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphvx-0-thermal { + thermal-sensors =3D <&tsens6 1>; + + trips { + nsphvx-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphvx-1-thermal { + thermal-sensors =3D <&tsens6 2>; + + trips { + nsphvx-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphvx-2-thermal { + thermal-sensors =3D <&tsens6 3>; + + trips { + nsphvx-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphvx-3-thermal { + thermal-sensors =3D <&tsens6 4>; + + trips { + nsphvx-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphmx-0-thermal { + thermal-sensors =3D <&tsens6 5>; + + trips { + nsphmx-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphmx-1-thermal { + thermal-sensors =3D <&tsens6 6>; + + trips { + nsphmx-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphmx-2-thermal { + thermal-sensors =3D <&tsens6 7>; + + trips { + nsphmx-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphmx-3-thermal { + thermal-sensors =3D <&tsens6 8>; + + trips { + nsphmx-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + camera-0-thermal { + thermal-sensors =3D <&tsens6 9>; + + trips { + camera-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + camera-1-thermal { + thermal-sensors =3D <&tsens6 10>; + + trips { + camera-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + ddr-1-thermal { + thermal-sensors =3D <&tsens6 11>; + + trips { + ddr-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + ddr-2-thermal { + thermal-sensors =3D <&tsens6 12>; + + trips { + ddr-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-7-thermal { + thermal-sensors =3D <&tsens7 0>; + + trips { + aoss-7-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-0-0-thermal { + thermal-sensors =3D <&tsens7 1>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-0-1-thermal { + thermal-sensors =3D <&tsens7 2>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-0-2-thermal { + thermal-sensors =3D <&tsens7 3>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-0-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-1-0-thermal { + thermal-sensors =3D <&tsens7 4>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-1-1-thermal { + thermal-sensors =3D <&tsens7 5>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-1-2-thermal { + thermal-sensors =3D <&tsens7 6>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-1-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-2-0-thermal { + thermal-sensors =3D <&tsens7 7>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-2-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-2-1-thermal { + thermal-sensors =3D <&tsens7 8>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-2-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-2-2-thermal { + thermal-sensors =3D <&tsens7 9>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-2-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-3-0-thermal { + thermal-sensors =3D <&tsens7 10>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-3-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-3-1-thermal { + thermal-sensors =3D <&tsens7 11>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-3-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-3-2-thermal { + thermal-sensors =3D <&tsens7 12>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-3-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-0-thermal { + thermal-sensors =3D <&tsens7 13>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-1-thermal { + thermal-sensors =3D <&tsens7 14>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi b/arch/arm64/boot/dts/q= com/pmcx0102.dtsi new file mode 100644 index 000000000000..c3256a5caca8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +&spmi_bus0 { + pmcx0102_c_e0: pmic@2 { + compatible =3D "qcom,pmcx0102", "qcom,spmi-pmic"; + reg =3D <0x2 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmcx0102_c_e0_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmcx0102_c_e0_gpios: gpio@8800 { + compatible =3D "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmcx0102_c_e0_gpios 0 0 14>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmcx0102_d_e0: pmic@3 { + compatible =3D "qcom,pmcx0102", "qcom,spmi-pmic"; + reg =3D <0x3 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmcx0102_d_e0_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmcx0102_d_e0_gpios: gpio@8800 { + compatible =3D "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmcx0102_d_e0_gpios 0 0 14>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmcx0102_e_e0: pmic@4 { + compatible =3D "qcom,pmcx0102", "qcom,spmi-pmic"; + reg =3D <0x4 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmcx0102_e_e0_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmcx0102_e_e0_gpios: gpio@8800 { + compatible =3D "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmcx0102_e_e0_gpios 0 0 14>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + +}; + +&spmi_bus1 { + pmcx0102_c_e1: pmic@2 { + compatible =3D "qcom,pmcx0102", "qcom,spmi-pmic"; + reg =3D <0x2 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmcx0102_c_e1_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmcx0102_c_e1_gpios: gpio@8800 { + compatible =3D "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmcx0102_c_e1_gpios 0 0 14>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmcx0102_d_e1: pmic@3 { + compatible =3D "qcom,pmcx0102", "qcom,spmi-pmic"; + reg =3D <0x3 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmcx0102_d_e1_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmcx0102_d_e1_gpios: gpio@8800 { + compatible =3D "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmcx0102_d_e1_gpios 0 0 14>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0101.dtsi b/arch/arm64/boot/dts/qc= om/pmh0101.dtsi new file mode 100644 index 000000000000..831c79305f7a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0101.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +&spmi_bus0 { + pmic@1 { + compatible =3D "qcom,pmh0101", "qcom,spmi-pmic"; + reg =3D <0x1 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmh0101_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmh0101_gpios: gpio@8800 { + compatible =3D "qcom,pmh0101-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmh0101_gpios 0 0 18>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + pmh0101_flash: led-controller@ee00 { + compatible =3D "qcom,pmh0101-flash-led", "qcom,spmi-flash-led"; + reg =3D <0xee00>; + status =3D "disabled"; + }; + + pmh0101_pwm: pwm { + compatible =3D "qcom,pmh0101-pwm", "qcom,pm8350c-pwm"; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot= /dts/qcom/pmh0104-glymur.dtsi new file mode 100644 index 000000000000..6a68d71cc0cf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +&spmi_bus0 { + pmh0104_i_e0: pmic@8 { + compatible =3D "qcom,pmh0104", "qcom,spmi-pmic"; + reg =3D <0x8 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmh0104_i_e0_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmh0104_i_e0_gpios: gpio@8800 { + compatible =3D "qcom,pmh0104-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmh0104_i_e0_gpios 0 0 8>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmh0104_j_e0: pmic@9 { + compatible =3D "qcom,pmh0104", "qcom,spmi-pmic"; + reg =3D <0x9 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmh0104_j_e0_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmh0104_j_e0_gpios: gpio@8800 { + compatible =3D "qcom,pmh0104-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmh0104_j_e0_gpios 0 0 8>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; + +&spmi_bus1 { + pmh0104_l_e1: pmic@b { + compatible =3D "qcom,pmh0104", "qcom,spmi-pmic"; + reg =3D <0xb SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmh0104_l_e1_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0xb 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmh0104_l_e1_gpios: gpio@8800 { + compatible =3D "qcom,pmh0104-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmh0104_l_e1_gpios 0 0 8>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi b/arch/arm64/boot= /dts/qcom/pmh0110-glymur.dtsi new file mode 100644 index 000000000000..c950d717061b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +&spmi_bus0 { + pmh0110_f_e0: pmic@5 { + compatible =3D "qcom,pmh0110", "qcom,spmi-pmic"; + reg =3D <0x5 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmh0110_f_e0_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmh0110_f_e0_gpios: gpio@8800 { + compatible =3D "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmh0110_f_e0_gpios 0 0 14>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmh0110_h_e0: pmic@7 { + compatible =3D "qcom,pmh0110", "qcom,spmi-pmic"; + reg =3D <0x7 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmh0110_h_e0_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmh0110_h_e0_gpios: gpio@8800 { + compatible =3D "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmh0110_h_e0_gpios 0 0 14>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; + +&spmi_bus1 { + pmh0110_f_e1: pmic@5 { + compatible =3D "qcom,pmh0110", "qcom,spmi-pmic"; + reg =3D <0x5 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmh0110_f_e1_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells =3D <0>; + }; + + pmh0110_f_e1_gpios: gpio@8800 { + compatible =3D "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmh0110_f_e1_gpios 0 0 14>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmk8850.dtsi b/arch/arm64/boot/dts/qc= om/pmk8850.dtsi new file mode 100644 index 000000000000..c7ba72fd48bc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmk8850.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +&spmi_bus0 { + pmic@0 { + compatible =3D "qcom,pmk8850", "qcom,spmi-pmic"; + reg =3D <0x0 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmk8850_pon: pon@1300 { + compatible =3D "qcom,pmk8350-pon"; + reg =3D <0x1300>, + <0x800>; + reg-names =3D "hlos", + "pbs"; + + pon_pwrkey: pwrkey { + compatible =3D "qcom,pmk8350-pwrkey"; + interrupts =3D <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code =3D ; + }; + + pon_resin: resin { + compatible =3D "qcom,pmk8350-resin"; + interrupts =3D <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + status =3D "disabled"; + }; + }; + + pmk8850_gpios: gpio@b800 { + compatible =3D "qcom,pmk8850-gpio", "qcom,spmi-gpio"; + reg =3D <0xb800>; + gpio-controller; + gpio-ranges =3D <&pmk8850_gpios 0 0 8>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + pmk8850_rtc: rtc@6100 { + compatible =3D "qcom,pmk8350-rtc"; + reg =3D <0x6100>, + <0x6200>; + reg-names =3D "rtc", + "alarm"; + interrupts =3D <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pmk8850_sdam_2: nvram@7100 { + compatible =3D "qcom,spmi-sdam"; + reg =3D <0x7100>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x7100 0x100>; + + reboot_reason: reboot-reason@48 { + reg =3D <0x48 0x1>; + bits =3D <1 7>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/smb2370.dtsi b/arch/arm64/boot/dts/qc= om/smb2370.dtsi new file mode 100644 index 000000000000..80f3fdae5705 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/smb2370.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +&spmi_bus2 { + smb2370_j_e2: pmic@9 { + compatible =3D "qcom,smb2370", "qcom,spmi-pmic"; + reg =3D <0x9 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + smb2370_j_e2_eusb2_repeater: phy@fd00 { + compatible =3D "qcom,smb2370-eusb2-repeater"; + reg =3D <0xfd00>; + #phy-cells =3D <0>; + }; + }; + + smb2370_k_e2: pmic@a { + compatible =3D "qcom,smb2370", "qcom,spmi-pmic"; + reg =3D <0xa SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + smb2370_k_e2_eusb2_repeater: phy@fd00 { + compatible =3D "qcom,smb2370-eusb2-repeater"; + reg =3D <0xfd00>; + #phy-cells =3D <0>; + }; + }; + + smb2370_l_e2: pmic@b { + compatible =3D "qcom,smb2370", "qcom,spmi-pmic"; + reg =3D <0xb SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + smb2370_l_e2_eusb2_repeater: phy@fd00 { + compatible =3D "qcom,smb2370-eusb2-repeater"; + reg =3D <0xfd00>; + #phy-cells =3D <0>; + }; + }; +}; --=20 2.34.1 From nobody Mon Feb 9 04:02:49 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C345E337BB5 for ; Fri, 19 Dec 2025 14:47:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766155671; cv=none; b=mPL/g07fYzR2ed+RUPvSeGXP4RIlrM2HLRzZuKI+yOkY3Or5DnxLT69H42n3rIRmNHb7vFL5lED0IXIZwFzJ0qWQuntne/OoTE1dZlXKI/VhqukKeEkJ6Foko0y+kctRr5o97R0CsPIVJ1dvjrpha6IJN1xft/1UHcninHnORfQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766155671; c=relaxed/simple; bh=+v6epbEJ9lGIKWS/C4CAv+mgesmOySMOExkX9nSiO0k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pU7JaGeS9LKbeZ4rb5ELDaOVUe/PGsVK3+f7ovMwUDaSGi5j0Lpi+HKPQQMxZAO0spXWcOmHNJJgf31C9IaTP0FBltoOkPFN2sPjuusq6OHsjwN3fMU8inUUBHj7GKve2gK0pfkq0z/4tAYpYac57LGJFVhSB+W7v9sVQFjm5sU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=baLn9UFX; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=gvjOxM6V; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="baLn9UFX"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="gvjOxM6V" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJBBInL4102694 for ; Fri, 19 Dec 2025 14:47:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= C6bZcGlQ11MXnBi6clTrulclc54PhSecTf/GBKLuogw=; b=baLn9UFXo4OlV9FV Tpm8ofwyP9HNb5LiMhlY2gIQ9jiHjZT3mQAGcP33FbuaGLD8xJiARgA0VjOxaGoX D0fjS506rL65N3pHGT6m0X0VyUMsMQ34LulX7efpNwibT0auqrC9McuZGz+OIOGz YKlxeYxdZIwlX2+MNv94H54tEG5ypFY8C+qzcBwNdCeYhEvV6/Zbnrq5nAlYs11L jRDUjQf8v0Box40ytTK92+qDHxhhnuJFnSJQ1XHr5Z5pHDcsSAY+Oc2Av4GSVqw8 3fub6HF7lvisUtFnqG9j5EzrMJFRvkAANQgUSCZ+iV2IgBuW8gD5QJP8pzyEmxTt keI+bQ== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r2c2yy4-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 14:47:47 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-29f8e6a5de4so25217915ad.2 for ; Fri, 19 Dec 2025 06:47:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766155667; x=1766760467; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=C6bZcGlQ11MXnBi6clTrulclc54PhSecTf/GBKLuogw=; b=gvjOxM6VTy0bWlBRjRoNmEKln/9b5LCyTtYpCM/wMvQYBz99TbyrrMY5t924A/5YoT JPRK1b/mp9rMPy0HufgUdy3C+TLyG4KbbpE2Woqe2qgaO7ndrlIEg67fCX4E8H5ysGA6 ZxMJc/0CnWrJahyPSb3aH6Z+MqLovkNEdZ23mJQ2cGNsmdvYYNfHT2U/MaAxA8ry2k6Y kMVNGkwmOLEgBsv4Qqefg9E6307O2E53qCmZwOykPS06XHy9GtrX4pJckThYv0mwoQ0x jXb55VLmjYTuAib+wn1SKso7Hgq/YCSR70u2JeVsnkTaDWfD+crkXysml57tVmivm8Kc zMVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766155667; x=1766760467; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=C6bZcGlQ11MXnBi6clTrulclc54PhSecTf/GBKLuogw=; b=GojK20yQl9C9SJnPSguzX8haPboS+zbo7V8T3d1QCQsWNGT0It8bvKk/JG6us5KlY9 wzxAELqdSvwx2Tc+GG1pNIXm3JT+F39MyvgtoMzt4kf+Lco0fyb9/GIiElTf08CbmFxH q/523Hh+v5ydT9KKHIcy8H05WsI1pSUyshbl5RtTT3oJOf7YN1eUjDM5rr9s2c7GORyY weqOuWV1ydDnHj+GvoTCr8tPOVqRdZkyD7vZQzOOgGCzkJDJRRn0tKBv/Lv6RA9TNrz7 RTkhLkNwaAeDXwdOdyU55yXOwzkJBAHaTudsQue0BybTYevG8LTR3Zpx9xmk23npMMcq tm1A== X-Forwarded-Encrypted: i=1; AJvYcCVzdIqccb0mWi/K/wRKwwd5uqrSxL2vsW1+4eB3gk4geOeQNNXFVVbliQHDBhieZHshoJRiyhWW0Csw+y4=@vger.kernel.org X-Gm-Message-State: AOJu0Yw44dKK+J1NafHvWyLPm3UntVWgOX70x5TfS+GGSG/tiwSnXFUF VzY6RJi1Mf++xv6TBw2ljyESd1tHGpmDIV8igJIhp45e8aq7JSpnsDEq9Dfj41mV4N2U8CgW2wS WxwqnTzdv28+lHQpDAQeW+wDUi/wXqXzm3ct+9WJKmIX9ykOvP47Z6tEEjsxFvi43FM4= X-Gm-Gg: AY/fxX5fuqE0Cp0uE2hJt5UFWBbs5OQpgi5RUALAgSvZRXbPA7B7hBw+o9jbtdaEv5y G9vjxXehZ57UHvrd758vDJyecTHTVHkp4LR5fegyu10rPsxAc0plQmQ1qVnwNvzFQyc3wQ7HeTw s0s0eaxROTx0N2GwYlOYYAB2brNSslSvp2I5y6WJsMKiowrov5g2oE6nhXfNz72DF6tK7nbUaJI VMP5xcw0WwVeII8DrTSJlNdCDy5C3Tjd27wTBIMSEHzWRgJy1q/kLtiQN1IyF23ePSPkB7cW4Rk Xy6WNSjBvDaO/oa2xNN2szPaif1+4JeSgT+yW9Ds5KKVa37F9mjT/oLkKPBZ9HtFHJ0IrBv8sLJ kxhmwUSKUw/Srub1FRapAtnTzFg/F0r1ypRlcL/TslMy26uA9ddxMyQZDUTk49U939NXPuN70FM 9Z2G4OXqcPdcZ0BJEiPlp5MeemOwra4A== X-Received: by 2002:a17:902:f64a:b0:2a0:c5b8:24b0 with SMTP id d9443c01a7336-2a2f2a34fedmr40542625ad.46.1766155666768; Fri, 19 Dec 2025 06:47:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IELUpr3B1JT5EdJFofw18XNapzYotJHnYxFGOrY99hUP5lr1IVp8EanEsg3tDzWl/Vq+EXIBg== X-Received: by 2002:a17:902:f64a:b0:2a0:c5b8:24b0 with SMTP id d9443c01a7336-2a2f2a34fedmr40542325ad.46.1766155666235; Fri, 19 Dec 2025 06:47:46 -0800 (PST) Received: from hu-pankpati-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3c8286esm25433855ad.33.2025.12.19.06.47.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 06:47:45 -0800 (PST) From: Pankaj Patil Date: Fri, 19 Dec 2025 20:16:57 +0530 Subject: [PATCH v3 4/4] arm64: dts: qcom: glymur: Enable Glymur CRD board support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-upstream_v3_glymur_introduction-v3-4-32271f1f685d@oss.qualcomm.com> References: <20251219-upstream_v3_glymur_introduction-v3-0-32271f1f685d@oss.qualcomm.com> In-Reply-To: <20251219-upstream_v3_glymur_introduction-v3-0-32271f1f685d@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pankaj Patil , rajendra.nayak@oss.qualcomm.com, sibi.sankar@oss.qualcomm.com, Kamal Wadhwa , Qiang Yu , Jyothi Kumar Seerapu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766155644; l=21566; i=pankaj.patil@oss.qualcomm.com; s=20251121; h=from:subject:message-id; bh=+v6epbEJ9lGIKWS/C4CAv+mgesmOySMOExkX9nSiO0k=; b=1ETc319OEXunmeNGqpOOFVg8X6AblRpjFCKFAWAxBl5AgFlmZklW4hqA5mK2PndLmTX4xDWFf m2vDBP+ditqD6voOxMbnX9pgmz2ZzSiF4uk49wCV0NZKw8S77XBTGEd X-Developer-Key: i=pankaj.patil@oss.qualcomm.com; a=ed25519; pk=pWpEq/tlX6TaKH1UQolvxjRD+Vdib/sEkb8bH8AL6gc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDEyNCBTYWx0ZWRfX65ILJImbDYT0 y4cixUlI3GrgbqjP+5GH2/DG6TSPygwbzD7gURHnYdvhf+2/GhPW3EpKXoOpVLKhsQPh+tzmcmy hXg0oJJX5ohHxeVsm32maZz1LzTsD7iFLk+SQO3uRqX7Ol4/HzXUBVayFjnXmu8VlfwF70B422d r/z9/xrO9X0Wj2YIJ9Bn+/5X4PpBijQ8+ITNkH3O9kWe/r3gxXuhfWoIZDhZX9nDJ+4+dLCkBYF vhRJw02c8eM4jtHVgZIVUvheo0yKOnLubyR2Q4aQAaFHUmFtI0A3zLlPQR8owO0+1XslJJKsnik YSQtCeEMFV9xAc4LnqpFR58MxWlRT1EgcLbVm4CgsP0phBIWNBBrTIYaFCwp0ZpcM6PEIyVu3UE z2cESwIOHYyZO20Gx8tZ6PrFW9LoEltuIluIWBMaSWKt1yUq3aiLS2VWaWkZ94kfpIGpPNo0NgI X+nnpSydoK9ekXF1Yjg== X-Authority-Analysis: v=2.4 cv=dOmrWeZb c=1 sm=1 tr=0 ts=69456593 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=Sr3Z2WK-enE8fikEQukA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: SC_9ZN7TSLsZWAPdA1r3qf8zK34kGEYY X-Proofpoint-GUID: SC_9ZN7TSLsZWAPdA1r3qf8zK34kGEYY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_05,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 clxscore=1011 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190124 Add initial device tree support for the Glymur Compute Reference Device(CRD) board, with this board dts glymur crd can boot to shell with rootfs on nvme and uart21 as serial console Features enabled are: - Regulators 0 - 4 - Power supplies and sideband signals (PERST, WAKE, CLKREQ) for PCIe3b/4/5/6 controllers and PHYs - QUPv3 instances - PMIC thermal-zone updates Co-developed-by: Kamal Wadhwa Signed-off-by: Kamal Wadhwa Co-developed-by: Qiang Yu Signed-off-by: Qiang Yu Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Co-developed-by: Jyothi Kumar Seerapu Signed-off-by: Jyothi Kumar Seerapu Signed-off-by: Pankaj Patil Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/glymur-crd.dts | 860 ++++++++++++++++++++++++++++= ++++ 2 files changed, 861 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 6f34d5ed331c..6ff911cca06c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D glymur-crd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D hamoa-iot-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-tplink-archer-ax55-v1.dtb diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts new file mode 100644 index 000000000000..7c168e813f1e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -0,0 +1,860 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "glymur.dtsi" +#include "glymur-pmics.dtsi" +#include + +/ { + model =3D "Qualcomm Technologies, Inc. Glymur CRD"; + compatible =3D "qcom,glymur-crd", "qcom,glymur"; + + aliases { + serial0 =3D &uart21; + serial1 =3D &uart14; + i2c0 =3D &i2c0; + i2c1 =3D &i2c4; + i2c2 =3D &i2c5; + spi0 =3D &spi18; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + #clock-cells =3D <0>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&key_vol_up_default>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + linux,can-disable; + wakeup-source; + }; + }; + + vreg_nvme: regulator-nvme { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_NVME_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&nvme_reg_en>; + pinctrl-names =3D "default"; + }; + + vreg_nvme_sec: regulator-nvme-sec { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_NVME_SEC_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&nvme_sec_reg_en>; + pinctrl-names =3D "default"; + }; + + vreg_wlan: regulator-wlan { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WLAN_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 94 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wlan_reg_en>; + }; + + vreg_wwan: regulator-wwan { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WWAN_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 246 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wwan_reg_en>; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + }; + + thermal-zones { + pmh0101-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmh0101_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pmcx0102-c0-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmcx0102_c_e0_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pmcx0102-d0-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmcx0102_d_e0_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pmcx0102-c1-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmcx0102_c_e1_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pmcx0102-d1-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmcx0102_d_e1_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pmh0110-f0-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmh0110_f_e0_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pmh0110-h0-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmh0110_h_e0_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pmh0110-f1-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmh0110_f_e1_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pmh0104-i0-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmh0104_i_e0_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pmh0104-j0-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmh0104_j_e0_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + + pmh0104-l1-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pmh0104_l_e1_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + }; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges =3D <4 4>, /* EC TZ Secure I3C */ + <10 2>, /* OOB UART */ + <44 4>; /* Security SPI (TPM) */ + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins =3D "gpio147"; + function =3D "pcie4_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio146"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio148"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins =3D "gpio153"; + function =3D "pcie5_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio152"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio154"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie6_default: pcie6-default-state { + clkreq-n-pins { + pins =3D "gpio150"; + function =3D "pcie6_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio149"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio151"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie3b_default: pcie3b-default-state { + clkreq-n-pins { + pins =3D "gpio156"; + function =3D "pcie3b_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio155"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio157"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + wlan_reg_en: wlan-reg-en-state { + pins =3D "gpio94"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wwan_reg_en: wwan-reg-en-state { + pins =3D "gpio246"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; +}; + +&pmh0101_gpios { + key_vol_up_default: key-vol-up-default-state { + pins =3D "gpio6"; + function =3D "normal"; + output-disable; + bias-pull-up; + }; +}; + +&pon_resin { + linux,code =3D ; + status =3D "okay"; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id =3D "B_E0"; + + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + vdd-l1-l10-l15-supply =3D <&vreg_s9f_e0_1p9>; + vdd-l2-l7-l8-l9-l16-supply =3D <&vreg_bob1_e0>; + vdd-l11-l12-l18-supply =3D <&vreg_s7f_e0_1p32>; + vdd-l17-supply =3D <&vreg_bob2_e0>; + + vreg_bob1_e0: bob1 { + regulator-name =3D "vreg_bob1_e0"; + regulator-min-microvolt =3D <2200000>; + regulator-max-microvolt =3D <4224000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2_e0: bob2 { + regulator-name =3D "vreg_bob2_e0"; + regulator-min-microvolt =3D <2540000>; + regulator-max-microvolt =3D <3600000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_e0_1p8: ldo1 { + regulator-name =3D "vreg_l1b_e0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_e0_2p9: ldo2 { + regulator-name =3D "vreg_l2b_e0_2p9"; + regulator-min-microvolt =3D <2904000>; + regulator-max-microvolt =3D <2904000>; + regulator-initial-mode =3D ; + }; + + vreg_l7b_e0_2p79: ldo7 { + regulator-name =3D "vreg_l7b_e0_2p79"; + regulator-min-microvolt =3D <2790000>; + regulator-max-microvolt =3D <2792000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_e0_1p50: ldo8 { + regulator-name =3D "vreg_l8b_e0_1p50"; + regulator-min-microvolt =3D <1504000>; + regulator-max-microvolt =3D <1504000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b_e0_2p7: ldo9 { + regulator-name =3D "vreg_l9b_e0_2p7"; + regulator-min-microvolt =3D <2704000>; + regulator-max-microvolt =3D <2704000>; + regulator-initial-mode =3D ; + }; + + vreg_l10b_e0_1p8: ldo10 { + regulator-name =3D "vreg_l10b_e0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l11b_e0_1p2: ldo11 { + regulator-name =3D "vreg_l11b_e0_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b_e0_1p14: ldo12 { + regulator-name =3D "vreg_l12b_e0_1p14"; + regulator-min-microvolt =3D <1144000>; + regulator-max-microvolt =3D <1144000>; + regulator-initial-mode =3D ; + }; + + vreg_l15b_e0_1p8: ldo15 { + regulator-name =3D "vreg_l15b_e0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b_e0_2p4: ldo17 { + regulator-name =3D "vreg_l17b_e0_2p4"; + regulator-min-microvolt =3D <2400000>; + regulator-max-microvolt =3D <2700000>; + regulator-initial-mode =3D ; + }; + + vreg_l18b_e0_1p2: ldo18 { + regulator-name =3D "vreg_l18b_e0_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id =3D "C_E1"; + + vdd-l2-supply =3D <&vreg_s7f_e0_1p32>; + vdd-l1-l3-l4-supply =3D <&vreg_s8f_e0_0p95>; + + vreg_l1c_e1_0p82: ldo1 { + regulator-name =3D "vreg_l1c_e1_0p82"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l2c_e1_1p14: ldo2 { + regulator-name =3D "vreg_l2c_e1_1p14"; + regulator-min-microvolt =3D <1144000>; + regulator-max-microvolt =3D <1144000>; + regulator-initial-mode =3D ; + }; + + vreg_l3c_e1_0p89: ldo3 { + regulator-name =3D "vreg_l3c_e1_0p89"; + regulator-min-microvolt =3D <890000>; + regulator-max-microvolt =3D <980000>; + regulator-initial-mode =3D ; + }; + + vreg_l4c_e1_0p72: ldo4 { + regulator-name =3D "vreg_l4c_e1_0p72"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <720000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "F_E0"; + vdd-s7-supply =3D <&vph_pwr>; + vdd-s8-supply =3D <&vph_pwr>; + vdd-s9-supply =3D <&vph_pwr>; + vdd-s10-supply =3D <&vph_pwr>; + vdd-l2-supply =3D <&vreg_s8f_e0_0p95>; + vdd-l3-supply =3D <&vreg_s8f_e0_0p95>; + vdd-l4-supply =3D <&vreg_s8f_e0_0p95>; + + vreg_s7f_e0_1p32: smps7 { + regulator-name =3D "vreg_s7f_e0_1p32"; + regulator-min-microvolt =3D <1320000>; + regulator-max-microvolt =3D <1352000>; + regulator-initial-mode =3D ; + }; + + vreg_s8f_e0_0p95: smps8 { + regulator-name =3D "vreg_s8f_e0_0p95"; + regulator-min-microvolt =3D <952000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_s9f_e0_1p9: smps9 { + regulator-name =3D "vreg_s9f_e0_1p9"; + regulator-min-microvolt =3D <1900000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f_e0_0p82: ldo2 { + regulator-name =3D "vreg_l2f_e0_0p82"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l3f_e0_0p72: ldo3 { + regulator-name =3D "vreg_l3f_e0_0p72"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <720000>; + regulator-initial-mode =3D ; + }; + + vreg_l4f_e0_0p3: ldo4 { + regulator-name =3D "vreg_l4f_e0_0p3"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "F_E1"; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + vdd-s7-supply =3D <&vph_pwr>; + vdd-l1-supply =3D <&vreg_s8f_e0_0p95>; + vdd-l2-supply =3D <&vreg_s8f_e0_0p95>; + vdd-l4-supply =3D <&vreg_s8f_e0_0p95>; + + vreg_s7f_e1_0p3: smps7 { + regulator-name =3D "vreg_s7f_e1_0p3"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_e1_0p82: ldo1 { + regulator-name =3D "vreg_l1f_e1_0p82"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f_e1_0p83: ldo2 { + regulator-name =3D "vreg_l2f_e1_0p83"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l4f_e1_1p08: ldo4 { + regulator-name =3D "vreg_l4f_e1_1p08"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1320000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "H_E0"; + + vdd-l1-supply =3D <&vreg_s8f_e0_0p95>; + vdd-l2-supply =3D <&vreg_s8f_e0_0p95>; + vdd-l3-supply =3D <&vreg_s9f_e0_1p9>; + vdd-l4-supply =3D <&vreg_s7f_e0_1p32>; + + vreg_l1h_e0_0p89: ldo1 { + regulator-name =3D "vreg_l1h_e0_0p89"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l2h_e0_0p72: ldo2 { + regulator-name =3D "vreg_l2h_e0_0p72"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l3h_e0_0p32: ldo3 { + regulator-name =3D "vreg_l3h_e0_0p32"; + regulator-min-microvolt =3D <320000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l4h_e0_1p2: ldo4 { + regulator-name =3D "vreg_l4h_e0_1p2"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1320000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&gpi_dma0 { + status =3D "okay"; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpi_dma2 { + status =3D "okay"; +}; + +&pmk8850_rtc { + qcom,no-alarm; +}; + +&pmh0101_gpios { + nvme_reg_en: nvme-reg-en-state { + pins =3D "gpio14"; + function =3D "normal"; + bias-disable; + }; +}; + +&qupv3_0 { + status =3D "okay"; +}; + +&qupv3_1 { + status =3D "okay"; +}; + +&qupv3_2 { + status =3D "okay"; +}; + +&pmh0110_f_e1_gpios { + nvme_sec_reg_en: nvme-reg-en-state { + pins =3D "gpio14"; + function =3D "normal"; + bias-disable; + }; +}; + +&pcie3b { + vddpe-3v3-supply =3D <&vreg_nvme_sec>; + + pinctrl-0 =3D <&pcie3b_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie3b_phy { + vdda-phy-supply =3D <&vreg_l3c_e1_0p89>; + vdda-pll-supply =3D <&vreg_l2c_e1_1p14>; + + status =3D "okay"; +}; + +&pcie3b_port0 { + reset-gpios =3D <&tlmm 155 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 157 GPIO_ACTIVE_LOW>; +}; + +&pcie4 { + vddpe-3v3-supply =3D <&vreg_wlan>; + + pinctrl-0 =3D <&pcie4_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie4_phy { + vdda-phy-supply =3D <&vreg_l1c_e1_0p82>; + vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; + + status =3D "okay"; +}; + +&pcie4_port0 { + reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + +&pcie5 { + vddpe-3v3-supply =3D <&vreg_nvme>; + + pinctrl-0 =3D <&pcie5_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie5_phy { + vdda-phy-supply =3D <&vreg_l2f_e0_0p82>; + vdda-pll-supply =3D <&vreg_l4h_e0_1p2>; + + status =3D "okay"; +}; + +&pcie5_port0 { + reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pcie6 { + vddpe-3v3-supply =3D <&vreg_wwan>; + + pinctrl-0 =3D <&pcie6_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie6_phy { + vdda-phy-supply =3D <&vreg_l1c_e1_0p82>; + vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; + + status =3D "okay"; +}; + +&pcie6_port0 { + reset-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; +}; --=20 2.34.1