From nobody Mon Feb 9 16:13:04 2026 Received: from mail-ot1-f49.google.com (mail-ot1-f49.google.com [209.85.210.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C485346A11 for ; Fri, 19 Dec 2025 21:33:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180020; cv=none; b=EdkX8GSpmTXAwgS+uizIEQxcUwVjFV5cdHPTFA7Tn/0C922i6hbrzJOflEZLebhL1jRWJxbc+Dnwb8zRMHKoXzhBWoIn8ox8edUX0uFMaMmEvDi1j0z7/Ptmn2z+QyC4tvY1Ue+X8AEiwCdsiesCO4Ja9k9i66zvGyA6TUNAwsQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180020; c=relaxed/simple; bh=dY7cp3RBBiVCkp9Kcc53brAEC9hdPWhw6DTjqjQNuOU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sdCPi1XxbZru3AJLrguvmgLJnS51enM2U5FhA1F8pD2y1nxpsHpaJ/2twTb7FF8yno7SrcAmpzwHffiHJyUSUkX7dqzNjD3zRMk5s0Fd3uso7/IRNyE6Ll11U5h445c45nr+decUwcwGC/qufattenomUY0JjSj8YBu6U4yprkU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=OYBHwfmE; arc=none smtp.client-ip=209.85.210.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="OYBHwfmE" Received: by mail-ot1-f49.google.com with SMTP id 46e09a7af769-7c765f41346so1098155a34.3 for ; Fri, 19 Dec 2025 13:33:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1766180015; x=1766784815; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3Z43oS2Jw0Ev4dfYo22by9u6LAdxn5XavRVOij2D4nc=; b=OYBHwfmEq716OpxS6FqQ3aBY2UuKnc0yNAHfFyN/KxzpndfNIqaTuQH1n3SwY9aWqJ fefzVPchGoywDJZ46oOWLtesBz1ABgSMraRPNC/3nS6DXoOn4swg69p/Y8WmhtTtbVnY LN3WECQOUolYLJaeq3gGTmb+H5Xyoj/5VsvutwHWGH/xG9LaFJjIrmFKzTwoo66hg6by epSNL/j351nTVGNuU5X69eEQ3JIrKVww3hGkBRJIrz5LbenmfO4Y8p867nLfwM7bOwRP ne82WgySl/dPYqsoKk3SLfshQzSSym57jlkyF2/FKtSepjYgSxH6+ItrGjJCTObICVux GMiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766180015; x=1766784815; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=3Z43oS2Jw0Ev4dfYo22by9u6LAdxn5XavRVOij2D4nc=; b=kSt96fU94AwZDeJgL9rWCP72asljJFopPZWbMLZ4yhBFKln9iKuESNWT7Q5Qc+uGt+ b+yrQkTJvh7QTtNZUVOC2OqA1Hm4L74C1Db/GK6OtYewucIVZDi3N6MPQfQ1raTpr1Cz ekq6fMlCm7PypG28lSQhiyYCShsICHXJpxZ5O2pWEvX5EqcaYrvDBrO0reKtUE9WbQJT aPOKjSYcvVfuUVWXfzZxGOk/blJDtSG9DrGd1cBPuU9lE1Xv4BGjg3qc0qV1vfgPJwYm iBa3hGcy4ILiZBYsA5bGJ+AtVoYq20w6URe1PFeG8scXRiRVP/nugu5/qQ4ZfzoVM4DV J7HQ== X-Forwarded-Encrypted: i=1; AJvYcCWEnBvOpxH1K00GBuAQ6uL4Qc9rnKaM3dthC/KIanntXm524iEBZO2K3N+tX/GSfctCAjcSEKHgxtFNl+Q=@vger.kernel.org X-Gm-Message-State: AOJu0YxO1xcweRvDn0k7wFEh+/Uap8pLvHgrGpdZgV/gAS1VWdLogiQu V7o8P6eupHqbyvYiijHjcp1sRp7YOmtZDIcjNWjJ/8L3bJ2PGQhp7E5dmdV5Cq+Sh44= X-Gm-Gg: AY/fxX5B7BV1QwaeEdFhmqFGW/92oh5FqDJPqdhJYLl1UbJiKC/oZzV7zfZQH66pyfZ JmsvxxnkEs5IyG61dI6F6o+f4891O71Gj8a/ODETFmPGsNUoqhq2OM5mkv05iD+1JJG4uOppcYx gQrsil+tl5o6jNEiOTLuKVtvenfmu3R9LYmdlYMe3OGZLSEN8/DCNBzBZOURapcdZQ8M3xfAJuA k+mCjwTzj+Rv+1rK5lS4THqxp5sZk957eJ9E7f3ONHJQhAjs4vreTnzgnu/Yl+4M5VIcudI5LLL DduqJbiOaUhLjhew5JHPc0G5P5fxiYSnItfQvCU85G7r35IIdNvn1gFvU6lRSXTeCTboEBGc36R VPom3X1/xiD0UKX4HhiOo9q53JqV+KUqxIg2OtypXhiIR+9cMA4Eh1g8S0yrrQsnxtnljnGkfIV VsKNMpOUPpl2koLkhwMouc7JvU X-Google-Smtp-Source: AGHT+IEV2Y3TdkUjmquqF6HvA05aKkAArLkAjqKr0vCj0HIE8vG1QcO6ia3T+QJa2w3j6AwwMjeNgw== X-Received: by 2002:a05:6830:3105:b0:7c7:6348:594a with SMTP id 46e09a7af769-7cc668e8135mr2423716a34.7.1766180015061; Fri, 19 Dec 2025 13:33:35 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:9b20:bac4:9680:435]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7cc667563ffsm2485045a34.13.2025.12.19.13.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 13:33:34 -0800 (PST) From: David Lechner Date: Fri, 19 Dec 2025 15:32:15 -0600 Subject: [PATCH v4 7/9] spi: axi-spi-engine: support SPI_MULTI_LANE_MODE_STRIPE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-spi-add-multi-bus-support-v4-7-145dc5204cd8@baylibre.com> References: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> In-Reply-To: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=12068; i=dlechner@baylibre.com; h=from:subject:message-id; bh=dY7cp3RBBiVCkp9Kcc53brAEC9hdPWhw6DTjqjQNuOU=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpRcSRlMrxU20bsdrnwA0lULCe3bQauFngTE13D Cztvrg/HdKJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUXEkQAKCRDCzCAB/wGP wAYwB/9ZG35txJDZP6Mh2qj0HGLp4MngWr27B9x859qchxnuxg4Mdf9PGWo4QB5JyjIXpEWwerT AwEnsUnQVT7LM7du3wlzfxh5EKE5Zyq4kRGp8dKICL3W2u9H1hkgBLGIDaCpGc83QNf3vyi8469 HAPkzivB8SKBp/1hJeYiLx1ZYO+0J3bwbO3cpEVhaf+PHC9iT4tqnepj4FzGFWIoCsxxAbf9VLC OKq/XuQ0xN2dFzjhFxKFF5hnMdXLnpQcGWMf7FPTTkiun8Yad9nFZci3yVc6JJZFXaVN4WG9MAq sRmGuv67klWTxgPuNzeL8Sio0c1fKWuJNBlF6svZLB0FI2xq X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add support for SPI_MULTI_LANE_MODE_STRIPE to the AXI SPI engine driver. The v2.0.0 version of the AXI SPI Engine IP core supports multiple lanes. This can be used with SPI_MULTI_LANE_MODE_STRIPE to support reading from simultaneous sampling ADCs that have a separate SDO line for each analog channel. This allows reading all channels at the same time to increase throughput. Signed-off-by: David Lechner Reviewed-by: Marcelo Schmitt --- v4 changes: * Update for core SPI API changes. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. v2 changes: * Fixed off-by-one in SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO_MASK GENMASK --- drivers/spi/spi-axi-spi-engine.c | 145 +++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 141 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi-eng= ine.c index e06f412190fd..3028e6112909 100644 --- a/drivers/spi/spi-axi-spi-engine.c +++ b/drivers/spi/spi-axi-spi-engine.c @@ -23,6 +23,9 @@ #include #include =20 +#define SPI_ENGINE_REG_DATA_WIDTH 0x0C +#define SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO_MASK GENMASK(23, 16) +#define SPI_ENGINE_REG_DATA_WIDTH_MASK GENMASK(15, 0) #define SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH 0x10 #define SPI_ENGINE_REG_RESET 0x40 =20 @@ -75,6 +78,8 @@ #define SPI_ENGINE_CMD_REG_CLK_DIV 0x0 #define SPI_ENGINE_CMD_REG_CONFIG 0x1 #define SPI_ENGINE_CMD_REG_XFER_BITS 0x2 +#define SPI_ENGINE_CMD_REG_SDI_MASK 0x3 +#define SPI_ENGINE_CMD_REG_SDO_MASK 0x4 =20 #define SPI_ENGINE_MISC_SYNC 0x0 #define SPI_ENGINE_MISC_SLEEP 0x1 @@ -105,6 +110,10 @@ #define SPI_ENGINE_OFFLOAD_CMD_FIFO_SIZE 16 #define SPI_ENGINE_OFFLOAD_SDO_FIFO_SIZE 16 =20 +/* Extending SPI_MULTI_LANE_MODE values for optimizing messages. */ +#define SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN -1 +#define SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING -2 + struct spi_engine_program { unsigned int length; uint16_t instructions[] __counted_by(length); @@ -142,6 +151,11 @@ struct spi_engine_offload { unsigned long flags; unsigned int offload_num; unsigned int spi_mode_config; + unsigned int multi_lane_mode; + u8 rx_primary_lane_mask; + u8 tx_primary_lane_mask; + u8 rx_all_lanes_mask; + u8 tx_all_lanes_mask; u8 bits_per_word; }; =20 @@ -165,6 +179,25 @@ struct spi_engine { bool offload_requires_sync; }; =20 +static void spi_engine_primary_lane_flag(struct spi_device *spi, + u8 *rx_lane_flags, u8 *tx_lane_flags) +{ + *rx_lane_flags =3D BIT(spi->rx_lane_map[0]); + *tx_lane_flags =3D BIT(spi->tx_lane_map[0]); +} + +static void spi_engine_all_lanes_flags(struct spi_device *spi, + u8 *rx_lane_flags, u8 *tx_lane_flags) +{ + int i; + + for (i =3D 0; i < spi->num_rx_lanes; i++) + *rx_lane_flags |=3D BIT(spi->rx_lane_map[i]); + + for (i =3D 0; i < spi->num_tx_lanes; i++) + *tx_lane_flags |=3D BIT(spi->tx_lane_map[i]); +} + static void spi_engine_program_add_cmd(struct spi_engine_program *p, bool dry, uint16_t cmd) { @@ -193,7 +226,7 @@ static unsigned int spi_engine_get_config(struct spi_de= vice *spi) } =20 static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry, - struct spi_transfer *xfer) + struct spi_transfer *xfer, u32 num_lanes) { unsigned int len; =20 @@ -204,6 +237,9 @@ static void spi_engine_gen_xfer(struct spi_engine_progr= am *p, bool dry, else len =3D xfer->len / 4; =20 + if (xfer->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) + len /=3D num_lanes; + while (len) { unsigned int n =3D min(len, 256U); unsigned int flags =3D 0; @@ -269,6 +305,7 @@ static int spi_engine_precompile_message(struct spi_mes= sage *msg) { unsigned int clk_div, max_hz =3D msg->spi->controller->max_speed_hz; struct spi_transfer *xfer; + int multi_lane_mode =3D SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN; u8 min_bits_per_word =3D U8_MAX; u8 max_bits_per_word =3D 0; =20 @@ -284,6 +321,24 @@ static int spi_engine_precompile_message(struct spi_me= ssage *msg) min_bits_per_word =3D min(min_bits_per_word, xfer->bits_per_word); max_bits_per_word =3D max(max_bits_per_word, xfer->bits_per_word); } + + if (xfer->rx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM || + xfer->tx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_TX_STREAM) { + switch (xfer->multi_lane_mode) { + case SPI_MULTI_LANE_MODE_SINGLE: + case SPI_MULTI_LANE_MODE_STRIPE: + break; + default: + /* Other modes, like mirror not supported */ + return -EINVAL; + } + + /* If all xfers have the same multi-lane mode, we can optimize. */ + if (multi_lane_mode =3D=3D SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN) + multi_lane_mode =3D xfer->multi_lane_mode; + else if (multi_lane_mode !=3D xfer->multi_lane_mode) + multi_lane_mode =3D SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING; + } } =20 /* @@ -297,6 +352,14 @@ static int spi_engine_precompile_message(struct spi_me= ssage *msg) priv->bits_per_word =3D min_bits_per_word; else priv->bits_per_word =3D 0; + + priv->multi_lane_mode =3D multi_lane_mode; + spi_engine_primary_lane_flag(msg->spi, + &priv->rx_primary_lane_mask, + &priv->tx_primary_lane_mask); + spi_engine_all_lanes_flags(msg->spi, + &priv->rx_all_lanes_mask, + &priv->tx_all_lanes_mask); } =20 return 0; @@ -310,6 +373,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, struct spi_engine_offload *priv; struct spi_transfer *xfer; int clk_div, new_clk_div, inst_ns; + int prev_multi_lane_mode =3D SPI_MULTI_LANE_MODE_SINGLE; bool keep_cs =3D false; u8 bits_per_word =3D 0; =20 @@ -334,6 +398,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, * in the same way. */ bits_per_word =3D priv->bits_per_word; + prev_multi_lane_mode =3D priv->multi_lane_mode; } else { spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG, @@ -344,6 +409,28 @@ static void spi_engine_compile_message(struct spi_mess= age *msg, bool dry, spi_engine_gen_cs(p, dry, spi, !xfer->cs_off); =20 list_for_each_entry(xfer, &msg->transfers, transfer_list) { + if (xfer->rx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM || + xfer->tx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_TX_STREAM) { + if (xfer->multi_lane_mode !=3D prev_multi_lane_mode) { + u8 tx_lane_flags, rx_lane_flags; + + if (xfer->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) + spi_engine_all_lanes_flags(spi, &rx_lane_flags, + &tx_lane_flags); + else + spi_engine_primary_lane_flag(spi, &rx_lane_flags, + &tx_lane_flags); + + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + rx_lane_flags)); + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + tx_lane_flags)); + } + prev_multi_lane_mode =3D xfer->multi_lane_mode; + } + new_clk_div =3D host->max_speed_hz / xfer->effective_speed_hz; if (new_clk_div !=3D clk_div) { clk_div =3D new_clk_div; @@ -360,7 +447,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, bits_per_word)); } =20 - spi_engine_gen_xfer(p, dry, xfer); + spi_engine_gen_xfer(p, dry, xfer, spi->num_rx_lanes); spi_engine_gen_sleep(p, dry, spi_delay_to_ns(&xfer->delay, xfer), inst_ns, xfer->effective_speed_hz); =20 @@ -394,6 +481,19 @@ static void spi_engine_compile_message(struct spi_mess= age *msg, bool dry, if (clk_div !=3D 1) spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV, 0)); + + /* Restore single lane mode unless offload disable will restore it later.= */ + if (prev_multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE && + (!msg->offload || priv->multi_lane_mode !=3D SPI_MULTI_LANE_MODE_STRI= PE)) { + u8 rx_lane_flags, tx_lane_flags; + + spi_engine_primary_lane_flag(spi, &rx_lane_flags, &tx_lane_flags); + + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, rx_lane_flags)); + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, tx_lane_flags)); + } } =20 static void spi_engine_xfer_next(struct spi_message *msg, @@ -799,6 +899,19 @@ static int spi_engine_setup(struct spi_device *device) writel_relaxed(SPI_ENGINE_CMD_CS_INV(spi_engine->cs_inv), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 + if (host->num_data_lanes > 1) { + u8 rx_lane_flags, tx_lane_flags; + + spi_engine_primary_lane_flag(device, &rx_lane_flags, &tx_lane_flags); + + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + rx_lane_flags), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + tx_lane_flags), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } + /* * In addition to setting the flags, we have to do a CS assert command * to make the new setting actually take effect. @@ -902,6 +1015,15 @@ static int spi_engine_trigger_enable(struct spi_offlo= ad *offload) priv->bits_per_word), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 + if (priv->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) { + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + priv->rx_all_lanes_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + priv->tx_all_lanes_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } + writel_relaxed(SPI_ENGINE_CMD_SYNC(1), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 @@ -929,6 +1051,16 @@ static void spi_engine_trigger_disable(struct spi_off= load *offload) reg &=3D ~SPI_ENGINE_OFFLOAD_CTRL_ENABLE; writel_relaxed(reg, spi_engine->base + SPI_ENGINE_REG_OFFLOAD_CTRL(priv->offload_num)); + + /* Restore single-lane mode. */ + if (priv->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) { + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + priv->rx_primary_lane_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + priv->tx_primary_lane_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } } =20 static struct dma_chan @@ -973,7 +1105,7 @@ static int spi_engine_probe(struct platform_device *pd= ev) { struct spi_engine *spi_engine; struct spi_controller *host; - unsigned int version; + unsigned int version, data_width_reg_val; int irq, ret; =20 irq =3D platform_get_irq(pdev, 0); @@ -1042,7 +1174,7 @@ static int spi_engine_probe(struct platform_device *p= dev) return PTR_ERR(spi_engine->base); =20 version =3D readl(spi_engine->base + ADI_AXI_REG_VERSION); - if (ADI_AXI_PCORE_VER_MAJOR(version) !=3D 1) { + if (ADI_AXI_PCORE_VER_MAJOR(version) > 2) { dev_err(&pdev->dev, "Unsupported peripheral version %u.%u.%u\n", ADI_AXI_PCORE_VER_MAJOR(version), ADI_AXI_PCORE_VER_MINOR(version), @@ -1050,6 +1182,8 @@ static int spi_engine_probe(struct platform_device *p= dev) return -ENODEV; } =20 + data_width_reg_val =3D readl(spi_engine->base + SPI_ENGINE_REG_DATA_WIDTH= ); + if (adi_axi_pcore_ver_gteq(version, 1, 1)) { unsigned int sizes =3D readl(spi_engine->base + SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH); @@ -1097,6 +1231,9 @@ static int spi_engine_probe(struct platform_device *p= dev) } if (adi_axi_pcore_ver_gteq(version, 1, 3)) host->mode_bits |=3D SPI_MOSI_IDLE_LOW | SPI_MOSI_IDLE_HIGH; + if (adi_axi_pcore_ver_gteq(version, 2, 0)) + host->num_data_lanes =3D FIELD_GET(SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO= _MASK, + data_width_reg_val); =20 if (host->max_speed_hz =3D=3D 0) return dev_err_probe(&pdev->dev, -EINVAL, "spi_clk rate is 0"); --=20 2.43.0