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Fri, 19 Dec 2025 13:33:29 -0800 (PST) From: David Lechner Date: Fri, 19 Dec 2025 15:32:10 -0600 Subject: [PATCH v4 2/9] spi: dt-bindings: add spi-{tx,rx}-lane-map properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-spi-add-multi-bus-support-v4-2-145dc5204cd8@baylibre.com> References: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> In-Reply-To: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2219; i=dlechner@baylibre.com; h=from:subject:message-id; bh=TqPWfvOKcEsi12rSA+ulOC61NeC7/72fTMR7lVl6WbU=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpRcRxkkWWmrsQKWOdOOI4zUmj8yp+SSBCoYPla Ijt1bECtPOJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUXEcQAKCRDCzCAB/wGP wOS5B/95gImmMOy/n5PIPOKuqGZKZlN6KkZHhVvrFPsEYpOxGhMAm2wfTl/Hi6Ro1jAT1xSOPGF e9a7iLotreIH1SHeMvvvzUyZM8OSPL1PYw72p+OXRAnXJLkAFv1SH1irWKZ4klHAkfkpQPs/Z/D bmsFLhKMWtTS8Cjh9MCflaYH6uETdgh7NwIyECT/z2BqK/RQWjJ0PkBijrJfbryfoQiPbJIQgkJ XGHzpjN2RaX9Q/XhkJxq8z7yyeWEbS3Am7uW54r13ra/K7v/G+AupfGhqZU7T4paWW8fR6/WUGQ RozmMQzn7BtuCXf8H1q8+SGyD7Om84FmAVZYKv91k6mn3/BY X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add spi-tx-lane-map and spi-rx-lane-map properties to the SPI peripheral device tree binding. These properties allow specifying the mapping of peripheral data lanes to controller data lanes. This is needed e.g. when some lanes are skipped on the controller side so that the controller can correctly route data to/from the peripheral. Signed-off-by: David Lechner Reviewed-by: Rob Herring (Arm) --- v4 changes: - This replaces the data-lanes property from the previous revision. Now there are separate properties for tx and rx lane maps. And instead of being the primary property for determining the number of lanes, this is only needed in special cases where the mapping is non-trivial. --- .../devicetree/bindings/spi/spi-peripheral-props.yaml | 14 ++++++++++= ++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 59ddead7da14..2f278f145f78 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -75,6 +75,13 @@ properties: enum: [0, 1, 2, 4, 8] default: [1] =20 + spi-rx-lane-map: + description: Mapping of peripheral RX lanes to controller RX lanes. + Each index in the array represents a peripheral RX lane, and the val= ue + at that index represents the corresponding controller RX lane. + $ref: /schemas/types.yaml#/definitions/uint32-array + default: [0, 1, 2, 3, 4, 5, 6, 7] + spi-rx-delay-us: description: Delay, in microseconds, after a read transfer. @@ -99,6 +106,13 @@ properties: enum: [0, 1, 2, 4, 8] default: [1] =20 + spi-tx-lane-map: + description: Mapping of peripheral TX lanes to controller TX lanes. + Each index in the array represents a peripheral TX lane, and the val= ue + at that index represents the corresponding controller TX lane. + $ref: /schemas/types.yaml#/definitions/uint32-array + default: [0, 1, 2, 3, 4, 5, 6, 7] + spi-tx-delay-us: description: Delay, in microseconds, after a write transfer. --=20 2.43.0