From nobody Sun Feb 8 13:27:49 2026 Received: from mail-oi1-f182.google.com (mail-oi1-f182.google.com [209.85.167.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 412A83242A9 for ; Fri, 19 Dec 2025 21:33:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180012; cv=none; b=T0z0Jd94JGcx1UqCKTUM7MjB6v1IWtgZXtqKB7EVGMUTuJD+TC0U25DL7sX2BMgcpw1gnYQXljQ35b0GqIPmm+5o2//8YLgWt9Dl9JklUF4N2iAJXIiXFYxz8p1GC3wzkvWKjSRsZbzX0+IxXliypoPWHE9Iku1O/9j8LgCEmlk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180012; c=relaxed/simple; bh=eXLLDXKfOA+2V2f1sRQNUzsvVCDsgch7yTVzmIc7Kfs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pVmWEhBIzIwe2x8W6SOxTHyIHlhqkwyuNrXPqdUqsB7gVim/Nudc9uAIIb6nRWhw16EhFsJbVMvI/mEl6Z2uOYzQb1A/dEIteytjkonrxrPml9FLy/UuayGchIIIIyLiNtW0OBlhfQOdv25Y+9EkGjJpDiA0cnJn3wEeDNgjwTI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=h5xDNzCY; arc=none smtp.client-ip=209.85.167.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="h5xDNzCY" Received: by mail-oi1-f182.google.com with SMTP id 5614622812f47-45330fe6e1bso1415656b6e.2 for ; Fri, 19 Dec 2025 13:33:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1766180009; x=1766784809; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=CwhL2XTdSKphpbDNArSNYm/QFBPbMdsK+MdRobcyzN8=; b=h5xDNzCYa+kR/oZEZWzDXsu2VAju3tz9jqbZH4p16XSnK2vaFfv9RC4ETj2MfTg+7R d6JVlEAsiGiA7gSYYVW26FtqFYG48LYc0qVKQOIwDIUdPDJ3MRw899XtSBB0/JjeNrVH QQSqIc6K2BXHHMyuDyO6W5JtymoC6wNmfBiSScdRal11J+zzA74yky/gzm9U1aBbRj/L lvf/l2xeICZEyxWqk/r67rQUGapGB5Q4lNYLAlsZM9C4Xyg1suQa7VcS0lBES41XX7h8 tq1/eFQWFse2jJZz7AblaEKkbbHlQpBruRAkbSAcO5mR86Y2YXaUuDRn77OglurseAHR Jc/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766180009; x=1766784809; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=CwhL2XTdSKphpbDNArSNYm/QFBPbMdsK+MdRobcyzN8=; b=UPLLT1YHpLfPEdIdszcPMnLPY4tS51rXRTSgFRRHaKAyZ/3LCNt0Jv4+Fh39PQgT/9 XWcdL8auBc5FnC95xelocZLuIBwnxO0MNi6O8vN8H8HUGP73QCvP2o2DZnQDZqQfJXZ+ igY+nvVi8ax/PAgy0OYNEeaLGdbHo8EZzTzlzia+DKLdo3aaoG7K4OohZOQHv9nqkRQk s60tw+PxQAMhibDELMNRah6Hn6WHMCZE9f3FlsVq5urK24Y+DIekJISSJuU+j+9ZqJEO Rt5TmwGamBif+UhaZQ5mOhSZZsMd9sGUHRJVfGw1RChpjTSwzYTMqHOViRCJfsSuZM51 s2Hg== X-Forwarded-Encrypted: i=1; AJvYcCXWeP67lPYbnYo9cdShXO4ZVt1jEM0bGz+X90/efnd5QYck0N+1TrDEJSVZ6tkDswSq/Ow2KoGfQnoe2ms=@vger.kernel.org X-Gm-Message-State: AOJu0Yx/3b/Sx9TpULgAzn9HbeJOa4URGkQ7pgk0FvBrIZLMtd0V/PDa ZQpR9Wr6sprfudggCBZ+mEMdSZ3JJJxQZaGZGsswyB0I5CW79o3xrDgXOu5W3SchCpI= X-Gm-Gg: AY/fxX5WNME0zDNIfYgIk8FbLGg1Uom0Q/oPIbyJNpmB716P+ALLz+3pS5fKJ//0IpS M07sUVMZ1wLiQUNSuVOSrmWI/GWQNEpCa04Xx0xL0/aGOoei9J9ml25Rf7Q5JodvYUwy+nnQtxb b6FiRAMM6YhwwBoO7jwWm9F3Oe/GDQc48R74c83VPE1yeXq9GzxyG6VUHOOJabsPNxC9mrSw9Zn GrSd77+OQhq+DId5lXw0QXDeK4Srfr2pz//DM8+uvMw/1FhFkpzi5co1VJvVlU+cOH4VBY+I044 MyfKJc2N+9E3WYopAxjIo/ThS097bYN9UuqpYixR2SwU8BRw/H8esb2rJ52V3sEpKR712WqoHj8 wpDzrxpRpnihyi3Rkei3g/Js9LeJsDD5TAKcLBuC7urIGzv8Tp5HFm1J+yxMRi+DdDYuJKeR0AY aQjYvaoIc8Nvu6jQ== X-Google-Smtp-Source: AGHT+IHZJw+RiDLBmaeDbeQUFrqbDtSK1//gqrxlOK/7F319JCtYiEBVmJe2iut00bN7PQ7TNXN7GQ== X-Received: by 2002:a05:6808:189e:b0:450:c877:fd5f with SMTP id 5614622812f47-457b200ba40mr2182741b6e.49.1766180009065; Fri, 19 Dec 2025 13:33:29 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:9b20:bac4:9680:435]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7cc667563ffsm2485045a34.13.2025.12.19.13.33.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 13:33:28 -0800 (PST) From: David Lechner Date: Fri, 19 Dec 2025 15:32:09 -0600 Subject: [PATCH v4 1/9] spi: dt-bindings: change spi-{rx,tx}-bus-width to arrays Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-spi-add-multi-bus-support-v4-1-145dc5204cd8@baylibre.com> References: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> In-Reply-To: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=9014; i=dlechner@baylibre.com; h=from:subject:message-id; bh=eXLLDXKfOA+2V2f1sRQNUzsvVCDsgch7yTVzmIc7Kfs=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpRcRqhY5V6vWS8QZzXn5TO9ZsSyacivD7iII1g aFHllTGzXWJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUXEagAKCRDCzCAB/wGP wKTNCACM6BZcUhlLZs31DgYm4ylqfRE/65t20Nh62ANpb0i3H5ZSZEa+LB73pzj868YLQjlEYo/ IEiz3BUDJdRjxh+Jc1hY7490TCgX9uLua7OCy88M58/i5SfTm/mFkmfSPJQ90vPciOLVWyO9G5d ++uOVWW8BHbx1Jy5/bMZnsNaTXS1kHDBCnM/VoSObk+8GYuY/UpKgZENTF3Cye1LF80HOQAs/Sz Mqgc645DVmGl2gP3qWifSinC+0Or2hjuwjuAoT7SZ9k6J8gr1M+ACfhL8WBEcNLSJJLrDPaaaZL /ZawSYElxndMZbmh6FBhDYyXuGKcx6mVg+3Z0LzxfslZ7tk+ X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Change spi-rx-bus-width and spi-tx-bus-width properties from single uint32 values to arrays of uint32 values. This allows describing SPI peripherals connected to controllers that have multiple data lanes for receiving or transmitting two or more words in parallel. Each index in the array corresponds to a physical data lane (one or more wires depending on the bus width). Additional mapping properties will be needed in cases where a lane on the controller or peripheral is skipped. Bindings that make use of this property are updated in the same commit to avoid validation errors. The adi,ad4030 binding can now better describe the chips multi-lane capabilities, so that binding is refined and gets a new example. Converting from single uint32 to array of uint32 does not break .dts/ .dtb files since there is no difference between specifying a single uint32 value and an array with a single uint32 value in devicetree. Signed-off-by: David Lechner Reviewed-by: Jonathan Cameron Reviewed-by: Marcelo Schmitt Reviewed-by: Rob Herring (Arm) --- v4 changes: - New patch to replace data-lanes property patch. In v3, Rob suggested possibly splitting the spi-controller.yaml file to have a way to make most SPI controllers have maxItems: 1 for these properties. I would like to avoid that because it doesn't seem scalable, e.g. if we need another similar split in the future, the number of combinations would grow exponentially (factorially?). I have an idea to instead do this using $dynamicAnchor and $dynamicRef, but dt-schema doesn't currently support that. So I propose we do the best we can for now with the current dt-schema and make further improvements later. Also, in v3, I suggested that we could have leading 0s in the arrays to indicate unused lanes. But after further consideration, I think it's better to have separate lane-mapping properties for that purpose. It will be easier to explain and parse and be a bit more flexible that way. --- .../bindings/display/panel/sitronix,st7789v.yaml | 5 +-- .../devicetree/bindings/iio/adc/adi,ad4030.yaml | 42 ++++++++++++++++++= +++- .../devicetree/bindings/iio/adc/adi,ad4695.yaml | 5 +-- .../bindings/spi/allwinner,sun4i-a10-spi.yaml | 6 ++-- .../bindings/spi/allwinner,sun6i-a31-spi.yaml | 6 ++-- .../bindings/spi/nvidia,tegra210-quad.yaml | 6 ++-- .../bindings/spi/spi-peripheral-props.yaml | 26 ++++++++++---- 7 files changed, 79 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/sitronix,st778= 9v.yaml b/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.= yaml index 0ce2ea13583d..c35d4f2ab9a4 100644 --- a/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml +++ b/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml @@ -34,8 +34,9 @@ properties: spi-cpol: true =20 spi-rx-bus-width: - minimum: 0 - maximum: 1 + items: + minimum: 0 + maximum: 1 =20 dc-gpios: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index 54e7349317b7..e22d518135f2 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -37,7 +37,15 @@ properties: maximum: 102040816 =20 spi-rx-bus-width: - enum: [1, 2, 4] + maxItems: 2 + # all lanes must have the same width + oneOf: + - contains: + const: 1 + - contains: + const: 2 + - contains: + const: 4 =20 vdd-5v-supply: true vdd-1v8-supply: true @@ -88,6 +96,18 @@ oneOf: =20 unevaluatedProperties: false =20 +allOf: + - if: + properties: + compatible: + enum: + - adi,ad4030-24 + - adi,ad4032-24 + then: + properties: + spi-rx-bus-width: + maxItems: 1 + examples: - | #include @@ -108,3 +128,23 @@ examples: reset-gpios =3D <&gpio0 1 GPIO_ACTIVE_LOW>; }; }; + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4630-24"; + reg =3D <0>; + spi-max-frequency =3D <80000000>; + spi-rx-bus-width =3D <4>, <4>; + vdd-5v-supply =3D <&supply_5V>; + vdd-1v8-supply =3D <&supply_1_8V>; + vio-supply =3D <&supply_1_8V>; + ref-supply =3D <&supply_5V>; + cnv-gpios =3D <&gpio0 0 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4695.yaml index cbde7a0505d2..ae8d0b5f328b 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml @@ -38,8 +38,9 @@ properties: spi-cpha: true =20 spi-rx-bus-width: - minimum: 1 - maximum: 4 + items: + minimum: 1 + maximum: 4 =20 avdd-supply: description: Analog power supply. diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.= yaml b/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml index e1ab3f523ad6..a34e6471dbe8 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml @@ -55,10 +55,12 @@ patternProperties: maximum: 4 =20 spi-rx-bus-width: - const: 1 + items: + - const: 1 =20 spi-tx-bus-width: - const: 1 + items: + - const: 1 =20 required: - compatible diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.= yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 3b47b68b92cb..414f5bc36304 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -77,10 +77,12 @@ patternProperties: maximum: 4 =20 spi-rx-bus-width: - const: 1 + items: + - const: 1 =20 spi-tx-bus-width: - const: 1 + items: + - const: 1 =20 required: - compatible diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yam= l b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml index 8b3640280559..909c204b8adf 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml @@ -54,10 +54,12 @@ patternProperties: =20 properties: spi-rx-bus-width: - enum: [1, 2, 4] + items: + - enum: [1, 2, 4] =20 spi-tx-bus-width: - enum: [1, 2, 4] + items: + - enum: [1, 2, 4] =20 required: - compatible diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 8b6e8fc009db..59ddead7da14 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -64,9 +64,16 @@ properties: description: Bus width to the SPI bus used for read transfers. If 0 is provided, then no RX will be possible on this device. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 4, 8] - default: 1 + + Some SPI peripherals and controllers may have multiple data lanes for + receiving two or more words at the same time. If this is the case, e= ach + index in the array represents the lane on both the SPI peripheral and + controller. Additional mapping properties may be needed if a lane is + skipped on either side. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + enum: [0, 1, 2, 4, 8] + default: [1] =20 spi-rx-delay-us: description: @@ -81,9 +88,16 @@ properties: description: Bus width to the SPI bus used for write transfers. If 0 is provided, then no TX will be possible on this device. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 4, 8] - default: 1 + + Some SPI peripherals and controllers may have multiple data lanes for + transmitting two or more words at the same time. If this is the case= , each + index in the array represents the lane on both the SPI peripheral and + controller. Additional mapping properties may be needed if a lane is + skipped on either side. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + enum: [0, 1, 2, 4, 8] + default: [1] =20 spi-tx-delay-us: description: --=20 2.43.0 From nobody Sun Feb 8 13:27:49 2026 Received: from mail-ot1-f51.google.com (mail-ot1-f51.google.com [209.85.210.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3786733D4EC for ; Fri, 19 Dec 2025 21:33:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180013; cv=none; b=gsj+6kC7JpGzOOxgfKV50gZNTYdcqMqv+7DpAdNo/luQXPUjxEGPg2PnnBseHmT9vZ8LdRYuC1MMAcBq7KQUdl5idYVlRGQ9KPw7AzofGhYT61ElrPWTnoDK2uyQWT+fjVsWv44l6Sz9kftLYyd4CfgmL4tE+yUjfmaFZA2BSQ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180013; c=relaxed/simple; bh=TqPWfvOKcEsi12rSA+ulOC61NeC7/72fTMR7lVl6WbU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JZkGjk3ll7W2TRC0OJdD7MWmyFEHK7k18UZxsHY81VsKt6OPja1NUfeSv8UK8N6I1/3niIuBaT7axpvUhXFbwg6vt/Q7ReQ8FKyx7yC56mMKZMqxji3+Wj/KTGVMzt6UyNM08asM3Nm3dXDQtya6RggBmTlPNM3VWESpMcbMHAk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=eiKenuxs; arc=none smtp.client-ip=209.85.210.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="eiKenuxs" Received: by mail-ot1-f51.google.com with SMTP id 46e09a7af769-7c75fc222c3so880467a34.0 for ; Fri, 19 Dec 2025 13:33:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1766180010; x=1766784810; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=iqTEzojZ7TZAx7J/CtrZy1pdl4/BgUd5w2Zhg+1M8js=; b=eiKenuxsWbO2Wf3tFNv7lnyWkvmxYDK4pfGNzZBEKiqBlDcuFpNabK8taP/NfBHune TEV62AXnAICztvGJ9dEI7LwEVVk544gMSnSY9FXX8V0SgFKfFYp370iYHz3yvlS/P5tJ HVLdnmTTuTKntb/qjYqP6AFJvF/lu1Qda+Vss+8nET2AOQEcF/Sw5dlWRoC4qdzy7DS7 /3SXlgiz8V30ihw+MWcl0Kp6VIruBCWCVkpcyhdoaCDiSPKbCshK1rBTF/Ii0ZLvWNpy Uy6UTijR725FqE4y9PBctdudCI+beUnrt279FGmqnq29PiPsg1UnSsDyr7sHZRXeTZ7C UR3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766180010; x=1766784810; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=iqTEzojZ7TZAx7J/CtrZy1pdl4/BgUd5w2Zhg+1M8js=; b=dydtudsulSMQhe/2hAFY7QlGUNOgeXZZLiP9lk7/0Mn+JVPw4T++r3o5uabjHscgwJ esUHLEJLX3oX1CqPLym8o0U22Iw2guSWHNJBtThxRTRs4kWC7LLgJwb7mL6U9Fb6V+xo q/h6VTnWIsmb/XxEMtGeLhDHD0Ty4IkSpZxpZv9rZj1isatE0GFpCA+1tEJTWDDJxa4+ NbCo1dYpUYIzmQqP4sb9385i95lSfbvDVyg/QoujQCx1Qqk7pwXHpm2JG4krqFozzJtX IQcSEasez5ZCOUT/RPo5f6vr546PlCw6M+KZIOM8CVsCbeZBZttzXNyZWOZ6zc84fPrL ffuw== X-Forwarded-Encrypted: i=1; AJvYcCXqx4PJHU5SvHnZUpPbwPqHeqKRxo3tzXkwbsoH/BPuRuBMPChme9f7+6vA91QRbxHDn6JXnT7DZ24yJYs=@vger.kernel.org X-Gm-Message-State: AOJu0YwVWAVYll/EnLdaQcQe4PrrmzHqrP/WjTyY2pbmv1XU6KLXsSaQ 2pvrv+3wxYoiJKJkS57wXeiNj3CbRfDfNNuposObdokXQ5Dc3iuQyeKSmicVCymHBSo= X-Gm-Gg: AY/fxX6IVO7enlziduk9Ayl5Q6CNCQl5YbbH4wvTyz4XMt6GQ5FOEUyu3xITVdOXUXc YvxwJj0scDQLh4F8rGrgU/3id066f1tajyJGtyXgjtTST+cc/+P0s/xxBP1NHJ/FLJQEYGLKMrt GpekfiqdGq6VYMZEqEWP8Iq53/MFdP8qWeZTPhXLnIPHSQwFMnJfE2bjtcg2dYR/I4q6DKVYZCf vRQ75KducIhWGFjlDVPTkXnWTts0RWwGcK0loaAviHyc+6rDKHkQ+UY1LRZo2JkV3H8+MKX03YX Tw8YN1UqjYwBJxAOZMSa8tXZxVh7wAidrHmZ4Qr6mLHwbEmwrMXJIgQHWb10hxCg4+ccVNHVq3c vwLztpfpCf4ov0iQXiWZSlO11ALn9Tm5H4w22NVaUQm5qTBxawDYolL0wWg7hgBwbPMgSNCCtFr Tuz6Njvggbu7qGcRBYA3bj1lAK X-Google-Smtp-Source: AGHT+IHyP6fh0H8vwvnVPTmgakBhXpLLWUkiet6oHZRcT83wBBX+S6YNzLE4KzjmaR9ePZdUYAayXg== X-Received: by 2002:a05:6830:44a4:b0:78e:a394:ca24 with SMTP id 46e09a7af769-7cc668d0fb4mr2768916a34.8.1766180009947; Fri, 19 Dec 2025 13:33:29 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:9b20:bac4:9680:435]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7cc667563ffsm2485045a34.13.2025.12.19.13.33.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 13:33:29 -0800 (PST) From: David Lechner Date: Fri, 19 Dec 2025 15:32:10 -0600 Subject: [PATCH v4 2/9] spi: dt-bindings: add spi-{tx,rx}-lane-map properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-spi-add-multi-bus-support-v4-2-145dc5204cd8@baylibre.com> References: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> In-Reply-To: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2219; i=dlechner@baylibre.com; h=from:subject:message-id; bh=TqPWfvOKcEsi12rSA+ulOC61NeC7/72fTMR7lVl6WbU=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpRcRxkkWWmrsQKWOdOOI4zUmj8yp+SSBCoYPla Ijt1bECtPOJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUXEcQAKCRDCzCAB/wGP wOS5B/95gImmMOy/n5PIPOKuqGZKZlN6KkZHhVvrFPsEYpOxGhMAm2wfTl/Hi6Ro1jAT1xSOPGF e9a7iLotreIH1SHeMvvvzUyZM8OSPL1PYw72p+OXRAnXJLkAFv1SH1irWKZ4klHAkfkpQPs/Z/D bmsFLhKMWtTS8Cjh9MCflaYH6uETdgh7NwIyECT/z2BqK/RQWjJ0PkBijrJfbryfoQiPbJIQgkJ XGHzpjN2RaX9Q/XhkJxq8z7yyeWEbS3Am7uW54r13ra/K7v/G+AupfGhqZU7T4paWW8fR6/WUGQ RozmMQzn7BtuCXf8H1q8+SGyD7Om84FmAVZYKv91k6mn3/BY X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add spi-tx-lane-map and spi-rx-lane-map properties to the SPI peripheral device tree binding. These properties allow specifying the mapping of peripheral data lanes to controller data lanes. This is needed e.g. when some lanes are skipped on the controller side so that the controller can correctly route data to/from the peripheral. Signed-off-by: David Lechner Reviewed-by: Rob Herring (Arm) --- v4 changes: - This replaces the data-lanes property from the previous revision. Now there are separate properties for tx and rx lane maps. And instead of being the primary property for determining the number of lanes, this is only needed in special cases where the mapping is non-trivial. --- .../devicetree/bindings/spi/spi-peripheral-props.yaml | 14 ++++++++++= ++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 59ddead7da14..2f278f145f78 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -75,6 +75,13 @@ properties: enum: [0, 1, 2, 4, 8] default: [1] =20 + spi-rx-lane-map: + description: Mapping of peripheral RX lanes to controller RX lanes. + Each index in the array represents a peripheral RX lane, and the val= ue + at that index represents the corresponding controller RX lane. + $ref: /schemas/types.yaml#/definitions/uint32-array + default: [0, 1, 2, 3, 4, 5, 6, 7] + spi-rx-delay-us: description: Delay, in microseconds, after a read transfer. @@ -99,6 +106,13 @@ properties: enum: [0, 1, 2, 4, 8] default: [1] =20 + spi-tx-lane-map: + description: Mapping of peripheral TX lanes to controller TX lanes. + Each index in the array represents a peripheral TX lane, and the val= ue + at that index represents the corresponding controller TX lane. + $ref: /schemas/types.yaml#/definitions/uint32-array + default: [0, 1, 2, 3, 4, 5, 6, 7] + spi-tx-delay-us: description: Delay, in microseconds, after a write transfer. --=20 2.43.0 From nobody Sun Feb 8 13:27:49 2026 Received: from mail-ot1-f51.google.com (mail-ot1-f51.google.com [209.85.210.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30C43342519 for ; Fri, 19 Dec 2025 21:33:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180015; cv=none; b=OTOqtV5InrY8x8qgM7eM/jjBbs+cgarXqWzg8f353fTg/iyo6tZfaUD6TCplHNrQCYQjMSP0FOHyiHPGjedrXZSbSuFMjjqCjDQYHHNcf/tYDl4vjk3m0IbmAHlc7Wko70nmQ13r4Z4It/TXfxQTgbXDi88r7qLToJjBK/F7lYU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180015; c=relaxed/simple; bh=dmKDx1Fv/D9g60Hrpe80FFHumuzs/k3EreCFMwZe2ow=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=npGAAfmk8Y3zXwPNepvVBwyRB12hWpymq47IU8VFZ9DRuNpgOoYKxNyuiuZRlg8iAj+LTz2VUgDAbFM3xCaO2twoF4ri0u90GdpFfW3nLDo3f/N4bgIxW7my9fIf4ux1kasoeNT1zt+6nY9GgSDASF0dF2JugwRBhbbtxEIL7HI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=Q8fmSvkM; arc=none smtp.client-ip=209.85.210.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="Q8fmSvkM" Received: by mail-ot1-f51.google.com with SMTP id 46e09a7af769-7c77fc7c11bso2308259a34.1 for ; Fri, 19 Dec 2025 13:33:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1766180011; x=1766784811; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ovFocDuZESoFfLXGTE37+Y+HD9mVmqzpjLno5vNVGiU=; b=Q8fmSvkMRFxx5bWlYmkVUrNu4W7uwJ7aVDTySM9z74Q0BiNno/TJqLpaXzqVvYxLVd +gVTyNjDJzEt81uwjXchuXpdZes7ty7oJoAmSOooQfaPuh+9CvgNfkZo3UTfZhrd6yqC M6wUCc5wct7EcHE3OG0aFJKG08QEKDNHR5F4Ab19yJduFRtDzpC/BsEOJqUeVJptObSf d+yDdgLa6dtAyoWpayuMyW5EXThbjK0lcIlC3H3Cnf4wfKh+gousY1EXK9lX+xQzA0+6 T2PCTzoGX1llP4iWDYFFZXyDtOjTTypFhh+2EOx2vlAlH7qBtMMa52yoL/j2Z39k3vYe WtPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766180011; x=1766784811; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ovFocDuZESoFfLXGTE37+Y+HD9mVmqzpjLno5vNVGiU=; b=Jxd96xFr0B04WxI087lqVJRrG/JZ+y3z+VYhJRvNAKcCtjSf/4iR1UNMCwCOL30wlj 5Sg7N4MtqFdKecsJj7sRWt+UrDXT2k/tqf61qXi07lKFl+Emv4MfVi/LnIteO6IWgCbx vwZ41E8thStCFpbopZTiSri3otRrYyz3ECj+0zXIqSbPoOjwnQH/v8sGgAcrXqoyk4Ap H9nukow/qNhKOJ/O7hpVFzrNGBVehBV/vTJhDoxcGu+aEPhDiSXbJxyhLHLukPKxMS9d WRoTlnmMbMY2fXQDCS7dImDWpZDXxC55O1P8/QEWfTQhV4nC1I+7z+72vTmm1JYFBgYO 6hUA== X-Forwarded-Encrypted: i=1; AJvYcCUQLTSIkCxvzLAwqcHkZMwSMd82EaZ8mFsJjIqmacdQoUwdRr+CQi7XnHRgfKuWGxMXOoNxk779tC+GdHY=@vger.kernel.org X-Gm-Message-State: AOJu0YyK47l4Mj5wlubf87MXnUSaj/XV3vRhoEisfJz2Mr8jEsUaZxSm 0dGKUvpWZB2LzjUlfNbo+5emIWvjhzNDK/zm+PYOwLdjiza3rRtPS4xQEnn0tA8Ml3c= X-Gm-Gg: AY/fxX75s396V5dfyJDUEo46I0hNXPsK7fJ5zdSgYtIEEPf/ETOA8AI4N//hDWD9neT wGgHl35DW2ecGs9nJ76iQL8G5xi2EJIdgdJBqOrmn8rE7JJMnKDJ+J/r0NU3Vl6Quonmnv1D8tP wXCTJ8xccSEjcLfbNoJV8VcZnAP/SdCogIMsHTT/xV02m0FSOZQqfTWZVN5bzU7XivYxNbej3qe LPY7PzgZFLOCPEC6zyfuhLBJqXtPwbFpzz5MtO7izkdtG7wsOMq0cp7yv7QJxwk45nEqTU8hMQr i3qI/6CVhXEootDxcSs6ZlTBVXs1/huV8MrQBx3EQMBXmZNNGsMbBGiARaWUyZOwmeTDKRBMpIq XC9PIfLsOWYrObD9ybbMG4pjE5gW+6Q1bTd9cOwnjnubBMTNpDqxfNAnWy80C7lP6nxzcX64nJB L9MNYcs6BKaAaqIQ== X-Google-Smtp-Source: AGHT+IE4mrII5d5kc6to1lNBrT3gGh5165SAEtgCvCvMjJA/KpQ8Ag5b2i5DItbp06iIzxckkFNigg== X-Received: by 2002:a05:6830:314c:b0:7c7:6a56:cfb5 with SMTP id 46e09a7af769-7cc65e3a826mr2355580a34.11.1766180010938; Fri, 19 Dec 2025 13:33:30 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:9b20:bac4:9680:435]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7cc667563ffsm2485045a34.13.2025.12.19.13.33.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 13:33:30 -0800 (PST) From: David Lechner Date: Fri, 19 Dec 2025 15:32:11 -0600 Subject: [PATCH v4 3/9] spi: support controllers with multiple data lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-spi-add-multi-bus-support-v4-3-145dc5204cd8@baylibre.com> References: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> In-Reply-To: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=8962; i=dlechner@baylibre.com; h=from:subject:message-id; bh=dmKDx1Fv/D9g60Hrpe80FFHumuzs/k3EreCFMwZe2ow=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpRcR495+H4JkgnbUmwE4Y5sb4jQHQpBE3pTlSD 1CYxR4c2riJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUXEeAAKCRDCzCAB/wGP wBbgB/9iwCruGaJtA9pANY7KaVwhRBTGFCuuG6Q5kJXLFVp7vxsztqYZCxSY+uojU5VntK08fPh jUbKXDq/xkOU/zFmxmRM2a3lJU5q646qWmVabVL7P4r2SMwi9Ja29S47gyA/VaoBjPyyh+YN7Za XV4RXzMNYl/ac3So5Rfci7CH+02DO99+U4+oC9wxe/EY3F0frIT5RHOsgZmb78laHQXaHd+1XiW 9I76hLvMNHEfjaL6N7zLeOCxRmW9Fc5wAK7ZNU0CCyAont47zgRr9xUoR9MuX7SrXuylt3jPtcl YSR4XbxemwIHFIQjwdQs6lTgZS2WzqgSkyPEFJlmrw11RTn3 X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add support for SPI controllers with multiple physical SPI data lanes. (A data lane in this context means lines connected to a serializer, so a controller with two data lanes would have two serializers in a single controller). This is common in the type of controller that can be used with parallel flash memories, but can be used for general purpose SPI as well. To indicate support, a controller just needs to set ctlr->num_data_lanes to something greater than 1. Peripherals indicate which lane they are connected to via device tree (ACPI support can be added if needed). The spi-{tx,rx}-bus-width DT properties can now be arrays. The length of the array indicates the number of data lanes, and each element indicates the bus width of that lane. For now, we restrict all lanes to have the same bus width to keep things simple. Support for an optional controller lane mapping property is also implemented. Signed-off-by: David Lechner --- v4 changes: - Update for changes in devicetree bindings. - Don't put new fields in the middle of CS fields. - Dropped acks since this was a significant rework. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. This patch has been seen in a different series [1] by Sean before: [1]: https://lore.kernel.org/linux-spi/20250616220054.3968946-4-sean.anders= on@linux.dev/ Changes: * Use u8 array instead of bitfield so that the order of the mapping is preserved. (Now looks very much like chip select mapping.) * Added doc strings for added fields. * Tweaked the comments. --- drivers/spi/spi.c | 114 ++++++++++++++++++++++++++++++++++++++++++++= +++- include/linux/spi/spi.h | 22 ++++++++++ 2 files changed, 134 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index e25df9990f82..9caa22583b8f 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2370,7 +2370,52 @@ static int of_spi_parse_dt(struct spi_controller *ct= lr, struct spi_device *spi, spi->mode |=3D SPI_CS_HIGH; =20 /* Device DUAL/QUAD mode */ - if (!of_property_read_u32(nc, "spi-tx-bus-width", &value)) { + + rc =3D of_property_read_u32_array(nc, "spi-tx-lane-map", spi->tx_lane_map, + ARRAY_SIZE(spi->tx_lane_map)); + if (rc =3D=3D -EINVAL) { + /* Default lane map */ + for (idx =3D 0; idx < ARRAY_SIZE(spi->tx_lane_map); idx++) + spi->tx_lane_map[idx] =3D idx; + } else if (rc < 0) { + dev_err(&ctlr->dev, + "failed to read spi-tx-lane-map property: %d\n", rc); + return rc; + } + + rc =3D of_property_count_u32_elems(nc, "spi-tx-bus-width"); + if (rc < 0 && rc !=3D -EINVAL) { + dev_err(&ctlr->dev, + "failed to read spi-tx-bus-width property: %d\n", rc); + return rc; + } + + if (rc =3D=3D -EINVAL) { + /* Default when property is not present. */ + spi->num_tx_lanes =3D 1; + } else { + u32 first_value; + + spi->num_tx_lanes =3D rc; + + for (idx =3D 0; idx < spi->num_tx_lanes; idx++) { + of_property_read_u32_index(nc, "spi-tx-bus-width", idx, + &value); + + /* + * For now, we only support all lanes having the same + * width so we can keep using the existing mode flags. + */ + if (!idx) + first_value =3D value; + else if (first_value !=3D value) { + dev_err(&ctlr->dev, + "spi-tx-bus-width has inconsistent values: first %d vs later %d\n", + first_value, value); + return -EINVAL; + } + } + switch (value) { case 0: spi->mode |=3D SPI_NO_TX; @@ -2394,7 +2439,61 @@ static int of_spi_parse_dt(struct spi_controller *ct= lr, struct spi_device *spi, } } =20 - if (!of_property_read_u32(nc, "spi-rx-bus-width", &value)) { + for (idx =3D 0; idx < spi->num_tx_lanes; idx++) { + if (spi->tx_lane_map[idx] >=3D spi->controller->num_data_lanes) { + dev_err(&ctlr->dev, + "spi-tx-lane-map has invalid value %d (num_data_lanes=3D%d)\n", + spi->tx_lane_map[idx], + spi->controller->num_data_lanes); + return -EINVAL; + } + } + + rc =3D of_property_read_u32_array(nc, "spi-rx-lane-map", spi->rx_lane_map, + ARRAY_SIZE(spi->rx_lane_map)); + if (rc =3D=3D -EINVAL) { + /* Default lane map */ + for (idx =3D 0; idx < ARRAY_SIZE(spi->rx_lane_map); idx++) + spi->rx_lane_map[idx] =3D idx; + } else if (rc < 0) { + dev_err(&ctlr->dev, + "failed to read spi-rx-lane-map property: %d\n", rc); + return rc; + } + + rc =3D of_property_count_u32_elems(nc, "spi-rx-bus-width"); + if (rc < 0 && rc !=3D -EINVAL) { + dev_err(&ctlr->dev, + "failed to read spi-rx-bus-width property: %d\n", rc); + return rc; + } + + if (rc =3D=3D -EINVAL) { + /* Default when property is not present. */ + spi->num_rx_lanes =3D 1; + } else { + u32 first_value; + + spi->num_rx_lanes =3D rc; + + for (idx =3D 0; idx < spi->num_rx_lanes; idx++) { + of_property_read_u32_index(nc, "spi-rx-bus-width", idx, + &value); + + /* + * For now, we only support all lanes having the same + * width so we can keep using the existing mode flags. + */ + if (!idx) + first_value =3D value; + else if (first_value !=3D value) { + dev_err(&ctlr->dev, + "spi-rx-bus-width has inconsistent values: first %d vs later %d\n", + first_value, value); + return -EINVAL; + } + } + switch (value) { case 0: spi->mode |=3D SPI_NO_RX; @@ -2418,6 +2517,16 @@ static int of_spi_parse_dt(struct spi_controller *ct= lr, struct spi_device *spi, } } =20 + for (idx =3D 0; idx < spi->num_rx_lanes; idx++) { + if (spi->rx_lane_map[idx] >=3D spi->controller->num_data_lanes) { + dev_err(&ctlr->dev, + "spi-rx-lane-map has invalid value %d (num_data_lanes=3D%d)\n", + spi->rx_lane_map[idx], + spi->controller->num_data_lanes); + return -EINVAL; + } + } + if (spi_controller_is_target(ctlr)) { if (!of_node_name_eq(nc, "slave")) { dev_err(&ctlr->dev, "%pOF is not called 'slave'\n", @@ -3066,6 +3175,7 @@ struct spi_controller *__spi_alloc_controller(struct = device *dev, mutex_init(&ctlr->add_lock); ctlr->bus_num =3D -1; ctlr->num_chipselect =3D 1; + ctlr->num_data_lanes =3D 1; ctlr->target =3D target; if (IS_ENABLED(CONFIG_SPI_SLAVE) && target) ctlr->dev.class =3D &spi_target_class; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index cb2c2df31089..7aff60ab257e 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -23,6 +23,9 @@ /* Max no. of CS supported per spi device */ #define SPI_DEVICE_CS_CNT_MAX 4 =20 +/* Max no. of data lanes supported per spi device */ +#define SPI_DEVICE_DATA_LANE_CNT_MAX 8 + struct dma_chan; struct software_node; struct ptp_system_timestamp; @@ -174,6 +177,10 @@ extern void spi_transfer_cs_change_delay_exec(struct s= pi_message *msg, * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect = array * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect li= nes * (optional, NULL when not using a GPIO line) + * @tx_lane_map: Map of peripheral lanes (index) to controller lanes (valu= e). + * @num_tx_lanes: Number of transmit lanes wired up. + * @rx_lane_map: Map of peripheral lanes (index) to controller lanes (valu= e). + * @num_rx_lanes: Number of receive lanes wired up. * * A @spi_device is used to interchange data between an SPI target device * (usually a discrete chip) and CPU memory. @@ -242,6 +249,12 @@ struct spi_device { =20 struct gpio_desc *cs_gpiod[SPI_DEVICE_CS_CNT_MAX]; /* Chip select gpio de= sc */ =20 + /* Multi-lane SPI controller support. */ + u32 tx_lane_map[SPI_DEVICE_DATA_LANE_CNT_MAX]; + u32 num_tx_lanes; + u32 rx_lane_map[SPI_DEVICE_DATA_LANE_CNT_MAX]; + u32 num_rx_lanes; + /* * Likely need more hooks for more protocol options affecting how * the controller talks to each chip, like: @@ -401,6 +414,7 @@ extern struct spi_device *spi_new_ancillary_device(stru= ct spi_device *spi, u8 ch * SPI targets, and are numbered from zero to num_chipselects. * each target has a chipselect signal, but it's common that not * every chipselect is connected to a target. + * @num_data_lanes: Number of data lanes supported by this controller. Def= ault is 1. * @dma_alignment: SPI controller constraint on DMA buffers alignment. * @mode_bits: flags understood by this controller driver * @buswidth_override_bits: flags to override for this controller driver @@ -576,6 +590,14 @@ struct spi_controller { */ u16 num_chipselect; =20 + /* + * Some specialized SPI controllers can have more than one physical + * data lane interface per controller (each having it's own serializer). + * This specifies the number of data lanes in that case. Other + * controllers do not need to set this (defaults to 1). + */ + u16 num_data_lanes; + /* Some SPI controllers pose alignment requirements on DMAable * buffers; let protocol drivers know about these requirements. */ --=20 2.43.0 From nobody Sun Feb 8 13:27:49 2026 Received: from mail-ot1-f46.google.com (mail-ot1-f46.google.com [209.85.210.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3695A34404B for ; Fri, 19 Dec 2025 21:33:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180015; cv=none; b=WTb/dWibX3DCacxhn1KvKTVEX5qtIOpYdCa+b+4VXeDw66b6RXGlLsS3ycpkLdyo8E12tQf8haAShF0wCUw4P84swDsancVe6JShI/a54U7Q3xTvbCqVGvvOKb8A6rVErfoCUtZ20Vq/Rp6pOg6c7C2+N4xlv/NZ5vgD56XUO4c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180015; c=relaxed/simple; bh=HF+bpVOoavKKEiID/RQ+Z83xMg2SKTxpfDjYlJ/W1Xc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FrjNLUC39TmlKMAErmMliIZMYU1vm+YAKF+/s+zdFHuBxVSBbeW/a+2DpddCtfReHnMfSmpI96PcamFpz24oIvJwpZmn6cCPXUQebzs8J2M+WoriQHLQrMLNHRc/iqiVob16mQHeTWIWigQlxU5NdZpkBdI0PCA+Lfzjwxbr5ZM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=VZwytgSd; arc=none smtp.client-ip=209.85.210.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="VZwytgSd" Received: by mail-ot1-f46.google.com with SMTP id 46e09a7af769-7cac8243bcdso1498766a34.3 for ; Fri, 19 Dec 2025 13:33:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1766180012; x=1766784812; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ne4Oc3piCV35xap5V5Dxt0Rd9if75XR+emO/qCvC+Q0=; b=VZwytgSdqbdqi4fWcqWhvq5PMxlklNBPWvGygLp/ifYE+VwqNxgdoKWsMe0LRjvNH3 6mfx5OOCTK4/qE17vMnHKo/d1c4EsmjeyfWI/z6a6kQ+Un+qDOuWbY7aHj2R1h7b+UR4 uwUt3LUL/wirEHw3r4fcnHEQamzp/Q5fsKSKpV7g4i8xhK1khsYYEYIOA4RHAnUx8jub rM3hbOslOL9XHas6Hxg52G8XfTBlSRGIKQIOKHBOPA0EZL/CRLIptK8diwnmomMVMfZx XnXXBXmEBrprRlcyVSXE8PPIAlikkM1GZ3XED2y4BN7BQ3+uB/IkJwBc8lE63Zpf4Vfx L5OA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766180012; x=1766784812; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ne4Oc3piCV35xap5V5Dxt0Rd9if75XR+emO/qCvC+Q0=; b=j4ETLlDMJ9/coj4c/2K/If34CT76RWqcgjCVcIOVMtBvUV1vfdMoiTDj7MlAg9qbPF y/PbyUKwu/QyjrikijDeXrrxev3fFEexGWOdnh+yQ/o6iB4MDiXGCo7vFJvJSmprviJd H122BxKXwZhB/kBJKPtI3xnjRw8ilVbul7eXgJngI8z4xEmqeNu+4LgYeD5sFyZEPip5 2gRIwQht7/VXuylwjig1T2lxV5zj3aSy/7I3IeCvNsITKviDvWFZCcXqpXmNGmOP4FdL qugvThndrY1yMN2oiZk2VSr9N/EUuipAEOdJ/seIHkcvZPhJFxIexOhuwaxuw2xQyeeC 8TKw== X-Forwarded-Encrypted: i=1; AJvYcCX3lWfdmB+RpHeVuivzIO8UNxqVPmHAT2aZbKv91U5hcNQrluMrTUgfOCEMQVXf4GmdibnOaPdwsPNKMJs=@vger.kernel.org X-Gm-Message-State: AOJu0YxE4NHXU9innJ4gKj64DaGBJPERxJHu1IAHmZ3/BeWx0/aW+UoO WyNnKYxj8ULbvef9ecITlYOLkYNVkDJ4yUOT+UoFA5j7ZD2qEou3lrwAt47OD7lOVcY= X-Gm-Gg: AY/fxX72iMLe4lq4yfn+lHM/4PevkddycHQNSiz0D1XXwa1l3KtLYmABC0YO3g50Ug6 oThemUd/L6qgBmGLg6mdhAcGN1cltbm70HXg9vbPfCF1+s06ebGSuf1Ie/Nk8C94JpRwLftBB5G GIU8LBT6DZnchTZcGibJmRjd39Eb6Dp0ILTIJn3zxTjUd7DnhIMwGkgJ8J4Wpeph0wOt/VmVSEI cQqeDZa2Mt4So7twU71wf5d7rue9fINNUMpbw/8JDhC9b4dKS260/5i9OIFM8N+bn7v5UNHYDjm GkR77BtwBo5AknCmS5AS3/21QVOqpkxHb9csAVHhS8BxnA7SgZ/6PoWm55EMN+/HA9+Tnl4YTo4 /Om0zHkasO1F7vyHg7ySaW347P2L4uLWhokow6eyQlSCSp6h2trtIWu0ogR31MczH5+pII112+H SG/M1Ozfa/edATBg== X-Google-Smtp-Source: AGHT+IE2okvpXZy3o6zspy8E6CK06vVwfK3mCEFz5O+h1kF5N8ELNZpYKpcp/La4JjKRWaZGwXF+SQ== X-Received: by 2002:a05:6830:61cd:b0:7c7:68d8:f702 with SMTP id 46e09a7af769-7cc66a1dba8mr2393869a34.9.1766180011918; Fri, 19 Dec 2025 13:33:31 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:9b20:bac4:9680:435]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7cc667563ffsm2485045a34.13.2025.12.19.13.33.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 13:33:31 -0800 (PST) From: David Lechner Date: Fri, 19 Dec 2025 15:32:12 -0600 Subject: [PATCH v4 4/9] spi: add multi_lane_mode field to struct spi_transfer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-spi-add-multi-bus-support-v4-4-145dc5204cd8@baylibre.com> References: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> In-Reply-To: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2028; i=dlechner@baylibre.com; h=from:subject:message-id; bh=HF+bpVOoavKKEiID/RQ+Z83xMg2SKTxpfDjYlJ/W1Xc=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpRcR+63tdWe3Dq3SfvXY3D0UkrPjsmJVZFWlyp BqDw/0tCMmJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUXEfgAKCRDCzCAB/wGP wOGIB/9gDadU5FGpX/q+RfD4+syl1wJV6/ulWqJD9resnhlPcBddMNNewxrCTlQzqHoDNEykqXP UUmVd5SACUC3AZSssyZBsslhEQocLCVAa3iva4W3O2+/h1GT4ya9ybBeBIc7w8LDWNDD/zmRrbZ s/lWNOWZzX9JGe4N5XjlJrKkB0HeNOix8mXpwsV/CpU8dsu/P6+swv1W00XnXbO+jiefVDge8cw fbpCdq5O3mqVDt9g1PJtEybbNEwtYCHG+39/nwgeLReOx0c0viMXFax17jLzpvGsudDcrFzG22g 8jIJFdxSFmnsx2yObmQfVg/DjuB43howiLEr3a5CzYwxfuPG X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add a new multi_lane_mode field to struct spi_transfer to allow peripherals that support multiple SPI lanes to be used with a single SPI controller. This requires both the peripheral and the controller to have multiple serializers connected to separate data lanes. It could also be used with a single controller and multiple peripherals that are functioning as a single logical device (similar to parallel memories). Acked-by: Nuno S=C3=A1 Acked-by: Marcelo Schmitt Signed-off-by: David Lechner --- v4 changes: * Shortened commit message (useful info will be in docs instead). * Added whitespace to create clear grouping of macros and the field. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. --- include/linux/spi/spi.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 7aff60ab257e..eba7ae8466ac 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -981,6 +981,8 @@ struct spi_res { * (SPI_NBITS_SINGLE) is used. * @rx_nbits: number of bits used for reading. If 0 the default * (SPI_NBITS_SINGLE) is used. + * @multi_lane_mode: How to serialize data on multiple lanes. One of the + * SPI_MULTI_LANE_MODE_* values. * @len: size of rx and tx buffers (in bytes) * @speed_hz: Select a speed other than the device default for this * transfer. If 0 the default (from @spi_device) is used. @@ -1117,6 +1119,12 @@ struct spi_transfer { unsigned cs_change:1; unsigned tx_nbits:4; unsigned rx_nbits:4; + +#define SPI_MULTI_LANE_MODE_SINGLE 0 /* only use single lane */ +#define SPI_MULTI_LANE_MODE_STRIPE 1 /* one data word per lane */ +#define SPI_MULTI_LANE_MODE_MIRROR 2 /* same word sent on all lanes */ + unsigned multi_lane_mode: 2; + unsigned timestamped:1; bool dtr_mode; #define SPI_NBITS_SINGLE 0x01 /* 1-bit transfer */ --=20 2.43.0 From nobody Sun Feb 8 13:27:49 2026 Received: from mail-ot1-f67.google.com (mail-ot1-f67.google.com [209.85.210.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F3CB345733 for ; Fri, 19 Dec 2025 21:33:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.67 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180017; cv=none; b=Fd+g+RlzxdkdUu4+vg7bFgQegRG3UyRMqvuVhtr1q9vhdTEgbLg6Ws6HpdUrUGk/0N3Qpntc4/62shmVKa1FHtOMiExY+iCLzYRUrx2WQC5czDa0p8jVvGskV71BufhgQCmP5gRJMb6vxScajnXiI5401zUanCHdLih0c6MSbac= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180017; c=relaxed/simple; bh=aXmv3z0/ZmZ8Ofn+73gLo6clj9Ab1P+H1oMNVIM3T5w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=efY5TtEd2Ae0XL5FZpSGfGBMnhip70QOPt0UanAWqLLVlXWQwCInhS29dgMUMqvgmfKSDwBKxlnVLwQQ2fO5aBuJtsB72s70ikQuJ7pC0W9Ac7fGSoGz7asgnZpg4QVTpSAfXYxjyvupIT+8XjlJkya5AYOg+Ojt9RZEi/gyIXg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=ST1yCF7g; arc=none smtp.client-ip=209.85.210.67 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="ST1yCF7g" Received: by mail-ot1-f67.google.com with SMTP id 46e09a7af769-7caf5314847so1438495a34.0 for ; Fri, 19 Dec 2025 13:33:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1766180013; x=1766784813; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=eweM9jT54taVa0b1bGSFhKXxW1qHo1mGh87AZPt1Jc8=; b=ST1yCF7g+t4Bs3yMoDGwjx/XZ7N37nbRfgPYLpbP9cZAem7zVP1TXtRVcQJjG0nMeD 9EI/fGKVr6swS5GVPoThrYF48O9J6fPq8FARYNsjkfXqwHS8pjIW3O2+SSOcR6/Ll81X XEGj0XGoVCxKbb12+Kcbw6eJ9GJXs7ERGZLrMdnQH74Rc8WiSXnqlD//U0tuU52LPg+Q kMty/Y9vd7wsql0IPZKDTUFgLEOKs0qjqb/ny9Q/z20u7VpgvbLohe+HFndMyeJmydBb vjmKpQAVXPOZmVHZJ2L5JztnZtxiCrw0IUhxN5b+Gdd+69zOZZfMROivQAMB9kACyQej acqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766180013; x=1766784813; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=eweM9jT54taVa0b1bGSFhKXxW1qHo1mGh87AZPt1Jc8=; b=wh8zuLYTf/maYXJaFZovZklXeC2Wu29hBk9YMd5MWqMi9huxMp0gepFuNkgLKatoL/ 9QLzvk4hApkPD+L1eXB7zWbinhaGdwqvYfPEiEQA8Eja7ZP8D2s5CwdjxdXnccMkatIF IpU9iMBhcqxlzbG7XsyCpjVDM2RHD/hcFz/cF30CR1iKEYIPK1KIOphexkMTLtrsv4Wf AHCqHrPQmW56Qhjeov5346fSvkxD8lgzLeg1e7KjFjE/noX+NvniMrTmba71EfIbx4NV fV8WcFraqWTgw789FG8bVKHqJUcij8bQbq+lD33ORdhnv2TF83kV4q1kHpYAH6V9BMQA Ai8w== X-Forwarded-Encrypted: i=1; AJvYcCWVy9qOV7jLlrcqwGECZKJN1+eGwleRvGua7AI7hUn+BJBLUev2wD9RAoVNNQzHJMGQtryvhfdTj8CUhBg=@vger.kernel.org X-Gm-Message-State: AOJu0YyaV6OHIuzYrdTcHU+iC+mH2+dedYAXEQ3r5KYBK0DsCgx94jIo gbV0z11qYIZvA3yKFGRigxEyz0p6vAGiVY75b6nX/zX8nVQC2cWme9RCI7vl/6+tW8k= X-Gm-Gg: AY/fxX5BUWNeG/VoIv5v4Z6ifxnJQ/axmctl6byu/Lx1vEUH5EKXNW2cRELkszF3iXu +hu12mGVZ/ztkB/CGsptrCSM7hNHEPJjJf9WW7Dt0vr46v2wwI/lxBHQF6B6RTEJvqkclb0G63c tko8Chgb9nbitzVKOwMps26FfVCdlTtbHdfOkFQhkxaTypcD0pKHtkVfDfj+QFts+02QF4BrZV+ Y57ZFUm5d589EsctfBGyYRmday6oQ9ftU4Jy8cBp76qLYmNOmuz1zOMfTgb1nUE+o8EjKCZYagI nFCAxTwqZvZoxA2PU431GQ9iBdsY1pn2sNGvY7B/nJFjZBcTFtmrB4v9T9w1OFD5RRgNiI2zejz Wd1/KeBDlboMs+05itWgdaCo3Y7HtgzFImps67AryDPBy7aKh1w8ClT8f0LsMgeRbmB6v26t4WJ 5zRZfxuOC7ZtDQ4w== X-Google-Smtp-Source: AGHT+IHPFvj1q6b2mgObZX2EPwKdIr9WKAX+NXfMIaaHSJz/qkfbu5KspscVUz1GusDDrfj5q+9c9g== X-Received: by 2002:a05:6830:348e:b0:7c7:7099:97f4 with SMTP id 46e09a7af769-7cc66a0b759mr2556677a34.3.1766180012868; Fri, 19 Dec 2025 13:33:32 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:9b20:bac4:9680:435]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7cc667563ffsm2485045a34.13.2025.12.19.13.33.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 13:33:32 -0800 (PST) From: David Lechner Date: Fri, 19 Dec 2025 15:32:13 -0600 Subject: [PATCH v4 5/9] spi: Documentation: add page on multi-lane support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-spi-add-multi-bus-support-v4-5-145dc5204cd8@baylibre.com> References: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> In-Reply-To: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=8776; i=dlechner@baylibre.com; h=from:subject:message-id; bh=aXmv3z0/ZmZ8Ofn+73gLo6clj9Ab1P+H1oMNVIM3T5w=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpRcSEM0oStjcDbIK619jZO9EATivi9D0G3dcSV GNICFSEiX6JATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUXEhAAKCRDCzCAB/wGP wCFsB/9QJ/fcbtVgn+HO+hBBx1tEvp5ySdzkcwkzDiGAssEzMNHo8uTKZmxJyoDtrUIBO+jsSdE j18VCARzcVSgwD2yDlewF6LxJiOEL1vj3sVhXGSOOPjm5/kpyLkYzNpebDkQ7CMDuZOfhPlUgPN EpHoL5AANmiK9C0Feq7jON7Y74OtA2FB/NlhTG43NUrYLvY5SgxXt/6bK42i1nelwsd723PeRHl dBthSlqkr7T93HuhQEnN9Lmpxkrq4ZiHaB7S3ADa9fI1iXPjt8lx0J4vig69hpN1wd/zzvIKTwT Bj0j+FWsVJo0uQhI7nDiHAhRnDxxN2aFz9QKDCVKlYoogykf X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add a new page to Documentation/spi/ describing how multi-lane SPI support works. This is uncommon functionality so it deserves its own documentation page. Signed-off-by: David Lechner Reviewed-by: Marcelo Schmitt --- v4 changes: * New patch in v4. --- Documentation/spi/index.rst | 1 + Documentation/spi/multiple-data-lanes.rst | 217 ++++++++++++++++++++++++++= ++++ 2 files changed, 218 insertions(+) diff --git a/Documentation/spi/index.rst b/Documentation/spi/index.rst index 824ce42ed4f0..2c89b1ee39e2 100644 --- a/Documentation/spi/index.rst +++ b/Documentation/spi/index.rst @@ -9,6 +9,7 @@ Serial Peripheral Interface (SPI) =20 spi-summary spidev + multiple-data-lanes butterfly spi-lm70llp spi-sc18is602 diff --git a/Documentation/spi/multiple-data-lanes.rst b/Documentation/spi/= multiple-data-lanes.rst new file mode 100644 index 000000000000..b267f31f0bc8 --- /dev/null +++ b/Documentation/spi/multiple-data-lanes.rst @@ -0,0 +1,217 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +SPI devices with multiple data lanes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Some specialized SPI controllers and peripherals support multiple data lan= es +that allow reading more than one word at a time in parallel. This is diffe= rent +from dual/quad/octal SPI where multiple bits of a single word are transfer= red +simultaneously. + +For example, controllers that support parallel flash memories have this fe= ature +as do some simultaneous-sampling ADCs where each channel has its own data = lane. + +--------------------- +Describing the wiring +--------------------- + +The ``spi-tx-bus-width`` and ``spi-rx-bus-width`` properties in the device= tree +are used to describe how many data lanes are connected between the control= ler +and how wide each lane is. The number of items in the array indicates how = many +lanes there are, and the value of each item indicates how many bits wide t= hat +lane is. + +For example, a dual-simultaneous-sampling ADC with two 4-bit lanes might be +wired up like this:: + + +--------------+ +----------+ + | SPI | | AD4630 | + | Controller | | ADC | + | | | | + | CS0 |--->| CS | + | SCK |--->| SCK | + | SDO |--->| SDI | + | | | | + | SDIA0 |<---| SDOA0 | + | SDIA1 |<---| SDOA1 | + | SDIA2 |<---| SDOA2 | + | SDIA3 |<---| SDOA3 | + | | | | + | SDIB0 |<---| SDOB0 | + | SDIB1 |<---| SDOB1 | + | SDIB2 |<---| SDOB2 | + | SDIB3 |<---| SDOB3 | + | | | | + +--------------+ +----------+ + +It is described in a devicetree like this:: + + spi { + compatible =3D "my,spi-controller"; + + ... + + adc@0 { + compatible =3D "adi,ad4630"; + reg =3D <0>; + ... + spi-rx-bus-width =3D <4>, <4>; /* 2 lanes of 4 bits each */ + ... + }; + }; + +In most cases, lanes will be wired up symmetrically (A to A, B to B, etc).= If +this isn't the case, extra ``spi-rx-bus-width`` and ``spi-tx-bus-width`` +properties are needed to provide a mapping between controller lanes and the +physical lane wires. + +Here is an example where a multi-lane SPI controller has each lane wired to +separate single-lane peripherals:: + + +--------------+ +----------+ + | SPI | | Thing 1 | + | Controller | | | + | | | | + | CS0 |--->| CS | + | SDO0 |--->| SDI | + | SDI0 |<---| SDO | + | SCLK0 |--->| SCLK | + | | | | + | | +----------+ + | | + | | +----------+ + | | | Thing 2 | + | | | | + | CS1 |--->| CS | + | SDO1 |--->| SDI | + | SDI1 |<---| SDO | + | SCLK1 |--->| SCLK | + | | | | + +--------------+ +----------+ + +This is described in a devicetree like this:: + + spi { + compatible =3D "my,spi-controller"; + + ... + + thing1@0 { + compatible =3D "my,thing1"; + reg =3D <0>; + ... + }; + + thing2@1 { + compatible =3D "my,thing2"; + reg =3D <1>; + ... + spi-tx-lane-map =3D <1>; /* lane 0 is not used, lane 1 is used= for tx wire */ + spi-rx-lane-map =3D <1>; /* lane 0 is not used, lane 1 is used= for rx wire */ + ... + }; + }; + + +The default values of ``spi-rx-bus-width`` and ``spi-tx-bus-width`` are ``= <1>``, +so these properties can still be omitted even when ``spi-rx-lane-map`` and +``spi-tx-lane-map`` are used. + +---------------------------- +Usage in a peripheral driver +---------------------------- + +These types of SPI controllers generally do not support arbitrary use of t= he +multiple lanes. Instead, they operate in one of a few defined modes. Perip= heral +drivers should set the :c:type:`struct spi_transfer.multi_lane_mode ` +field to indicate which mode they want to use for a given transfer. + +The possible values for this field have the following semantics: + +- :c:macro:`SPI_MULTI_BUS_MODE_SINGLE`: Only use the first lane. Other lan= es are + ignored. This means that it is operating just like a conventional SPI + peripheral. This is the default, so it does not need to be explicitly = set. + + Example:: + + tx_buf[0] =3D 0x88; + + struct spi_transfer xfer =3D { + .tx_buf =3D tx_buf, + .len =3D 1, + }; + + spi_sync_transfer(spi, &xfer, 1); + + Assuming the controller is sending the MSB first, the sequence of bits + sent over the tx wire would be (right-most bit is sent first):: + + controller > data bits > peripheral + ---------- ---------------- ---------- + SDO 0 0-0-0-1-0-0-0-1 SDI 0 + +- :c:macro:`SPI_MULTI_BUS_MODE_MIRROR`: Send a single data word over all o= f the + lanes at the same time. This only makes sense for writes and not + for reads. + + Example:: + + tx_buf[0] =3D 0x88; + + struct spi_transfer xfer =3D { + .tx_buf =3D tx_buf, + .len =3D 1, + .multi_lane_mode =3D SPI_MULTI_BUS_MODE_MIRROR, + }; + + spi_sync_transfer(spi, &xfer, 1); + + The data is mirrored on each tx wire:: + + controller > data bits > peripheral + ---------- ---------------- ---------- + SDO 0 0-0-0-1-0-0-0-1 SDI 0 + SDO 1 0-0-0-1-0-0-0-1 SDI 1 + +- :c:macro:`SPI_MULTI_BUS_MODE_STRIPE`: Send or receive two different data= words + at the same time, one on each lane. This means that the buffer needs t= o be + sized to hold data for all lanes. Data is interleaved in the buffer, w= ith + the first word corresponding to lane 0, the second to lane 1, and so o= n. + Once the last lane is used, the next word in the buffer corresponds to= lane + 0 again. Accordingly, the buffer size must be a multiple of the number= of + lanes. This mode works for both reads and writes. + + Example:: + + struct spi_transfer xfer =3D { + .rx_buf =3D rx_buf, + .len =3D 2, + .multi_lane_mode =3D SPI_MULTI_BUS_MODE_STRIPE, + }; + + spi_sync_transfer(spi, &xfer, 1); + + Each tx wire has a different data word sent simultaneously:: + + controller < data bits < peripheral + ---------- ---------------- ---------- + SDI 0 0-0-0-1-0-0-0-1 SDO 0 + SDI 1 1-0-0-0-1-0-0-0 SDO 1 + + After the transfer, ``rx_buf[0] =3D=3D 0x11`` (word from SDO 0) and + ``rx_buf[1] =3D=3D 0x88`` (word from SDO 1). + + +----------------------------- +SPI controller driver support +----------------------------- + +To support multiple data lanes, SPI controller drivers need to set +:c:type:`struct spi_controller.num_data_lanes ` to a value +greater than 1. + +Then the part of the driver that handles SPI transfers needs to check the +:c:type:`struct spi_transfer.multi_lane_mode ` field and imp= lement +the appropriate behavior for each supported mode and return an error for +unsupported modes. + +The core SPI code should handle the rest. --=20 2.43.0 From nobody Sun Feb 8 13:27:49 2026 Received: from mail-ot1-f52.google.com (mail-ot1-f52.google.com [209.85.210.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9A4F346766 for ; Fri, 19 Dec 2025 21:33:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180018; cv=none; b=VGNhH3poL9+q4KHW7LVr/fVI7qRMJ8W+DdiSC0x+EumUn/L/4qR6+634JhNxw/Er8TTTbPnl/WsTlWLKmLYHfFMx8DYgrslxSScySBr/NkQ38yYx71OhaQFxuTQx6k0ttfrd0FgoHnA1Gm4ecCKlaVjEXuEXlQyqyweQQioRnv4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180018; c=relaxed/simple; bh=oWBMnPrpGrThotMU9ljfUzKqVANXXO/+7KS1FgC4pbU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U9BRYrOf0UVplfw8aanZnDcVKjE4cUt0lGaaLEjapwl0ZOQQQ9kQbM//eYjPm5XwweSF+/ku/6Cu+F+SSfN0fLrwjeaRi1Z3nBX3s4dQ2moGfcszcAzzipNPYAoSPTOBn1a0G/XPhanoFT8B9uriebQxPy9cxtMHZFKtQp4GdXY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=Stqqz4GK; arc=none smtp.client-ip=209.85.210.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="Stqqz4GK" Received: by mail-ot1-f52.google.com with SMTP id 46e09a7af769-7c7533dbd87so1816572a34.2 for ; Fri, 19 Dec 2025 13:33:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1766180014; x=1766784814; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=fFWC+IDcRXjpxDjHpjRJWViF/+dbpWmpywiH9Uy/XS4=; b=Stqqz4GKT+59W2DorQQhmiqjT+F3zH3fy0eW9KKs049D5jUlLW2pgnmphlMbxKq+PH o5iv4XBZg0JLRfDAsdyJoBdZm1PHHr2WRs66y95h1QClWcO624IbTCwznkmOrQoCr+T8 sAP4LYvzxUD3RYmAvf7IlK9KGNWXH0hFcroPKzgddZ/xtDTOcp3WZWGs2241SdPnEJAS jKaper2njD02W9hkyaam6f6/zseaKc+m1OHXM1A7u9RQxJBNhMBRchrrueUhh9QBWtsA 4+Wv3sQp6I+IBu5EAQ9iH8Tl7lhWpjnaKWbxFEDE20dzD4wVFj/+sl6kELv2LL5g7voc 3rig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766180014; x=1766784814; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=fFWC+IDcRXjpxDjHpjRJWViF/+dbpWmpywiH9Uy/XS4=; b=udRofbUy30bcAyB7DRP0wk20xzVqCxGFORXxpq0u/5nxpeGrTmK1NuYTKY/W2v3jA4 akAzLKwOXyzNqCy5QH4LIyJMfGCPOAadg9bxJovTFnabbXU6XO8MkJPKKmiN2rJk5dKI tJVqaZt79USyGso+eXUPg0T+l1PhM6fFkHPRD51TkYyY+RewwDP5Wzvh0A5RKRPLFrKh D6uh7k4EdoFON3fGAoBFfRYNtJ+7pd/UgxdHU6ILDujvN99pnIotXIbkJ3W2uBc22EgF x3emh7LgeqHnECyQfL/uoEDzqaXC8LC87D5ZgO2Z/XjWYhemgsLYAVHDO/uysFiTf0r2 iW7A== X-Forwarded-Encrypted: i=1; AJvYcCVX8q+Tck+dk4lTiTd8poQTR+aHUKXYLu8jXyJe3CKj+e5tiNIbakSytHuQRMSFpTGIck/iXgs3HAbfKQ4=@vger.kernel.org X-Gm-Message-State: AOJu0YwKRwRVXzV+xinV5A2uBpn3+htEVRHKoPSN6gDeK8jmFqFWjIO2 Z/VcBS4LtGayBOo/5OMHZlD2+3aJmdzEbAKJaPPH4FVquJ3rcE1ydiWhgRkP9HK1YaI= X-Gm-Gg: AY/fxX77seiVTmW96fg9IMvLM0VMR59Azl9Prn5HI/w8jK12evDtHMEldMwbMTjHi0q Qd8U3Q6cnyaH9eJ7kp7WoWZ49YTtqVb0p4K79a0mHZCx41IlxbIPeLfV6yL6ADSkyebks08eSxL i0/4lCoC0JIxM4+IQbdPlLF6mHAbwou4OyyFAHLD+pAoS6uptgLCYNea9UsA0k/f3cFoyawBtX9 T2kIr91w82mgCN/J5AGOAAvGORctOCq/5rop1g8uI8QHI1jOelSzppZ41f2284Q7GSmRuaGlS1z L+9wzwX4IJj6K71Fg416vcvFYiqGtCfar9NBTWqxaSnNa3I1HSUgPBHE+2Cd76SvRtx1ztaETQM qYODqkI8tufc+HfKskQ9QUescTWp4Hjo0lTEOAzuirXMiDQcU4lSXgKQr1Y6lH1R0zllCAfx8Q/ CvFglbmV4xHLLftw== X-Google-Smtp-Source: AGHT+IFSpfHhi8xxfC0/N+lQDDvFqU6CV+t6PQI2c4qXO1CuJXBevV+MJgay8gDTRAmgQdttKD28IA== X-Received: by 2002:a05:6830:3698:b0:745:4823:df18 with SMTP id 46e09a7af769-7cc66a468ebmr2322063a34.28.1766180014080; Fri, 19 Dec 2025 13:33:34 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:9b20:bac4:9680:435]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7cc667563ffsm2485045a34.13.2025.12.19.13.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 13:33:33 -0800 (PST) From: David Lechner Date: Fri, 19 Dec 2025 15:32:14 -0600 Subject: [PATCH v4 6/9] spi: dt-bindings: adi,axi-spi-engine: add multi-lane support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-spi-add-multi-bus-support-v4-6-145dc5204cd8@baylibre.com> References: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> In-Reply-To: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1281; i=dlechner@baylibre.com; h=from:subject:message-id; bh=oWBMnPrpGrThotMU9ljfUzKqVANXXO/+7KS1FgC4pbU=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpRcSLtwISQYxTcnaJJr2o02veAMLBoy2FoWzP5 60rfky7QuyJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUXEiwAKCRDCzCAB/wGP wIPTB/9h97F8n43Ys3AHntQjx9qaoojBkCy4jOBYYNtyayieVmxE5ACYWaMaGe0VbWRtbg5cNtG N9065hQHhag+a0u1tEMj/gyZUGofi1OnwAReLtytYmoqF1T9hn+pfYdGDGGvIPHz7xyup90RHf5 F5vr+KcwTBI3Hi4UJBiWh3gHE+8mz2UtsneF9YnL1n14coim2fEolihN9D2HMP/+qmTSkAHf4NT tIQCLkRZRDgAi8zWG84QPH3arkcvPwoxGdPC5Mde9Di/kP8W1RWAfMJZHuI5KFPs6fHquv2zsBJ eUVTihWS6VP4QkML2tUJheSYh6rHcoz/wlW5EHTdrq4Rnay4 X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Extend the ADI AXI SPI engine binding for multiple data lanes. This SPI controller has a capability to read multiple data words at the same time (e.g. for use with simultaneous sampling ADCs). The current FPGA implementation can support up to 8 data lanes at a time (depending on a compile-time configuration option). Signed-off-by: David Lechner Reviewed-by: Rob Herring (Arm) --- v4 changes: - Update to use spi-{tx,rx}-bus-width properties. --- .../devicetree/bindings/spi/adi,axi-spi-engine.yaml | 15 +++++++++++= ++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml = b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml index 4b3828eda6cb..0f2448371f17 100644 --- a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml +++ b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml @@ -70,6 +70,21 @@ required: =20 unevaluatedProperties: false =20 +patternProperties: + "^.*@[0-9a-f]+": + type: object + + properties: + spi-rx-bus-width: + maxItems: 8 + items: + enum: [0, 1] + + spi-tx-bus-width: + maxItems: 8 + items: + enum: [0, 1] + examples: - | spi@44a00000 { --=20 2.43.0 From nobody Sun Feb 8 13:27:49 2026 Received: from mail-ot1-f49.google.com (mail-ot1-f49.google.com [209.85.210.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C485346A11 for ; Fri, 19 Dec 2025 21:33:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180020; cv=none; b=EdkX8GSpmTXAwgS+uizIEQxcUwVjFV5cdHPTFA7Tn/0C922i6hbrzJOflEZLebhL1jRWJxbc+Dnwb8zRMHKoXzhBWoIn8ox8edUX0uFMaMmEvDi1j0z7/Ptmn2z+QyC4tvY1Ue+X8AEiwCdsiesCO4Ja9k9i66zvGyA6TUNAwsQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180020; c=relaxed/simple; bh=dY7cp3RBBiVCkp9Kcc53brAEC9hdPWhw6DTjqjQNuOU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sdCPi1XxbZru3AJLrguvmgLJnS51enM2U5FhA1F8pD2y1nxpsHpaJ/2twTb7FF8yno7SrcAmpzwHffiHJyUSUkX7dqzNjD3zRMk5s0Fd3uso7/IRNyE6Ll11U5h445c45nr+decUwcwGC/qufattenomUY0JjSj8YBu6U4yprkU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=OYBHwfmE; arc=none smtp.client-ip=209.85.210.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="OYBHwfmE" Received: by mail-ot1-f49.google.com with SMTP id 46e09a7af769-7c765f41346so1098155a34.3 for ; Fri, 19 Dec 2025 13:33:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1766180015; x=1766784815; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3Z43oS2Jw0Ev4dfYo22by9u6LAdxn5XavRVOij2D4nc=; b=OYBHwfmEq716OpxS6FqQ3aBY2UuKnc0yNAHfFyN/KxzpndfNIqaTuQH1n3SwY9aWqJ fefzVPchGoywDJZ46oOWLtesBz1ABgSMraRPNC/3nS6DXoOn4swg69p/Y8WmhtTtbVnY LN3WECQOUolYLJaeq3gGTmb+H5Xyoj/5VsvutwHWGH/xG9LaFJjIrmFKzTwoo66hg6by epSNL/j351nTVGNuU5X69eEQ3JIrKVww3hGkBRJIrz5LbenmfO4Y8p867nLfwM7bOwRP ne82WgySl/dPYqsoKk3SLfshQzSSym57jlkyF2/FKtSepjYgSxH6+ItrGjJCTObICVux GMiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766180015; x=1766784815; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=3Z43oS2Jw0Ev4dfYo22by9u6LAdxn5XavRVOij2D4nc=; b=kSt96fU94AwZDeJgL9rWCP72asljJFopPZWbMLZ4yhBFKln9iKuESNWT7Q5Qc+uGt+ b+yrQkTJvh7QTtNZUVOC2OqA1Hm4L74C1Db/GK6OtYewucIVZDi3N6MPQfQ1raTpr1Cz ekq6fMlCm7PypG28lSQhiyYCShsICHXJpxZ5O2pWEvX5EqcaYrvDBrO0reKtUE9WbQJT aPOKjSYcvVfuUVWXfzZxGOk/blJDtSG9DrGd1cBPuU9lE1Xv4BGjg3qc0qV1vfgPJwYm iBa3hGcy4ILiZBYsA5bGJ+AtVoYq20w6URe1PFeG8scXRiRVP/nugu5/qQ4ZfzoVM4DV J7HQ== X-Forwarded-Encrypted: i=1; AJvYcCWEnBvOpxH1K00GBuAQ6uL4Qc9rnKaM3dthC/KIanntXm524iEBZO2K3N+tX/GSfctCAjcSEKHgxtFNl+Q=@vger.kernel.org X-Gm-Message-State: AOJu0YxO1xcweRvDn0k7wFEh+/Uap8pLvHgrGpdZgV/gAS1VWdLogiQu V7o8P6eupHqbyvYiijHjcp1sRp7YOmtZDIcjNWjJ/8L3bJ2PGQhp7E5dmdV5Cq+Sh44= X-Gm-Gg: AY/fxX5B7BV1QwaeEdFhmqFGW/92oh5FqDJPqdhJYLl1UbJiKC/oZzV7zfZQH66pyfZ JmsvxxnkEs5IyG61dI6F6o+f4891O71Gj8a/ODETFmPGsNUoqhq2OM5mkv05iD+1JJG4uOppcYx gQrsil+tl5o6jNEiOTLuKVtvenfmu3R9LYmdlYMe3OGZLSEN8/DCNBzBZOURapcdZQ8M3xfAJuA k+mCjwTzj+Rv+1rK5lS4THqxp5sZk957eJ9E7f3ONHJQhAjs4vreTnzgnu/Yl+4M5VIcudI5LLL DduqJbiOaUhLjhew5JHPc0G5P5fxiYSnItfQvCU85G7r35IIdNvn1gFvU6lRSXTeCTboEBGc36R VPom3X1/xiD0UKX4HhiOo9q53JqV+KUqxIg2OtypXhiIR+9cMA4Eh1g8S0yrrQsnxtnljnGkfIV VsKNMpOUPpl2koLkhwMouc7JvU X-Google-Smtp-Source: AGHT+IEV2Y3TdkUjmquqF6HvA05aKkAArLkAjqKr0vCj0HIE8vG1QcO6ia3T+QJa2w3j6AwwMjeNgw== X-Received: by 2002:a05:6830:3105:b0:7c7:6348:594a with SMTP id 46e09a7af769-7cc668e8135mr2423716a34.7.1766180015061; Fri, 19 Dec 2025 13:33:35 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:9b20:bac4:9680:435]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7cc667563ffsm2485045a34.13.2025.12.19.13.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 13:33:34 -0800 (PST) From: David Lechner Date: Fri, 19 Dec 2025 15:32:15 -0600 Subject: [PATCH v4 7/9] spi: axi-spi-engine: support SPI_MULTI_LANE_MODE_STRIPE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-spi-add-multi-bus-support-v4-7-145dc5204cd8@baylibre.com> References: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> In-Reply-To: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=12068; i=dlechner@baylibre.com; h=from:subject:message-id; bh=dY7cp3RBBiVCkp9Kcc53brAEC9hdPWhw6DTjqjQNuOU=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpRcSRlMrxU20bsdrnwA0lULCe3bQauFngTE13D Cztvrg/HdKJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUXEkQAKCRDCzCAB/wGP wAYwB/9ZG35txJDZP6Mh2qj0HGLp4MngWr27B9x859qchxnuxg4Mdf9PGWo4QB5JyjIXpEWwerT AwEnsUnQVT7LM7du3wlzfxh5EKE5Zyq4kRGp8dKICL3W2u9H1hkgBLGIDaCpGc83QNf3vyi8469 HAPkzivB8SKBp/1hJeYiLx1ZYO+0J3bwbO3cpEVhaf+PHC9iT4tqnepj4FzGFWIoCsxxAbf9VLC OKq/XuQ0xN2dFzjhFxKFF5hnMdXLnpQcGWMf7FPTTkiun8Yad9nFZci3yVc6JJZFXaVN4WG9MAq sRmGuv67klWTxgPuNzeL8Sio0c1fKWuJNBlF6svZLB0FI2xq X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add support for SPI_MULTI_LANE_MODE_STRIPE to the AXI SPI engine driver. The v2.0.0 version of the AXI SPI Engine IP core supports multiple lanes. This can be used with SPI_MULTI_LANE_MODE_STRIPE to support reading from simultaneous sampling ADCs that have a separate SDO line for each analog channel. This allows reading all channels at the same time to increase throughput. Signed-off-by: David Lechner Reviewed-by: Marcelo Schmitt --- v4 changes: * Update for core SPI API changes. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. v2 changes: * Fixed off-by-one in SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO_MASK GENMASK --- drivers/spi/spi-axi-spi-engine.c | 145 +++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 141 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi-eng= ine.c index e06f412190fd..3028e6112909 100644 --- a/drivers/spi/spi-axi-spi-engine.c +++ b/drivers/spi/spi-axi-spi-engine.c @@ -23,6 +23,9 @@ #include #include =20 +#define SPI_ENGINE_REG_DATA_WIDTH 0x0C +#define SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO_MASK GENMASK(23, 16) +#define SPI_ENGINE_REG_DATA_WIDTH_MASK GENMASK(15, 0) #define SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH 0x10 #define SPI_ENGINE_REG_RESET 0x40 =20 @@ -75,6 +78,8 @@ #define SPI_ENGINE_CMD_REG_CLK_DIV 0x0 #define SPI_ENGINE_CMD_REG_CONFIG 0x1 #define SPI_ENGINE_CMD_REG_XFER_BITS 0x2 +#define SPI_ENGINE_CMD_REG_SDI_MASK 0x3 +#define SPI_ENGINE_CMD_REG_SDO_MASK 0x4 =20 #define SPI_ENGINE_MISC_SYNC 0x0 #define SPI_ENGINE_MISC_SLEEP 0x1 @@ -105,6 +110,10 @@ #define SPI_ENGINE_OFFLOAD_CMD_FIFO_SIZE 16 #define SPI_ENGINE_OFFLOAD_SDO_FIFO_SIZE 16 =20 +/* Extending SPI_MULTI_LANE_MODE values for optimizing messages. */ +#define SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN -1 +#define SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING -2 + struct spi_engine_program { unsigned int length; uint16_t instructions[] __counted_by(length); @@ -142,6 +151,11 @@ struct spi_engine_offload { unsigned long flags; unsigned int offload_num; unsigned int spi_mode_config; + unsigned int multi_lane_mode; + u8 rx_primary_lane_mask; + u8 tx_primary_lane_mask; + u8 rx_all_lanes_mask; + u8 tx_all_lanes_mask; u8 bits_per_word; }; =20 @@ -165,6 +179,25 @@ struct spi_engine { bool offload_requires_sync; }; =20 +static void spi_engine_primary_lane_flag(struct spi_device *spi, + u8 *rx_lane_flags, u8 *tx_lane_flags) +{ + *rx_lane_flags =3D BIT(spi->rx_lane_map[0]); + *tx_lane_flags =3D BIT(spi->tx_lane_map[0]); +} + +static void spi_engine_all_lanes_flags(struct spi_device *spi, + u8 *rx_lane_flags, u8 *tx_lane_flags) +{ + int i; + + for (i =3D 0; i < spi->num_rx_lanes; i++) + *rx_lane_flags |=3D BIT(spi->rx_lane_map[i]); + + for (i =3D 0; i < spi->num_tx_lanes; i++) + *tx_lane_flags |=3D BIT(spi->tx_lane_map[i]); +} + static void spi_engine_program_add_cmd(struct spi_engine_program *p, bool dry, uint16_t cmd) { @@ -193,7 +226,7 @@ static unsigned int spi_engine_get_config(struct spi_de= vice *spi) } =20 static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry, - struct spi_transfer *xfer) + struct spi_transfer *xfer, u32 num_lanes) { unsigned int len; =20 @@ -204,6 +237,9 @@ static void spi_engine_gen_xfer(struct spi_engine_progr= am *p, bool dry, else len =3D xfer->len / 4; =20 + if (xfer->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) + len /=3D num_lanes; + while (len) { unsigned int n =3D min(len, 256U); unsigned int flags =3D 0; @@ -269,6 +305,7 @@ static int spi_engine_precompile_message(struct spi_mes= sage *msg) { unsigned int clk_div, max_hz =3D msg->spi->controller->max_speed_hz; struct spi_transfer *xfer; + int multi_lane_mode =3D SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN; u8 min_bits_per_word =3D U8_MAX; u8 max_bits_per_word =3D 0; =20 @@ -284,6 +321,24 @@ static int spi_engine_precompile_message(struct spi_me= ssage *msg) min_bits_per_word =3D min(min_bits_per_word, xfer->bits_per_word); max_bits_per_word =3D max(max_bits_per_word, xfer->bits_per_word); } + + if (xfer->rx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM || + xfer->tx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_TX_STREAM) { + switch (xfer->multi_lane_mode) { + case SPI_MULTI_LANE_MODE_SINGLE: + case SPI_MULTI_LANE_MODE_STRIPE: + break; + default: + /* Other modes, like mirror not supported */ + return -EINVAL; + } + + /* If all xfers have the same multi-lane mode, we can optimize. */ + if (multi_lane_mode =3D=3D SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN) + multi_lane_mode =3D xfer->multi_lane_mode; + else if (multi_lane_mode !=3D xfer->multi_lane_mode) + multi_lane_mode =3D SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING; + } } =20 /* @@ -297,6 +352,14 @@ static int spi_engine_precompile_message(struct spi_me= ssage *msg) priv->bits_per_word =3D min_bits_per_word; else priv->bits_per_word =3D 0; + + priv->multi_lane_mode =3D multi_lane_mode; + spi_engine_primary_lane_flag(msg->spi, + &priv->rx_primary_lane_mask, + &priv->tx_primary_lane_mask); + spi_engine_all_lanes_flags(msg->spi, + &priv->rx_all_lanes_mask, + &priv->tx_all_lanes_mask); } =20 return 0; @@ -310,6 +373,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, struct spi_engine_offload *priv; struct spi_transfer *xfer; int clk_div, new_clk_div, inst_ns; + int prev_multi_lane_mode =3D SPI_MULTI_LANE_MODE_SINGLE; bool keep_cs =3D false; u8 bits_per_word =3D 0; =20 @@ -334,6 +398,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, * in the same way. */ bits_per_word =3D priv->bits_per_word; + prev_multi_lane_mode =3D priv->multi_lane_mode; } else { spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG, @@ -344,6 +409,28 @@ static void spi_engine_compile_message(struct spi_mess= age *msg, bool dry, spi_engine_gen_cs(p, dry, spi, !xfer->cs_off); =20 list_for_each_entry(xfer, &msg->transfers, transfer_list) { + if (xfer->rx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM || + xfer->tx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_TX_STREAM) { + if (xfer->multi_lane_mode !=3D prev_multi_lane_mode) { + u8 tx_lane_flags, rx_lane_flags; + + if (xfer->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) + spi_engine_all_lanes_flags(spi, &rx_lane_flags, + &tx_lane_flags); + else + spi_engine_primary_lane_flag(spi, &rx_lane_flags, + &tx_lane_flags); + + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + rx_lane_flags)); + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + tx_lane_flags)); + } + prev_multi_lane_mode =3D xfer->multi_lane_mode; + } + new_clk_div =3D host->max_speed_hz / xfer->effective_speed_hz; if (new_clk_div !=3D clk_div) { clk_div =3D new_clk_div; @@ -360,7 +447,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, bits_per_word)); } =20 - spi_engine_gen_xfer(p, dry, xfer); + spi_engine_gen_xfer(p, dry, xfer, spi->num_rx_lanes); spi_engine_gen_sleep(p, dry, spi_delay_to_ns(&xfer->delay, xfer), inst_ns, xfer->effective_speed_hz); =20 @@ -394,6 +481,19 @@ static void spi_engine_compile_message(struct spi_mess= age *msg, bool dry, if (clk_div !=3D 1) spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV, 0)); + + /* Restore single lane mode unless offload disable will restore it later.= */ + if (prev_multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE && + (!msg->offload || priv->multi_lane_mode !=3D SPI_MULTI_LANE_MODE_STRI= PE)) { + u8 rx_lane_flags, tx_lane_flags; + + spi_engine_primary_lane_flag(spi, &rx_lane_flags, &tx_lane_flags); + + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, rx_lane_flags)); + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, tx_lane_flags)); + } } =20 static void spi_engine_xfer_next(struct spi_message *msg, @@ -799,6 +899,19 @@ static int spi_engine_setup(struct spi_device *device) writel_relaxed(SPI_ENGINE_CMD_CS_INV(spi_engine->cs_inv), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 + if (host->num_data_lanes > 1) { + u8 rx_lane_flags, tx_lane_flags; + + spi_engine_primary_lane_flag(device, &rx_lane_flags, &tx_lane_flags); + + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + rx_lane_flags), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + tx_lane_flags), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } + /* * In addition to setting the flags, we have to do a CS assert command * to make the new setting actually take effect. @@ -902,6 +1015,15 @@ static int spi_engine_trigger_enable(struct spi_offlo= ad *offload) priv->bits_per_word), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 + if (priv->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) { + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + priv->rx_all_lanes_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + priv->tx_all_lanes_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } + writel_relaxed(SPI_ENGINE_CMD_SYNC(1), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 @@ -929,6 +1051,16 @@ static void spi_engine_trigger_disable(struct spi_off= load *offload) reg &=3D ~SPI_ENGINE_OFFLOAD_CTRL_ENABLE; writel_relaxed(reg, spi_engine->base + SPI_ENGINE_REG_OFFLOAD_CTRL(priv->offload_num)); + + /* Restore single-lane mode. */ + if (priv->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) { + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + priv->rx_primary_lane_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + priv->tx_primary_lane_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } } =20 static struct dma_chan @@ -973,7 +1105,7 @@ static int spi_engine_probe(struct platform_device *pd= ev) { struct spi_engine *spi_engine; struct spi_controller *host; - unsigned int version; + unsigned int version, data_width_reg_val; int irq, ret; =20 irq =3D platform_get_irq(pdev, 0); @@ -1042,7 +1174,7 @@ static int spi_engine_probe(struct platform_device *p= dev) return PTR_ERR(spi_engine->base); =20 version =3D readl(spi_engine->base + ADI_AXI_REG_VERSION); - if (ADI_AXI_PCORE_VER_MAJOR(version) !=3D 1) { + if (ADI_AXI_PCORE_VER_MAJOR(version) > 2) { dev_err(&pdev->dev, "Unsupported peripheral version %u.%u.%u\n", ADI_AXI_PCORE_VER_MAJOR(version), ADI_AXI_PCORE_VER_MINOR(version), @@ -1050,6 +1182,8 @@ static int spi_engine_probe(struct platform_device *p= dev) return -ENODEV; } =20 + data_width_reg_val =3D readl(spi_engine->base + SPI_ENGINE_REG_DATA_WIDTH= ); + if (adi_axi_pcore_ver_gteq(version, 1, 1)) { unsigned int sizes =3D readl(spi_engine->base + SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH); @@ -1097,6 +1231,9 @@ static int spi_engine_probe(struct platform_device *p= dev) } if (adi_axi_pcore_ver_gteq(version, 1, 3)) host->mode_bits |=3D SPI_MOSI_IDLE_LOW | SPI_MOSI_IDLE_HIGH; + if (adi_axi_pcore_ver_gteq(version, 2, 0)) + host->num_data_lanes =3D FIELD_GET(SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO= _MASK, + data_width_reg_val); =20 if (host->max_speed_hz =3D=3D 0) return dev_err_probe(&pdev->dev, -EINVAL, "spi_clk rate is 0"); --=20 2.43.0 From nobody Sun Feb 8 13:27:49 2026 Received: from mail-ot1-f47.google.com (mail-ot1-f47.google.com [209.85.210.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B009A33A03F for ; Fri, 19 Dec 2025 21:33:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180020; cv=none; b=WZEJYcxuSropHuP+UmWCrzoK2vi2r33OMBGXiaa0PkuDEu9koEAr161nboyM5aoUsayI0FUNloEOauG8XK6Ms+qsmdk7o0pmWNLlmLtmiKI0Ak0CK5qCnQtjbH6S/VXVxBR1puBBGjIhSTg1oJPOWh2NGkQ+z5Mlq6lm1ogjG4Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180020; c=relaxed/simple; bh=VQOPaqQmoNwtfxLbCSXG6BhStJUeMtFzJ0prIuJB4JY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ampj0FMGTvOVlf9ycVYU+nXfjgm2nPjxG5XrlCEp8UrFFJ6Zo0gp25MrtYyX/HZzkYwPEW+eFJUCLlgzP8WwiYTv5I3CIKLK3kjmsd+qsqr7dIh3mt/6wXDU6bTCY/3+qJpr0nZs0LdUqsjZv7/C/PhvcoebGNdmg3qh4gZmtyM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=ClUwTzIv; arc=none smtp.client-ip=209.85.210.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="ClUwTzIv" Received: by mail-ot1-f47.google.com with SMTP id 46e09a7af769-7c7613db390so1315777a34.2 for ; Fri, 19 Dec 2025 13:33:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1766180016; x=1766784816; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dQ9bA5wAd5cOLSdkvDwsJ4KZGTUhg22dy+q+3KzYnqw=; b=ClUwTzIv7D5PMbxN5U2hCpoVmQmiheLK+Ejx49ksbUV4lrOdVCjjAKSIT8+IHQyPup DRc/RNMyPy+F7GWPXZp0G27Ln1n8gdnJT2F7mUfmaeUZx7jSG90FIYeyYzGuyptEKiZU xAg3NajpQ1u1NrfvwxoouNCJuxsMyYsn/gCdO20tP5DGSdemiv27clgl6bXv7gPpFbUq qoVPyJunXV88TM6awOyQ5WZUKS22Jt8J3BDVyNcI+gNzR//ihSkHqw76NDWQshYj8HZC xJnee4+DRXmrw93yFkX4VV3+AIxtbLgDZTk/tADKOz3TLOxL2l8lhjcXyqHvjPfeiNwl GPUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766180016; x=1766784816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=dQ9bA5wAd5cOLSdkvDwsJ4KZGTUhg22dy+q+3KzYnqw=; b=kzupeoemiuVHI5j+bVM96sVBiPMKhiEbTsmVbvdAqZjabqjQRz4JxDWR+7sg3hkSuI dODBGIDyUS56jyL9MUToizToPR42VNlDx3ZSOJtCCUHQXwBo7xUfxhJTIf1utsLKXp6G xeUgmoN7TLAxZ/YjhSCqOvKp8gsxdbWnVJh6kB4L+Yiw4TuRhTdLUFNNMJaOf2be1cdm +JSkdsPDbach1jdW7OtT/tG+OOfD0WDapZi9aN3Hx09wmfR3JYCwM1Uv6F0v5BnsvaJj L+66jv7qUj/gK0Tm5Fcrtyw1RuVCJ8o+xsNLqb2SEbta4SrQRvy7+U1v5ZTk6zsE/X73 JZCw== X-Forwarded-Encrypted: i=1; AJvYcCVLePe22dIwnDlLHaMarqwVcYYzcykZmRlF3Jami0kgYVJULeJnE8O1oFvlEwSFWkTHmj2zviwrXkQz34Q=@vger.kernel.org X-Gm-Message-State: AOJu0Yy4whE4mxGYbaowME8zTg28NLDqvPsZXAbjo4zsKqcoogWHYrFD sVadi6bnhUc+HFRbfSumevQpDE1Z/zBs8XEsWVi0PKsMbAZreQxPeWas/a+g/yVAeBo= X-Gm-Gg: AY/fxX6qhWMrZdQrShPVrKL7jpWISy10LspWxZeFxAcSJ2Ez67vJVTnnJlQOtYudP0Y F2px9XI3ewN+Q93EhrZpSjpBRF0nkZHAcEYUasiwS23WFJqaCLXG1jf6jkccQE9y+E5aJ0Q97+R tgrbfRhDck4eLU9g4L1/GeLWUdZNcdh+XJpG9BkGBih/f2EMa1EppNVKmHzDPyBe5Jf2xHZhHst YUtTcuozuSXlCM71kXDle/TO0l3qDd9rXEjiJyrtp1NcBZ5RIhGQNfPVSkO8z7To0NC/jsHkTES mhocA29vPBqg+74ZvXcy6YzLRyJSuqClzZVpZg81Eon7oWwAKN5bXgLOwgQhkOqky3Loqlsm5+R FNF3K1QPGS6IcaZrXKyEKtw+kpvEpdpiQHJEXN8KV+oMKpTkwusEW2hcSas81hN60Xiriw+WbAb tBEZ2V+uYKdHwtew== X-Google-Smtp-Source: AGHT+IHGyipb98La7XJE4vZ3dHFAmyXLQw9XZJ4q2W59l2gO7JhuowVl43/w0hKUEnQvJoe8SceFQQ== X-Received: by 2002:a05:6830:43a4:b0:7c7:6da2:6d67 with SMTP id 46e09a7af769-7cc6689d9a3mr2725997a34.3.1766180016063; Fri, 19 Dec 2025 13:33:36 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:9b20:bac4:9680:435]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7cc667563ffsm2485045a34.13.2025.12.19.13.33.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 13:33:35 -0800 (PST) From: David Lechner Date: Fri, 19 Dec 2025 15:32:16 -0600 Subject: [PATCH v4 8/9] dt-bindings: iio: adc: adi,ad7380: add spi-rx-bus-width property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-spi-add-multi-bus-support-v4-8-145dc5204cd8@baylibre.com> References: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> In-Reply-To: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1994; i=dlechner@baylibre.com; h=from:subject:message-id; bh=VQOPaqQmoNwtfxLbCSXG6BhStJUeMtFzJ0prIuJB4JY=; b=owGbwMvMwMV46IwC43/G/gOMp9WSGDJdj8x4ylQ589TTfacs62zckqz2Ftiw2V77mJYWu/bgq w/+tYsyOhmNWRgYuRhkxRRZ3kjcnJfE13xtzo2MGTCDWJlApjBwcQrARJLt2f8nbY/dJ2r7o6ss aqLRboWsvRb9e99U77iS53ubY6mUBEOPqVcD02a3roS3N24zbC+ujhMqz5Jh/MkjxiJtcfnHlMk zTOdLLM6qrZzkWxf4b/7TiybBBQnTNrrILXS64F8a21++6a3oztkttS/P/PJa9mmt3ZJ7go9YGK QVH94TKUhMU21pEvn486BYRmiamG8kC/MrkZNrG34mu8/cmdIjn9nhFxlsvYL3yaz8pgk1N60zY ybYTUq7ZKXyVyug/ORLXquoxnCWU45HtvyU9NpcrtZutTmYpzHfwDhxwaWc/KrX8828t6Q+6d7x v+xx81Xus4eS252a1PkYrZYU7GRx23vIbk+pn92SNOXlAA== X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add spi-rx-bus-width property to describe how many SDO lines are wired up on the ADC. These chips are simultaneous sampling ADCs and have one SDO line per channel, either 2 or 4 total depending on the part number. Signed-off-by: David Lechner Reviewed-by: Rob Herring (Arm) --- v4 changes: * Change to use spi-rx-bus-width property instead of spi-lanes. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. --- .../devicetree/bindings/iio/adc/adi,ad7380.yaml | 23 ++++++++++++++++++= ++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml index b91bfb16ed6b..396e1a1aa805 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -62,6 +62,11 @@ properties: spi-cpol: true spi-cpha: true =20 + spi-rx-bus-width: + maxItems: 4 + items: + maximum: 1 + vcc-supply: description: A 3V to 3.6V supply that powers the chip. =20 @@ -160,6 +165,23 @@ patternProperties: unevaluatedProperties: false =20 allOf: + # 2-channel chips only have two SDO lines + - if: + properties: + compatible: + enum: + - adi,ad7380 + - adi,ad7381 + - adi,ad7383 + - adi,ad7384 + - adi,ad7386 + - adi,ad7387 + - adi,ad7388 + then: + properties: + spi-rx-bus-width: + maxItems: 2 + # pseudo-differential chips require common mode voltage supplies, # true differential chips don't use them - if: @@ -284,6 +306,7 @@ examples: spi-cpol; spi-cpha; spi-max-frequency =3D <80000000>; + spi-rx-bus-width =3D <1>, <1>, <1>, <1>; =20 interrupts =3D <27 IRQ_TYPE_EDGE_FALLING>; interrupt-parent =3D <&gpio0>; --=20 2.43.0 From nobody Sun Feb 8 13:27:49 2026 Received: from mail-ot1-f50.google.com (mail-ot1-f50.google.com [209.85.210.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D03D0342C9E for ; Fri, 19 Dec 2025 21:33:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180022; cv=none; b=Zb/pBadN0dFJx4m7I51doA/3Vyd3FudugsXDj3EiTuBDJGpb15bvewgw69duxZsZpY5imacCoC75qvCdYY5tt9Kg6hB3klQmRCXEcVq862kW/gA4MDGC6/dHn130Ahd+7TOLGmJuewMSgDDdFy6sTaUhVaGUn1vsMP1WW0kt+xI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180022; c=relaxed/simple; bh=LH6Vyxalmz1bUck/pw36flu8Rm/aY8DBxOEtRceLBNY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TTkh3MW8yKb03V0DiTkfVh8412WRfJDnPHuvDF8J0tKuTGN9ITNbDz4UDqzRk15nvqhJLrVZifISdy6YqaW4QV+qVLfRTRP5xjuIQynf1u+JgRaj0KOlCAzaE6MBmsbnmgRNqFHXdffLCUEMxDol+zeaLCtn8jQFJ7QxXfz8AiY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=kJSpsl9u; arc=none smtp.client-ip=209.85.210.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="kJSpsl9u" Received: by mail-ot1-f50.google.com with SMTP id 46e09a7af769-7c6ce4f65f7so1854777a34.0 for ; Fri, 19 Dec 2025 13:33:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1766180017; x=1766784817; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=52JuNH3Z2gevqmnqd29jbAXefa/G2nNvDA29ajR6gPU=; b=kJSpsl9usa+RjG8Ev/lR5x2VG/TtK+U3Rr1aiCfE28QMpla1oGn8JG5aVVND5OAwYH IKmLnr7hdebCupBNBOJGeQ8LTvAqdgFazUq0TdUd4t0xSZey95wWoSXekFkUZ7NeaRi2 s4pjAMBfb4xYVx7k5GnJrr57GDh02v0jyBXQ7y5wQYzvGzFzvKUJGJDK0iAMKApnWu12 wLEhogoUu2kglIXck9h+Ve2k79Lrkv8mpI4w2kUWg4Gaxpd0zAcJ3Z4SDpb/pppdr/kd y+zg9cyseW4Jdx+L6ngV7zGv+q0xa/J29g0fRdvdFV2kUy3ev7sgOcsuNIcOLv5HOB34 X8Gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766180017; x=1766784817; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=52JuNH3Z2gevqmnqd29jbAXefa/G2nNvDA29ajR6gPU=; b=JKf7fyBOZ8rOmYuPccbh5hxyQXsVSg/7l1yMFJrtcY7irytRgCl4Df/BFo96rn0Ean 4EDJUIG0YAwmewiw/4Z0WvEqxx0PuS5kNiy1Fb1k0Aj6Ap1zP2ai0q6dYfEPxgMPCW5S VgQamNWhfO2oEGuDUDwCtvy/CHWd1mGNSLxkPIQsJlw2xUogmuE0a9Kkb8bEkaknltxT EYaPeRqK+IPHlYA+AY9YmjwI70uiK9sJhSGaXuw35lYxc19ADcItZhrQyUelZchX1N36 FkKo96gnEtarUGOI3l4vOPver/CkGvrBJHZUbG/m5sGPMrVLZla+1ObqkwswMzjzlE0B I7lg== X-Forwarded-Encrypted: i=1; AJvYcCVVKuSBedeAafuKBc6MbDeMU2FGFhDp+yns9Qy/7BnXt2CExa0xRSI7FJdwEOHshWsodyYWTniXWsRAkuw=@vger.kernel.org X-Gm-Message-State: AOJu0YxyPkMEB7zH8+km8m5ztau0yp7EWwYi2M+pOqMykeLVboW9Uuqq M501qVJYyLlWJDmgVGAyOybff03RWM03CWCKYuJ/MyOB26ppRdFFgKfihZ0aylFOnrQ= X-Gm-Gg: AY/fxX5PpxYiYGxDtkP3F1k9uJz4S2mIQFjWmjFGjzEJA3q4oiZb9MH8HClwdJlYIZA 0II6kqyqupVCkYcGVR7O1PIRFkqSOjPkDWuPnqhD6/IKigGp6o/mLoW4cZRlAKzbmRavtwPhLbb WqAzl6p8jA3JiyJ2jqIyl4azNEoCrFcogUbPjWRw3Gci9V9HnPB4ZZNO7q2NTT2x0vrJ5Nk51on TMMZGu8OkJCu4dIoHHKmgtmWo8weeAPiEn7zeagxKIy3T71pOBJN04jCPOmHkD64gvaGiPiBW2E 4qJug3Ja+1eRIcgqYdo+Jrhy9p7uz+UZdSnVq4J8U17OhxFr/8SVC+FMOygvUef7u6Rsu+6m2br X8eK7gYzElkHG87aPk9Qoo1h2Z01Nk+ydpC+riuixSN/PqUfOXrk8jw3pqmYSUxTYjUJxlCKc2s TZTJ/xmVp7VzvNFg== X-Google-Smtp-Source: AGHT+IHmMw3pWZZJVDqUr745Dbk0HYxeUkbZl92MLOTQ4m+qaXZzYjtt4smJbqsMgIkjg0Pk0sdgvA== X-Received: by 2002:a05:6830:448b:b0:7c7:4bb:dc06 with SMTP id 46e09a7af769-7cc6681931emr2154994a34.0.1766180016976; Fri, 19 Dec 2025 13:33:36 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:9b20:bac4:9680:435]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7cc667563ffsm2485045a34.13.2025.12.19.13.33.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 13:33:36 -0800 (PST) From: David Lechner Date: Fri, 19 Dec 2025 15:32:17 -0600 Subject: [PATCH v4 9/9] iio: adc: ad7380: add support for multiple SPI lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-spi-add-multi-bus-support-v4-9-145dc5204cd8@baylibre.com> References: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> In-Reply-To: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6063; i=dlechner@baylibre.com; h=from:subject:message-id; bh=LH6Vyxalmz1bUck/pw36flu8Rm/aY8DBxOEtRceLBNY=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpRcSfLJx0CYwXi+3uIOIko0pPqOOcsOg6PiCxZ 0u08pcxhUWJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUXEnwAKCRDCzCAB/wGP wNA6B/0VO4IDqFUdeHvEoKkOAZ/oM///2K1qeYPoAIWcCcr0cMVnOYjphT8TQK6cOWMmFNCGv4p pu+LrQaelIjhREHhgQRe6PMkXc88qb2/ucOO0+A0xk4j4wyfG8Ow3nLYXPiRN3GcWRQip9y3/Kc qvXTrsoh+jtmpxwMJqOrnBv0/72H50Uwpp7TX5mwuBoUSaMC4iCIBInxP2+39Ne/uqccqVEAzEF /ZU7FOOOBmPHDjkdZqtfSUgDCxtAniQjg9xDyOShilCZgKso7vj4SX5Kg4BMeb9QJMKV/AZFdgC w/szwCWzrS5JE7cIMxKZXOJ5aUu3kvhhtSuNuLkWwIL81taP X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add support for multiple SPI lanes to increase throughput. The AD7380 family of ADCs have multiple SDO lines on the chip that can be used to read each channel on a separate SPI lane. If wired up to a SPI controller that supports it, the driver will now take advantage of this feature. This allows reaching the maximum sample rate advertised in the datasheet when combined with SPI offloading. Reviewed-by: Nuno S=C3=A1 Signed-off-by: David Lechner Reviewed-by: Marcelo Schmitt --- v4 changes: * Update for core SPI API changes. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. v2 changes: * Move st->seq_xfer[3].multi_lane_mode =3D SPI_MULTI_BUS_MODE_STRIPE; to probe(). --- drivers/iio/adc/ad7380.c | 49 +++++++++++++++++++++++++++++++++++---------= ---- 1 file changed, 36 insertions(+), 13 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index bfd908deefc0..00982b70b316 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -77,8 +77,7 @@ #define AD7380_CONFIG1_REFSEL BIT(1) #define AD7380_CONFIG1_PMODE BIT(0) =20 -#define AD7380_CONFIG2_SDO2 GENMASK(9, 8) -#define AD7380_CONFIG2_SDO BIT(8) +#define AD7380_CONFIG2_SDO GENMASK(9, 8) #define AD7380_CONFIG2_RESET GENMASK(7, 0) =20 #define AD7380_CONFIG2_RESET_SOFT 0x3C @@ -92,11 +91,6 @@ #define T_CONVERT_X_NS 500 /* xth conversion start time (oversampling) */ #define T_POWERUP_US 5000 /* Power up */ =20 -/* - * AD738x support several SDO lines to increase throughput, but driver cur= rently - * supports only 1 SDO line (standard SPI transaction) - */ -#define AD7380_NUM_SDO_LINES 1 #define AD7380_DEFAULT_GAIN_MILLI 1000 =20 /* @@ -888,6 +882,8 @@ struct ad7380_state { bool resolution_boost_enabled; unsigned int ch; bool seq; + /* How many SDO lines are wired up. */ + u8 num_sdo_lines; unsigned int vref_mv; unsigned int vcm_mv[MAX_NUM_CHANNELS]; unsigned int gain_milli[MAX_NUM_CHANNELS]; @@ -1084,7 +1080,7 @@ static int ad7380_set_ch(struct ad7380_state *st, uns= igned int ch) if (oversampling_ratio > 1) xfer.delay.value =3D T_CONVERT_0_NS + T_CONVERT_X_NS * (oversampling_ratio - 1) * - st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; + st->chip_info->num_simult_channels / st->num_sdo_lines; =20 return spi_sync_transfer(st->spi, &xfer, 1); } @@ -1113,7 +1109,7 @@ static int ad7380_update_xfers(struct ad7380_state *s= t, if (oversampling_ratio > 1) t_convert =3D T_CONVERT_0_NS + T_CONVERT_X_NS * (oversampling_ratio - 1) * - st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; + st->chip_info->num_simult_channels / st->num_sdo_lines; =20 if (st->seq) { xfer[0].delay.value =3D xfer[1].delay.value =3D t_convert; @@ -1198,6 +1194,8 @@ static int ad7380_init_offload_msg(struct ad7380_stat= e *st, xfer->bits_per_word =3D scan_type->realbits; xfer->offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; xfer->len =3D AD7380_SPI_BYTES(scan_type) * st->chip_info->num_simult_cha= nnels; + if (st->num_sdo_lines > 1) + xfer->multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; =20 spi_message_init_with_transfers(&st->offload_msg, xfer, 1); st->offload_msg.offload =3D st->offload; @@ -1793,6 +1791,7 @@ static const struct iio_info ad7380_info =3D { =20 static int ad7380_init(struct ad7380_state *st, bool external_ref_en) { + u32 sdo; int ret; =20 /* perform hard reset */ @@ -1815,11 +1814,24 @@ static int ad7380_init(struct ad7380_state *st, boo= l external_ref_en) st->ch =3D 0; st->seq =3D false; =20 - /* SPI 1-wire mode */ + /* SDO field has an irregular mapping. */ + switch (st->num_sdo_lines) { + case 1: + sdo =3D 1; + break; + case 2: + sdo =3D 0; + break; + case 4: + sdo =3D 2; + break; + default: + return -EINVAL; + } + return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, AD7380_CONFIG2_SDO, - FIELD_PREP(AD7380_CONFIG2_SDO, - AD7380_NUM_SDO_LINES)); + FIELD_PREP(AD7380_CONFIG2_SDO, sdo)); } =20 static int ad7380_probe_spi_offload(struct iio_dev *indio_dev, @@ -1842,7 +1854,7 @@ static int ad7380_probe_spi_offload(struct iio_dev *i= ndio_dev, "failed to get offload trigger\n"); =20 sample_rate =3D st->chip_info->max_conversion_rate_hz * - AD7380_NUM_SDO_LINES / st->chip_info->num_simult_channels; + st->num_sdo_lines / st->chip_info->num_simult_channels; =20 st->sample_freq_range[0] =3D 1; /* min */ st->sample_freq_range[1] =3D 1; /* step */ @@ -1887,6 +1899,11 @@ static int ad7380_probe(struct spi_device *spi) if (!st->chip_info) return dev_err_probe(dev, -EINVAL, "missing match data\n"); =20 + st->num_sdo_lines =3D spi->num_rx_lanes; + + if (st->num_sdo_lines < 1 || st->num_sdo_lines > st->chip_info->num_simul= t_channels) + return dev_err_probe(dev, -EINVAL, "invalid number of SDO lines\n"); + ret =3D devm_regulator_bulk_get_enable(dev, st->chip_info->num_supplies, st->chip_info->supplies); =20 @@ -2010,6 +2027,8 @@ static int ad7380_probe(struct spi_device *spi) st->normal_xfer[0].cs_change_delay.value =3D st->chip_info->timing_specs-= >t_csh_ns; st->normal_xfer[0].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; st->normal_xfer[1].rx_buf =3D st->scan_data; + if (st->num_sdo_lines > 1) + st->normal_xfer[1].multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; =20 spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer, ARRAY_SIZE(st->normal_xfer)); @@ -2031,6 +2050,10 @@ static int ad7380_probe(struct spi_device *spi) st->seq_xfer[2].cs_change =3D 1; st->seq_xfer[2].cs_change_delay.value =3D st->chip_info->timing_specs->t_= csh_ns; st->seq_xfer[2].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + if (st->num_sdo_lines > 1) { + st->seq_xfer[2].multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; + st->seq_xfer[3].multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; + } =20 spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer, ARRAY_SIZE(st->seq_xfer)); --=20 2.43.0