From nobody Mon Feb 9 17:01:38 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 847C833C52A; Fri, 19 Dec 2025 19:23:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172192; cv=none; b=IWKCTaxTftClcJviGjEjlr47e955iDE4mkmXoHJ9FRc92hdIBrWBlGwSD3dEcHoLxFZJZFhEmu2bAi69XHZuGPiE8x56a58pZfc/1TVCFuUaHl/ZEGMv7exkPh2Z0Ewm/cfT42Q4HMuNPF5MRX3balH7pD8I5ApfG7JQ8Y/TIRU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172192; c=relaxed/simple; bh=sa2UnVgEnCd23b6EOC6Iyc0yYfI+fy2H5jtMEwZxIQg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZrnK5RmULugmiGa3GqTB0z5MwJezOKKbT6IVs3Jh1+iAhnT+8GZhT4rGO6J0mVfzwjZD4vjTwS7e+4dcVRicng2s3xNaPzCvluq+iA0ONvl5AaPLelDV63IdFTICnqXOlgSFSSAq8mjGC9bNG7yVix0M0QN16UAPc9IKb3Ys0/U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ckiBMi+5; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ckiBMi+5" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 1FFB71A22FB; Fri, 19 Dec 2025 19:23:06 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id E8A066071D; Fri, 19 Dec 2025 19:23:05 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7146C102F0BC0; Fri, 19 Dec 2025 20:22:59 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1766172181; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=6UUmCV1uKTvyWoCEI0vuqFzr0aPmGzmvG/9l0oPKd8s=; b=ckiBMi+5pnR/+mSnWvDDxB1HFEv2eZw1GJfIfrTzsVZcogi4yn8Fm6gINbD+DGMH8g/y8I dfefjbEtO2kp40lmCFQ0eNgDxnyLUXZEK4ZvJPgsqMIoFQHl9pTm+gQ7MH1V2LN+2LebUQ qN4IrHFhA4q2paXOlQTc8w72sHZuPTZH0SH+9jJGLBfG6EzxVdEvHnSs4sP8ecU9bxyGHp adYaBTPjULyoJ7P2Y8x1p71GPuILNybmiT4tSnstOB1Fpu7UVUHw7CZfWmqD4nHBKZCgrW 6FuloiGpxWCQV69qYzEOg/LGJGwtBGYm5yIz2+pnnnN4HMIjyWVcNDeN4lEAWw== From: "Miquel Raynal (Schneider Electric)" Date: Fri, 19 Dec 2025 20:22:03 +0100 Subject: [PATCH 01/13] spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-schneider-6-19-rc1-qspi-v1-1-8ad505173e44@bootlin.com> References: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> In-Reply-To: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add support for the Renesas RZ/N1D400 QSPI controller. This SoC is identified in the bindings with its other name: r9a06g032. It is part of the RZ/N1 family, which contains a "D" and a "S" variant. Align the compatibles used with all other IPs from the same SoC, which requires providing 3 compatibles (the SoC specific compatible, the family compatible, and the original Cadence IP). Signed-off-by: Miquel Raynal (Schneider Electric) --- Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Doc= umentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 53a52fb8b819..62948990defb 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -80,6 +80,10 @@ properties: # controllers are meant to be used with flashes of all kinds, # ie. also NAND flashes, not only NOR flashes. - const: cdns,qspi-nor + - items: + - const: renesas,r9a06g032-qspi + - const: renesas,rzn1-qspi + - const: cdns,qspi-nor - const: cdns,qspi-nor deprecated: true =20 --=20 2.51.1 From nobody Mon Feb 9 17:01:38 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6030C33CEA5 for ; Fri, 19 Dec 2025 19:23:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172195; cv=none; b=K1KGZwfKtyfpJ3eXOXMbLTdvQQPXguIRFqE0ygnxrJdTgUjUDf+R0k5db7HIejSiKozkNyYT9o5qL6MIicEZySklFvsCc7G1csUh8nxgFJpzhnKEdN4acVymsIqlf6CaEJmoZDMyFmI/doLXz+BfeCzH5oQoI9+sciRjP8KP9eY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172195; c=relaxed/simple; bh=6bV1SMUpcFVhm9YkKUunGGcPXiGGY1da3bBRqEHtNNE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=irxVZRzU931JlaXfiYT+h/DVoxU020GAvXuEzFyMFAjy8Dw8bwU9+YMyrii0mRNu3aMEv87k/yxa2tP5nV8Z+fK7ky07p63pBoWIO1Y3SuOmFHppOnjR6/P4XvlsTXDRHzp9oQRDoCn51qcuJyQz9S9VjKMW2Ancrv4U9IMryUI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=FuvItLoz; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="FuvItLoz" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id C58F21A22FA; Fri, 19 Dec 2025 19:23:11 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 9A70D6071D; Fri, 19 Dec 2025 19:23:11 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4AD70102F0CDA; Fri, 19 Dec 2025 20:23:05 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1766172186; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=a7Z+ejC9K/VTb5U+uLkvXhxiuwGhNojSrxEzFC2ijaE=; b=FuvItLozz6Y+blMkmAZCpsCrE4CihpKeHX1fn8T8JJlUGzX9/PMswdwqebHlXR3xmJEovf MecqV4BJ7MdU4ZKmecYrMTDY7mol7bWBKcEHQkJ89W0sAiTm/PvBSU3vK//wWezdfl5HAZ TuUoOvvwU++OAgq5m8RH/1vfI+x0ZXLgKV6x3/6KIljmva6tlPXGl0o1ZgyAWFKeiNl3GR Rnm2fB3CbUbGbNBD3c3VzDVrrqCvA9+gP0f63jKGPMBIthJjS7o45G6M8IBd2pO1qJ7AgK XFxlCDSaf7NDE4yFq+xFJfJtDFSSJP4ogGPl1G1O1dtFJbcOmU3ET84BCUWEog== From: "Miquel Raynal (Schneider Electric)" Date: Fri, 19 Dec 2025 20:22:04 +0100 Subject: [PATCH 02/13] spi: cadence-qspi: Align definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-schneider-6-19-rc1-qspi-v1-2-8ad505173e44@bootlin.com> References: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> In-Reply-To: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Fix alignment on the #defines. Signed-off-by: Miquel Raynal (Schneider Electric) Reviewed-by: Pratyush Yadav --- drivers/spi/spi-cadence-quadspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index af6d050da1c8..e16a591e1f20 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,7 +40,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT= _MAX); #define CQSPI_DISABLE_DAC_MODE BIT(1) #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) -#define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_SLOW_SRAM BIT(4) #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) #define CQSPI_RD_NO_IRQ BIT(6) #define CQSPI_DMA_SET_MASK BIT(7) --=20 2.51.1 From nobody Mon Feb 9 17:01:38 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A56E833F8B4; Fri, 19 Dec 2025 19:23:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172197; cv=none; b=lpnAMWKGW5YZBCioLER2bgAj2rZ8iq+GypWqfMiCQ4ZdCW6HniL0Oe39WINPt2oDaTodng+LCRk3QFZng9SqpWMbzHpXnx3tGIkVt3ivPIqfDEvOoh3DBo/XHxTWO98QnhsymOSNtOVo4XGrpM10fhlyPUhGeDZOXCo6gHF1vVE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172197; c=relaxed/simple; bh=H2+vHq5CFjw1AO60vwoHNGa/FCI4RhTLLNSX0NwP8mw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GX1OOwfM54nN9gyXCUNoklubZGTrWvEfLmaIRrHB75iRoMLmFjNYmbWbEJuGQhjfqhZWStZkuw8q27C/WTGJAcx+USkwg9lSrXheNKUYaFcOqcVr8q6exJ8YiVe/P/wiWvFaooZQ/lvHtPjRYJuDQRtnFlBNb+zBevnpfxrBS4s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=q5KNhQSj; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="q5KNhQSj" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 44EF54E40B7D; Fri, 19 Dec 2025 19:23:14 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 1A8AA6071D; Fri, 19 Dec 2025 19:23:14 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E4F0A10AA981B; Fri, 19 Dec 2025 20:23:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1766172193; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=UeFyK3BHE5JEVZOBeBvHsYEaMdmJRiZh9bgX0hDLsvs=; b=q5KNhQSjcVugqUnwvomnLETI4nNZMM8GexS35/dG+oOuoyA5DAXdBBrYLhulrPcNZN9AYx fNm+rfjQKmVHvYHnlESa5n/ZNI2NsyQOIoWetdOWj/THqn+v55S5GRgv6826lMT3fwa8rW KJZKc+omVeAOToV+6PLzT7FyztozmDT6w5m+iUg1nygzBEa0136K7Cf5M493AmLC0OM+GX 0/W61k2wn06LMC6MrusodsqGYTGKo7vhNL+oqvKPrbToDYKErPr14o4unecgtjCyDTfedx IbiJn8yNRI+pNDnhcvuIsZpt95MciDwQ7GVAK7ZfAUD3+mjmVIEZJjSvtIQOrg== From: "Miquel Raynal (Schneider Electric)" Date: Fri, 19 Dec 2025 20:22:05 +0100 Subject: [PATCH 03/13] spi: cadence-qspi: Fix style and improve readability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-schneider-6-19-rc1-qspi-v1-3-8ad505173e44@bootlin.com> References: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> In-Reply-To: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 It took me several seconds to correctly understand this block. I understand the goal: showing that we are in the if, or in one of the two other cases. Improve the organization of the code to both improve readability and fix the style. Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index e16a591e1f20..90387757fb6b 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -376,13 +376,13 @@ static irqreturn_t cqspi_irq_handler(int this_irq, vo= id *dev) complete(&cqspi->transfer_complete); return IRQ_HANDLED; } + } else { + if (!cqspi->slow_sram) + irq_status &=3D CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; + else + irq_status &=3D CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR; } =20 - else if (!cqspi->slow_sram) - irq_status &=3D CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; - else - irq_status &=3D CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR; - if (irq_status) complete(&cqspi->transfer_complete); =20 --=20 2.51.1 From nobody Mon Feb 9 17:01:38 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3690A33F8AA; Fri, 19 Dec 2025 19:23:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172200; cv=none; b=aONFipsTiA8xMts9snjDBNcKkN5W69IiRq+xXK2d/SgxzoJnp95mh26fN0lnIsD0zBt/eD8CBEOAtm2VARyfQDjPHSjzV4w1q63vwdtFwJYtBTeIob9uINNlnX4vf+J8hSSBaxKUU2fkLpZUuinjOkpkn8GzgO1s3bboFaDMX6U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172200; c=relaxed/simple; bh=AMJ2DGj8AFafe0OktmuvJSX724ZJU8PVhDK8lMGtHfw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZBFaCL8ft+8vVnTWL/UfFFQjBNiMLWyPi38eNpLo5RkcwkclrWYdmBJ35sycWvfLAbLM4dFKssELTHftQX/FCxhc4jZHWTc0pMARCWL90QfnNHQfrVXf7nhiegibu16xPi3QqYtTAd1jGttBeNIQmMtu2f2R2fVLILPlkKS59Yo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=YMGC1ruJ; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="YMGC1ruJ" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id DAA961A22FC; Fri, 19 Dec 2025 19:23:15 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id B0F436071D; Fri, 19 Dec 2025 19:23:15 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 503EB10AA9820; Fri, 19 Dec 2025 20:23:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1766172194; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=6wPdvixvmMf2wMfqEuafLPsvUy/hsce/40XpaNYa+yw=; b=YMGC1ruJXSXW5aNMHL9hjnLUnVFq9xpqUVtGFGB9NDQ6ePJaZPCMVBL6Qwgx1ITvt+UPwg NVybz4IDboerJ3yZYt6wQIEeeeqR+eV4Uw5ugcDSJGBi3K574JGuvAM1UZbWJcaLRWbAqQ VYo5BMPrFVayUTJB/a+Zhac1cgOiV7OQDUdSfG28M/oVgRlD+ESJ93np74lbo3FLiPpB7C scz6XnGMebys+nJkoTgvDpXLcPSkxEhBlVbrPeppDr21RWNIB40Z1n5xlEF7KTwrUStr/d Edtj7SS954mc35PSbupxEExcWWqMKmn510S4upn+OAZ96Ha2KfLHlUUIYkmVVA== From: "Miquel Raynal (Schneider Electric)" Date: Fri, 19 Dec 2025 20:22:06 +0100 Subject: [PATCH 04/13] spi: cadence-qspi: Fix ORing style and alignments Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-schneider-6-19-rc1-qspi-v1-4-8ad505173e44@bootlin.com> References: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> In-Reply-To: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 These definitions do not follow the standard patterns. Alignments are incoherent and the logical OR symbols '|' are misplaced. Reorganize these definitions. There is no functional change. Signed-off-by: Miquel Raynal (Schneider Electric) Acked-by: Pratyush Yadav --- drivers/spi/spi-cadence-quadspi.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 90387757fb6b..143904514736 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -2134,26 +2134,23 @@ static const struct cqspi_driver_platdata intel_lgm= _qspi =3D { }; =20 static const struct cqspi_driver_platdata socfpga_qspi =3D { - .quirks =3D CQSPI_DISABLE_DAC_MODE - | CQSPI_NO_SUPPORT_WR_COMPLETION - | CQSPI_SLOW_SRAM - | CQSPI_DISABLE_STIG_MODE - | CQSPI_DISABLE_RUNTIME_PM, + .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION | + CQSPI_SLOW_SRAM | CQSPI_DISABLE_STIG_MODE | + CQSPI_DISABLE_RUNTIME_PM, }; =20 static const struct cqspi_driver_platdata versal_ospi =3D { .hwcaps_mask =3D CQSPI_SUPPORTS_OCTAL, - .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA - | CQSPI_DMA_SET_MASK, + .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA | + CQSPI_DMA_SET_MASK, .indirect_read_dma =3D cqspi_versal_indirect_read_dma, .get_dma_status =3D cqspi_get_versal_dma_status, }; =20 static const struct cqspi_driver_platdata versal2_ospi =3D { .hwcaps_mask =3D CQSPI_SUPPORTS_OCTAL, - .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA - | CQSPI_DMA_SET_MASK - | CQSPI_SUPPORT_DEVICE_RESET, + .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA | + CQSPI_DMA_SET_MASK | CQSPI_SUPPORT_DEVICE_RESET, .indirect_read_dma =3D cqspi_versal_indirect_read_dma, .get_dma_status =3D cqspi_get_versal_dma_status, }; @@ -2170,7 +2167,7 @@ static const struct cqspi_driver_platdata pensando_cd= ns_qspi =3D { static const struct cqspi_driver_platdata mobileye_eyeq5_ospi =3D { .hwcaps_mask =3D CQSPI_SUPPORTS_OCTAL, .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION | - CQSPI_RD_NO_IRQ, + CQSPI_RD_NO_IRQ, }; =20 static const struct of_device_id cqspi_dt_ids[] =3D { --=20 2.51.1 From nobody Mon Feb 9 17:01:38 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDDB4340A5D; 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arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="L/1VT6n4" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 91FC84E40B7D; Fri, 19 Dec 2025 19:23:17 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 68A5B6071D; Fri, 19 Dec 2025 19:23:17 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 0FF8A10AA981C; Fri, 19 Dec 2025 20:23:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1766172196; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=CINICTjpmxNi5NbYaOjyMfdiaKWMma9y0DPGZD4hR9A=; b=L/1VT6n4bmShB8kV0io8lc51CHXpHRWMsZwujb70YcBEeJtzSivVHLza9r39/qBEaQyIF5 aLl3eyppmHunH0F7pUE4VMCgErdNKUjufyVijEy0WdC0WCYBjFdEWPj1qTjACu42Sqzaqu LKqxAcNmSiBj0EikaUKwbX6BF0eaYLXYxKnaPxQvW9s1CGUwwzm69KPXKbcOHvo6d96RCP alECkgQTmZmJINI2wRywnWsrVcfOl7WGkWezMOU2eqdO3Lgyaz/32sQDkm0sJqt1sITA7N vvVot3DDj+eXmQFI+OaM/1JHOfP21nco9CySqjlx8vjftW9KFuwzqWOMivU7Hw== From: "Miquel Raynal (Schneider Electric)" Date: Fri, 19 Dec 2025 20:22:07 +0100 Subject: [PATCH 05/13] spi: cadence-qspi: Remove an useless operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-schneider-6-19-rc1-qspi-v1-5-8ad505173e44@bootlin.com> References: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> In-Reply-To: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Right above writing the register value back based on 'div' value, there is the following check: if (div > CQSPI_REG_CONFIG_BAUD_MASK) div =3D CQSPI_REG_CONFIG_BAUD_MASK; which means div does not need to be AND'ed against the bitfield mask. Remove this redundant operation. Signed-off-by: Miquel Raynal (Schneider Electric) Reviewed-by: Pratyush Yadav --- drivers/spi/spi-cadence-quadspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 143904514736..8f78d1c44663 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1264,7 +1264,7 @@ static void cqspi_config_baudrate_div(struct cqspi_st= *cqspi) =20 reg =3D readl(reg_base + CQSPI_REG_CONFIG); reg &=3D ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); - reg |=3D (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; + reg |=3D div << CQSPI_REG_CONFIG_BAUD_LSB; writel(reg, reg_base + CQSPI_REG_CONFIG); } =20 --=20 2.51.1 From nobody Mon Feb 9 17:01:38 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A233341046; Fri, 19 Dec 2025 19:23:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172202; cv=none; b=hjSU4ZAIy3VgxsemvVmzt530KrHgOkDo4FJBkuYK9Jpfjr7r+h7NBvvic/rQ+5nOf+d2gyTF7MY9lW9jGseDLkNOzKRguI7v3PhLY7wjxvwbEzDDLNm6ofN9KeEj0zJIBKpidkVkXNpcLLyy76EfPGwbdaEq9F3cgVZZ8nmpkAk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172202; c=relaxed/simple; bh=MdZ3d8nEN8aYHL4QEwKmkoUUdnztQwqgvokaNOhd5UY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=poZOKrl3HAzit0wwaoGOW75XCUyLmPUUuMyYJAlOxhw0X4GCnLkBbcc9A2NNF/jfg6tCtg0mQcya6+I1ZpF6gZBBhul8qXeoUUk/0nfX+36it2yVasrM5hGxLS3yu8/A6BXC+mUn77xDVlmj2QOigLWXDiCinuLQd4cdxD8AJU8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=caKo3UjO; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="caKo3UjO" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 5E4D8C1B210; Fri, 19 Dec 2025 19:22:54 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 207516071D; Fri, 19 Dec 2025 19:23:19 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CBC1910AA95EC; Fri, 19 Dec 2025 20:23:16 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1766172198; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Kwu3Bk7SfRQkZlA6MLoy4o6YT2zdfxSbLAm4sFOyrsQ=; b=caKo3UjOGaLXrv/ZFGhXdhDMlR7OAlBQNL/zBitE/z7xQtjCTDWQmgehg2uxgZXRMquWzJ mts4WivPqM/KRgWPZ36DIwI7GrVo4FVEYZjiHSJYFEjFlWZ9egCpjDghBWP3kC3UnwzffV 8LdL9a71h//Bz2Lsd3iKRy81YEndsImflrHq6GLGeJuMjmgbLtJ7xmp182wVbEgMgsItbL R5Qz5UYeeFljs43am/WQ2cQ6XBeacLHlirKWHNfZGb0fPT/QtBotIq4gM8F6Zv87WYuMp5 8q6VFcBjkfHaVr/KXjJJGsotaY3MZve4HRoLztjH/+9l8GHUNdtyAZm6KuEuIg== From: Miquel Raynal Date: Fri, 19 Dec 2025 20:22:08 +0100 Subject: [PATCH 06/13] spi: cadence-qspi: Make sure we filter out unsupported ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-schneider-6-19-rc1-qspi-v1-6-8ad505173e44@bootlin.com> References: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> In-Reply-To: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The Cadence driver does not support anything else than repeating the command opcode twice while in octal DTR mode. Make this clear by checking for this in the ->supports_op() hook. Signed-off-by: Miquel Raynal Reviewed-by: Pratyush Yadav --- drivers/spi/spi-cadence-quadspi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 8f78d1c44663..f59f3a8dccf5 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1537,6 +1537,10 @@ static bool cqspi_supports_mem_op(struct spi_mem *me= m, return false; if (op->data.nbytes && op->data.buswidth !=3D 8) return false; + + /* A single opcode is supported, it will be repeated */ + if ((op->cmd.opcode >> 8) !=3D (op->cmd.opcode & 0xFF)) + return false; } else if (!all_false) { /* Mixed DTR modes are not supported. */ return false; --=20 2.51.1 From nobody Mon Feb 9 17:01:38 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5832030C610; Fri, 19 Dec 2025 19:23:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172204; cv=none; b=Qu7eXZ7c4Ak+QENoxHEjmlAdFygKHjWZCuw0/QS27LRrkPBlkxkP+xizNI0yHjabIGsEVWO9pSeXOScTmkTwaVKYGTTyNz/ZAPAE5mikXv9zth/TzjjZw9GRSCLngmAUV+t46pFlq+RIfuEJblI1G8hTu579AgCqmyg2cITuDDU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172204; c=relaxed/simple; bh=V1d7lGjeLKI9sMwgaextJPK1cYCiLcN3Ja+3a2Mk6p4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uqpELLO4votZecpTv29saowwYttJ0jARZRYRnm9msgu0uEGch+dk9vxJpqFBWfOqle/andvl+T+o93X0QgeU7jTsEzM1iB/KNT8uQqCAWFnrDVLvLpWEqpNQCleSRs+8+Q7nRGB29PZGC6UdoqS3NbeaoxWk7tbFqhrbWAgRLP4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=sw8oG0a0; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="sw8oG0a0" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 21C3EC1B20F; Fri, 19 Dec 2025 19:22:56 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id D6E4C6071D; Fri, 19 Dec 2025 19:23:20 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 86DC710AA981D; Fri, 19 Dec 2025 20:23:18 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1766172200; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=56idGnW2rU9U+yKgXckx55lFlLnEcYAtFsLlIPjr5uo=; b=sw8oG0a0ySJnjHASF7yDy8+mZiGIHZPVU/i3inxbEyxXebYBktD4N5byFfV7DOLkCeaZuU 0EnxlBEwylNN0kQAu+COOSMbyn57jWpN7Z7763WE95oifQiIhmTOM//aF7LZS0NwKkblvh dAgJ2iun0LkS9xN4e26eKGTCfS0qIK0IKezftTPt6JVrGlzrpVkLaPV5RKNy1M2WQlZCLL U6HGBuMcXy1MAdwXShKy8U3AfQ01j9YsVa57+BlOK5u/e7iFL45OycE4pHHlsxFqwKYi/B SNwxf3yWTblKTdPb0thXZnhlf0iDjELcJJmJAXQ3OiTlY1vaYkNmZu9eASQ13w== From: "Miquel Raynal (Schneider Electric)" Date: Fri, 19 Dec 2025 20:22:09 +0100 Subject: [PATCH 07/13] spi: cadence-qspi: Fix probe error path and remove Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-schneider-6-19-rc1-qspi-v1-7-8ad505173e44@bootlin.com> References: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> In-Reply-To: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The probe has been modified by many different users, it is hard to track history, but for sure its current state is partially broken. One easy rule to follow is to drop/free/release the resources in the opposite order they have been queried. Fix the labels, the order for freeing the resources, and add the missing DMA channel step. Replicate these changes in the remove path as well. Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 45 ++++++++++++++++++++++-------------= ---- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index f59f3a8dccf5..ff0ddd2c0d41 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1890,7 +1890,7 @@ static int cqspi_probe(struct platform_device *pdev) ret =3D clk_prepare_enable(cqspi->clk); if (ret) { dev_err(dev, "Cannot enable QSPI clock.\n"); - goto probe_clk_failed; + goto disable_rpm; } =20 /* Obtain QSPI reset control */ @@ -1898,14 +1898,14 @@ static int cqspi_probe(struct platform_device *pdev) if (IS_ERR(rstc)) { ret =3D PTR_ERR(rstc); dev_err(dev, "Cannot get QSPI reset.\n"); - goto probe_reset_failed; + goto disable_clk; } =20 rstc_ocp =3D devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); if (IS_ERR(rstc_ocp)) { ret =3D PTR_ERR(rstc_ocp); dev_err(dev, "Cannot get QSPI OCP reset.\n"); - goto probe_reset_failed; + goto disable_clk; } =20 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { @@ -1913,7 +1913,7 @@ static int cqspi_probe(struct platform_device *pdev) if (IS_ERR(rstc_ref)) { ret =3D PTR_ERR(rstc_ref); dev_err(dev, "Cannot get QSPI REF reset.\n"); - goto probe_reset_failed; + goto disable_clk; } reset_control_assert(rstc_ref); reset_control_deassert(rstc_ref); @@ -1955,7 +1955,7 @@ static int cqspi_probe(struct platform_device *pdev) if (ddata->jh7110_clk_init) { ret =3D cqspi_jh7110_clk_init(pdev, cqspi); if (ret) - goto probe_reset_failed; + goto disable_clk; } if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) cqspi->disable_stig_mode =3D true; @@ -1963,7 +1963,7 @@ static int cqspi_probe(struct platform_device *pdev) if (ddata->quirks & CQSPI_DMA_SET_MASK) { ret =3D dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); if (ret) - goto probe_reset_failed; + goto disable_clks; } } =20 @@ -1974,7 +1974,7 @@ static int cqspi_probe(struct platform_device *pdev) pdev->name, cqspi); if (ret) { dev_err(dev, "Cannot request IRQ.\n"); - goto probe_reset_failed; + goto disable_clks; } =20 cqspi_wait_idle(cqspi); @@ -1995,7 +1995,7 @@ static int cqspi_probe(struct platform_device *pdev) ret =3D cqspi_setup_flash(cqspi); if (ret) { dev_err(dev, "failed to setup flash parameters %d\n", ret); - goto probe_setup_failed; + goto disable_controller; } =20 host->num_chipselect =3D cqspi->num_chipselect; @@ -2006,13 +2006,13 @@ static int cqspi_probe(struct platform_device *pdev) if (cqspi->use_direct_mode) { ret =3D cqspi_request_mmap_dma(cqspi); if (ret =3D=3D -EPROBE_DEFER) - goto probe_setup_failed; + goto disable_controller; } =20 ret =3D spi_register_controller(host); if (ret) { dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); - goto probe_setup_failed; + goto release_dma_chan; } =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { @@ -2021,15 +2021,21 @@ static int cqspi_probe(struct platform_device *pdev) } =20 return 0; -probe_setup_failed: - if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) - pm_runtime_disable(dev); + +release_dma_chan: + if (cqspi->rx_chan) + dma_release_channel(cqspi->rx_chan); +disable_controller: cqspi_controller_enable(cqspi, 0); -probe_reset_failed: +disable_clks: if (cqspi->is_jh7110) cqspi_jh7110_disable_clk(pdev, cqspi); +disable_clk: clk_disable_unprepare(cqspi->clk); -probe_clk_failed: +disable_rpm: + if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) + pm_runtime_disable(dev); + return ret; } =20 @@ -2047,18 +2053,19 @@ static void cqspi_remove(struct platform_device *pd= ev) cqspi_wait_idle(cqspi); =20 spi_unregister_controller(cqspi->host); - cqspi_controller_enable(cqspi, 0); =20 if (cqspi->rx_chan) dma_release_channel(cqspi->rx_chan); =20 - if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) - if (pm_runtime_get_sync(&pdev->dev) >=3D 0) - clk_disable(cqspi->clk); + cqspi_controller_enable(cqspi, 0); =20 if (cqspi->is_jh7110) cqspi_jh7110_disable_clk(pdev, cqspi); =20 + if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) + if (pm_runtime_get_sync(&pdev->dev) >=3D 0) + clk_disable(cqspi->clk); + if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); --=20 2.51.1 From nobody Mon Feb 9 17:01:38 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3E3833F392 for ; Fri, 19 Dec 2025 19:23:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172210; cv=none; b=QZTDeJOhbQ75p+6eTw5K1KPzUAW1PUT20mIar9C/2I5m/Bz2GYvY0dHIQtVYuPvDrETarWabAkmgcwl8/HPix1hPNscEZk1MsGiVQ+l29zseo/Zlb+9q5DUepU5Orx/u1r68BYnhaSTdIoV9rGZv3fndD2X+h+1P+aJboxkLGvY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172210; c=relaxed/simple; bh=Xg6XHj6KozlX4NrGzKx/YCl8Yj2IOOPWG22yyPcuZ80=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Fri, 19 Dec 2025 19:23:26 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 461F510AA981E; Fri, 19 Dec 2025 20:23:20 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1766172201; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=PT1SPgDsRcvNYZ5/SapnZsLtcwfzwA7IG18t6F0iYJk=; b=Gj+1Z6hFqsWd4w22uR6ASCST6fEewFiYRrbbGGa97OMKH8pS3pwQM4HYaLFiWVGPZxcC+h myYkDo7dJAnFzASv0oc9PLXa2dqp4MpOReQHy3fLoTBWF+eyiIYYAN5JBoehCgMn84ExC6 8+ycMuT1OnI1Dx8Hb+O/Dn+NNPp6twkg/AfnVsL9bocC6j9YuSCK1iMdYSB6AqWG6Bhqzd dt7k+Ot+pqwm4ANkwVT7BlO535ZQL6jB+Zu/b70gSprkslPDXBDdvuLjDp4syAb3XoWXnZ 0RAlNDGQxu/LSTZs35pxOC+OSJb6JSLXNjGJce2MmG8kdg0awFIJxQJa49tHHA== From: "Miquel Raynal (Schneider Electric)" Date: Fri, 19 Dec 2025 20:22:10 +0100 Subject: [PATCH 08/13] spi: cadence-qspi: Try hard to disable the clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-schneider-6-19-rc1-qspi-v1-8-8ad505173e44@bootlin.com> References: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> In-Reply-To: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In the remove path, we should try hard to perform all steps as we simply cannot fail. The "no runtime PM" quirk must only alter the state of the RPM core, but the clocks should still be disabled if that is possible. Move the disable call outside of the RPM quirk. Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index ff0ddd2c0d41..f282a06ba383 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -2044,6 +2044,7 @@ static void cqspi_remove(struct platform_device *pdev) const struct cqspi_driver_platdata *ddata; struct cqspi_st *cqspi =3D platform_get_drvdata(pdev); struct device *dev =3D &pdev->dev; + int ret =3D 0; =20 ddata =3D of_device_get_match_data(dev); =20 @@ -2063,8 +2064,10 @@ static void cqspi_remove(struct platform_device *pde= v) cqspi_jh7110_disable_clk(pdev, cqspi); =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) - if (pm_runtime_get_sync(&pdev->dev) >=3D 0) - clk_disable(cqspi->clk); + ret =3D pm_runtime_get_sync(&pdev->dev); + + if (ret >=3D 0) + clk_disable(cqspi->clk); =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { pm_runtime_put_sync(&pdev->dev); --=20 2.51.1 From nobody Mon Feb 9 17:01:38 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC08233F8AA; Fri, 19 Dec 2025 19:23:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172213; cv=none; b=tExlkz79tn25zDe4WAZmyhMBAJBhsnp9rRTkN+873xk651cVuTblGxaB0W7g3EemZ8bIAG833UQ8nLsOxr2c6sEOaDafUm9vjDQYXYYJxuTwvXSvX94CaBEtAw0h+LGI+wJeTPHgRebt4oiIOlbnQLvq6mp4e5GrbMrjfrUN7EA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172213; c=relaxed/simple; bh=WR/c1HEjMAOZRTjCDbKMwKXr2rjYDPmUYw4v3La4RB8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=muuDYcPxTwRsBW25rLQc/GnTOWd+0MO0uUxblj6seJnWHk7cOS60/0G0807MU7tfDktqAeNBYL30QnxnEMHMJYHNF8VnHvusfjXTWK48IDVON1sCTeKEmazU3wzFfSqa3uOLMbUd9Yq14mj/prdbKWd/a1kY9vmPKXqt6pEtT+0= ARC-Authentication-Results: i=1; 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Fri, 19 Dec 2025 20:23:25 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1766172207; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=5Ai2GrQNhNZ2L7dr/AUzs6yHCVvf+CgSk3LzomjMofc=; b=pMs/4OzavTTAkgU6/PMUlGj+rXVwTGVFf9OCsnDaxQRoDz/9yOzwR3yCoJoJq3LBWlcY/f WJVMAmk7DN7VOW1jgkOtWRFehaVNUXUiiuz1myrNIcUvmDelShOCdosrMPFOp20pY/4p/I zxdAj2Brn6V/dFHnCuFi2c+lbECRp5inxRwRYzTDU/Sm3Wl2f66O/wcEzt8aDn9Dv2r1GL lvk7+NU+Jx5oUh6+RxdcRNx3F7alj4nDMX5B8mK9eCPyecB1ouHDdoE+a2S4+z07n4MRIc Mi+w4wi5puDOdfi/Z2DhZNYJydJYbonSy07EhD7Q7soV/fm4cZKYWhGMns9HBg== From: "Miquel Raynal (Schneider Electric)" Date: Fri, 19 Dec 2025 20:22:11 +0100 Subject: [PATCH 09/13] spi: cadence-qspi: Kill cqspi_jh7110_clk_init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-schneider-6-19-rc1-qspi-v1-9-8ad505173e44@bootlin.com> References: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> In-Reply-To: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This controller can be fed by either a main "ref" clock, or three clocks ("ref" again, "ahb", "apb"). In practice, it is likely that all controllers have the same inputs, but a single clock feeds the three interfaces (ref is used for controlling the external interface, ahb/apb the internal ones). Handling these clocks is in no way SoC specific, only the number of expected clocks may change. Plus, we will soon be adding another controller requiring an AHB and an APB clock as well, so it is time to align the whole clock handling. Furthermore, the use of the cqspi_jh7110_clk_init() helper, which specifically grabs and enables the "ahb" and "apb" clocks, is a bit convoluted: - only the JH7110 compatible provides the ->jh7110_clk_init() callback, - in the probe, if the above callback is set in the driver data, the driver does not call the callback (!) but instead calls the helper directly (?), - in the helper, the is_jh7110 boolean is set. This logic does not make sense. Instead: - in the probe, set the is_jh7110 boolean based on the compatible, - collect all available clocks with the "bulk" helper, - enable the extra clocks if they are available, - kill the SoC specific cqspi_jh7110_clk_init() helper. This also allows to group the clock handling instead of depending on the driver data pointer, which further simplifies the error path and the remove callback. Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 120 ++++++++++++----------------------= ---- 1 file changed, 37 insertions(+), 83 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index f282a06ba383..3972bca5c4a9 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -55,7 +55,8 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT= _MAX); #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) =20 enum { - CLK_QSPI_APB =3D 0, + CLK_QSPI_REF =3D 0, + CLK_QSPI_APB, CLK_QSPI_AHB, CLK_QSPI_NUM, }; @@ -76,8 +77,7 @@ struct cqspi_flash_pdata { struct cqspi_st { struct platform_device *pdev; struct spi_controller *host; - struct clk *clk; - struct clk *clks[CLK_QSPI_NUM]; + struct clk_bulk_data clks[CLK_QSPI_NUM]; unsigned int sclk; =20 void __iomem *iobase; @@ -121,8 +121,6 @@ struct cqspi_driver_platdata { int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, u_char *rxbuf, loff_t from_addr, size_t n_rx); u32 (*get_dma_status)(struct cqspi_st *cqspi); - int (*jh7110_clk_init)(struct platform_device *pdev, - struct cqspi_st *cqspi); }; =20 /* Operation timeout value */ @@ -1769,61 +1767,20 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi) return 0; } =20 -static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqsp= i_st *cqspi) -{ - static struct clk_bulk_data qspiclk[] =3D { - { .id =3D "apb" }, - { .id =3D "ahb" }, - }; - - int ret =3D 0; - - ret =3D devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk); - if (ret) { - dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__); - return ret; - } - - cqspi->clks[CLK_QSPI_APB] =3D qspiclk[0].clk; - cqspi->clks[CLK_QSPI_AHB] =3D qspiclk[1].clk; - - ret =3D clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]); - if (ret) { - dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__); - return ret; - } - - ret =3D clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]); - if (ret) { - dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__); - goto disable_apb_clk; - } - - cqspi->is_jh7110 =3D true; - - return 0; - -disable_apb_clk: - clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); - - return ret; -} - -static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct = cqspi_st *cqspi) -{ - clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]); - clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); -} static int cqspi_probe(struct platform_device *pdev) { const struct cqspi_driver_platdata *ddata; struct reset_control *rstc, *rstc_ocp, *rstc_ref; + static const char *clk_ids[CLK_QSPI_NUM] =3D { + [CLK_QSPI_REF] =3D "ref", + [CLK_QSPI_APB] =3D "apb", + [CLK_QSPI_AHB] =3D "ahb", + }; struct device *dev =3D &pdev->dev; struct spi_controller *host; struct resource *res_ahb; struct cqspi_st *cqspi; - int ret; - int irq; + int ret, i, irq; =20 host =3D devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi)); if (!host) @@ -1835,10 +1792,11 @@ static int cqspi_probe(struct platform_device *pdev) host->dev.of_node =3D pdev->dev.of_node; =20 cqspi =3D spi_controller_get_devdata(host); + if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) + cqspi->is_jh7110 =3D true; =20 cqspi->pdev =3D pdev; cqspi->host =3D host; - cqspi->is_jh7110 =3D false; cqspi->ddata =3D ddata =3D of_device_get_match_data(dev); platform_set_drvdata(pdev, cqspi); =20 @@ -1849,12 +1807,17 @@ static int cqspi_probe(struct platform_device *pdev) return -ENODEV; } =20 - /* Obtain QSPI clock. */ - cqspi->clk =3D devm_clk_get(dev, NULL); - if (IS_ERR(cqspi->clk)) { - dev_err(dev, "Cannot claim QSPI clock.\n"); - ret =3D PTR_ERR(cqspi->clk); - return ret; + /* Obtain QSPI clocks. */ + for (i =3D 0; i < CLK_QSPI_NUM; ++i) + cqspi->clks[i].id =3D clk_ids[i]; + + ret =3D devm_clk_bulk_get_optional(dev, CLK_QSPI_NUM, cqspi->clks); + if (ret) + return dev_err_probe(dev, ret, "Failed to get clocks\n"); + + if (!cqspi->clks[CLK_QSPI_REF].clk) { + dev_err(dev, "Cannot claim mandatory QSPI ref clock.\n"); + return -ENODEV; } =20 /* Obtain and remap controller address. */ @@ -1886,10 +1849,9 @@ static int cqspi_probe(struct platform_device *pdev) if (ret) return ret; =20 - - ret =3D clk_prepare_enable(cqspi->clk); + ret =3D clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); if (ret) { - dev_err(dev, "Cannot enable QSPI clock.\n"); + dev_err(dev, "Cannot enable QSPI clocks.\n"); goto disable_rpm; } =20 @@ -1898,22 +1860,22 @@ static int cqspi_probe(struct platform_device *pdev) if (IS_ERR(rstc)) { ret =3D PTR_ERR(rstc); dev_err(dev, "Cannot get QSPI reset.\n"); - goto disable_clk; + goto disable_clks; } =20 rstc_ocp =3D devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); if (IS_ERR(rstc_ocp)) { ret =3D PTR_ERR(rstc_ocp); dev_err(dev, "Cannot get QSPI OCP reset.\n"); - goto disable_clk; + goto disable_clks; } =20 - if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { + if (cqspi->is_jh7110) { rstc_ref =3D devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); if (IS_ERR(rstc_ref)) { ret =3D PTR_ERR(rstc_ref); dev_err(dev, "Cannot get QSPI REF reset.\n"); - goto disable_clk; + goto disable_clks; } reset_control_assert(rstc_ref); reset_control_deassert(rstc_ref); @@ -1925,7 +1887,7 @@ static int cqspi_probe(struct platform_device *pdev) reset_control_assert(rstc_ocp); reset_control_deassert(rstc_ocp); =20 - cqspi->master_ref_clk_hz =3D clk_get_rate(cqspi->clk); + cqspi->master_ref_clk_hz =3D clk_get_rate(cqspi->clks[CLK_QSPI_REF].clk); host->max_speed_hz =3D cqspi->master_ref_clk_hz; =20 /* write completion is supported by default */ @@ -1951,12 +1913,6 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->slow_sram =3D true; if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) cqspi->apb_ahb_hazard =3D true; - - if (ddata->jh7110_clk_init) { - ret =3D cqspi_jh7110_clk_init(pdev, cqspi); - if (ret) - goto disable_clk; - } if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) cqspi->disable_stig_mode =3D true; =20 @@ -2028,10 +1984,7 @@ static int cqspi_probe(struct platform_device *pdev) disable_controller: cqspi_controller_enable(cqspi, 0); disable_clks: - if (cqspi->is_jh7110) - cqspi_jh7110_disable_clk(pdev, cqspi); -disable_clk: - clk_disable_unprepare(cqspi->clk); + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); disable_rpm: if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) pm_runtime_disable(dev); @@ -2060,14 +2013,12 @@ static void cqspi_remove(struct platform_device *pd= ev) =20 cqspi_controller_enable(cqspi, 0); =20 - if (cqspi->is_jh7110) - cqspi_jh7110_disable_clk(pdev, cqspi); =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) ret =3D pm_runtime_get_sync(&pdev->dev); =20 if (ret >=3D 0) - clk_disable(cqspi->clk); + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { pm_runtime_put_sync(&pdev->dev); @@ -2080,15 +2031,19 @@ static int cqspi_runtime_suspend(struct device *dev) struct cqspi_st *cqspi =3D dev_get_drvdata(dev); =20 cqspi_controller_enable(cqspi, 0); - clk_disable_unprepare(cqspi->clk); + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); return 0; } =20 static int cqspi_runtime_resume(struct device *dev) { struct cqspi_st *cqspi =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); + if (ret) + return ret; =20 - clk_prepare_enable(cqspi->clk); cqspi_wait_idle(cqspi); cqspi_controller_enable(cqspi, 0); cqspi_controller_init(cqspi); @@ -2171,7 +2126,6 @@ static const struct cqspi_driver_platdata versal2_osp= i =3D { =20 static const struct cqspi_driver_platdata jh7110_qspi =3D { .quirks =3D CQSPI_DISABLE_DAC_MODE, - .jh7110_clk_init =3D cqspi_jh7110_clk_init, }; =20 static const struct cqspi_driver_platdata pensando_cdns_qspi =3D { --=20 2.51.1 From nobody Mon Feb 9 17:01:38 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD91834107D for ; Fri, 19 Dec 2025 19:23:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="pWsuPRBx" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 4D3AE1A22FA; Fri, 19 Dec 2025 19:23:30 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 2269C6071D; Fri, 19 Dec 2025 19:23:30 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A42DB10AA981B; Fri, 19 Dec 2025 20:23:27 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1766172209; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=MJHGZZNMdeJVGktGftmqJKyOTlwEgokSeVQPziFIuBs=; b=pWsuPRBxQUCCvu+3vOPs0Aj9/BN+k+IgDdpKbTW4tHvTElJyQ/XBNwmXhhe1131ZVOf8+T GwnlDw9KY7EmwavwjYhQnjwn0xtEYjRVM8hIVDYnFd6FE6ZeClbr0cD5NonZFlXsq+yRAO bAvifaiNDGOCF2CULEMpgg15/Q91v2uEPOnubBIf9q1gDomzzDwYaGwgXobtI3aZCOCpQO clr+WU6eR7fNDHMKOBu7SOTNIc76+zGu79+F8F0o9U3UsyutGJFe+buNJESagNL0g/xuie ddgFb1+yzR0tJZObfDc2F12zBdTLNub0uR5aK2x+Jeofz1vFyqPcbr8WiYQkAw== From: "Miquel Raynal (Schneider Electric)" Date: Fri, 19 Dec 2025 20:22:12 +0100 Subject: [PATCH 10/13] spi: cadence-qspi: Add a flag for controllers without indirect access support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-schneider-6-19-rc1-qspi-v1-10-8ad505173e44@bootlin.com> References: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> In-Reply-To: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Renesas RZ/N1 QSPI controllers embed the Cadence IP with some limitations/simplifications. One of the is that only direct access is supported, none of the registers related to indirect writes are populated, so create a flag to avoid these accesses and make sure only direct accessors are called. Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 3972bca5c4a9..340f7a186d92 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -47,6 +47,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT= _MAX); #define CQSPI_SUPPORT_DEVICE_RESET BIT(8) #define CQSPI_DISABLE_STIG_MODE BIT(9) #define CQSPI_DISABLE_RUNTIME_PM BIT(10) +#define CQSPI_NO_INDIRECT_MODE BIT(11) =20 /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -1429,7 +1430,8 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f= _pdata, if (ret) return ret; =20 - if (cqspi->use_direct_mode && ((from + len) <=3D cqspi->ahb_size)) + if ((cqspi->use_direct_mode && ((from + len) <=3D cqspi->ahb_size)) || + (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) return cqspi_direct_read_execute(f_pdata, buf, from, len); =20 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && @@ -1630,19 +1632,20 @@ static void cqspi_controller_init(struct cqspi_st *= cqspi) /* Disable all interrupts. */ writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); =20 - /* Configure the SRAM split to 1:1 . */ - writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); + if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { + /* Configure the SRAM split to 1:1 . */ + writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); + /* Load indirect trigger address. */ + writel(cqspi->trigger_address, + cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); =20 - /* Load indirect trigger address. */ - writel(cqspi->trigger_address, - cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); - - /* Program read watermark -- 1/2 of the FIFO. */ - writel(cqspi->fifo_depth * cqspi->fifo_width / 2, - cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); - /* Program write watermark -- 1/8 of the FIFO. */ - writel(cqspi->fifo_depth * cqspi->fifo_width / 8, - cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); + /* Program read watermark -- 1/2 of the FIFO. */ + writel(cqspi->fifo_depth * cqspi->fifo_width / 2, + cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); + /* Program write watermark -- 1/8 of the FIFO. */ + writel(cqspi->fifo_depth * cqspi->fifo_width / 8, + cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); + } =20 /* Disable direct access controller */ if (!cqspi->use_direct_mode) { --=20 2.51.1 From nobody Mon Feb 9 17:01:38 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AA9F33CEA4; Fri, 19 Dec 2025 19:23:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172215; cv=none; b=jhSW4josgUQYs+NBz4MIe8lnyX0q26by2E1d99gl2oc/4v27AOuPDLHHbDSR1B3GuuRcLKkTRb2tMhqoUdI8WwAUmBRyjPVwBYqKZvaYStL58cZuqZPDh/RXntJP0VJbCpJhxpXtI9fppMQwMUY6mUUF6CYxLOdmDUvlKozBSsM= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-schneider-6-19-rc1-qspi-v1-11-8ad505173e44@bootlin.com> References: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> In-Reply-To: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Renesas RZ/N1 QSPI controllers embed the Cadence IP with some modifications. For instance, they feature a write protection of the direct mapping at the controller level, with this feature all data writes to the AHB region are aborted. Despite the fact that the flag setting write protection is disabled by default, Bootloaders may (and actually do) set it, so mark this feature as being available with a specific flag to, if applicable, make sure it is disabled. Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 340f7a186d92..ef036a65c628 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -48,6 +48,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT= _MAX); #define CQSPI_DISABLE_STIG_MODE BIT(9) #define CQSPI_DISABLE_RUNTIME_PM BIT(10) #define CQSPI_NO_INDIRECT_MODE BIT(11) +#define CQSPI_HAS_WR_PROTECT BIT(12) =20 /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -218,6 +219,8 @@ struct cqspi_driver_platdata { #define CQSPI_REG_IRQSTATUS 0x40 #define CQSPI_REG_IRQMASK 0x44 =20 +#define CQSPI_REG_WR_PROT_CTRL 0x58 + #define CQSPI_REG_INDIRECTRD 0x60 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) @@ -1647,6 +1650,10 @@ static void cqspi_controller_init(struct cqspi_st *c= qspi) cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); } =20 + /* Disable write protection at controller level */ + if (cqspi->ddata && cqspi->ddata->quirks & CQSPI_HAS_WR_PROTECT) + writel(0, cqspi->iobase + CQSPI_REG_WR_PROT_CTRL); + /* Disable direct access controller */ if (!cqspi->use_direct_mode) { reg =3D readl(cqspi->iobase + CQSPI_REG_CONFIG); --=20 2.51.1 From nobody Mon Feb 9 17:01:38 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8163340A70; Fri, 19 Dec 2025 19:23:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766172216; cv=none; b=SEljS4m+GOe4riTH3DEkPZZSrZk9wJR9ZPNfu1DIg/ILfoaEdpxnQxbG5T/3/nMZvJq7oEhOAR1eDdMEZDvcvLa3miWmRiZZkHPWiQWE/rNtATkm+hjeIZgiixJSOLhqgan3XPnsjR8iJdxQgtBEaoUuaKmpY5e2SxYwxOSZQUY= ARC-Message-Signature: i=1; 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Fri, 19 Dec 2025 19:23:08 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 4A7966071D; Fri, 19 Dec 2025 19:23:33 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 1E5DA10AA981C; Fri, 19 Dec 2025 20:23:31 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1766172212; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=H8DEEPmnp7dKOfpVV6DAwyTdXFHX+2yIaLDtP6fELWM=; b=hgbqDmtuceSH08b7JQw5kopwTYlsfPJrntqzp6nYZuN61yk/z/qisnoKFl3XpboV6thUTW rcL3p4kNUCMD8BBY3af5/R2eWv6AqGQQpF5CoA6zWuNivilZdskct9aQZpBJAHx0NDpa+2 AabXikJTirn71OshHS3BNZCbq2a3tN+7Gjq3XyZ/N6m7tYBlhPu9K7z2tLDtUKuq9gmKiW SuKPHBru+XIst2yC/zrA+ctmlSaK6GCuRBhKpQxfIrHhegzxYfJrLwZdDp+GwuylWZkpqW 2Q3AshFiYcBd5JzRUstgyHJK7Tb7jXQAOuGHK2JdQjb1k+6MX90bHP+pHzFREg== From: "Miquel Raynal (Schneider Electric)" Date: Fri, 19 Dec 2025 20:22:14 +0100 Subject: [PATCH 12/13] spi: cadence-qspi: Add support for the Renesas RZ/N1 controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-schneider-6-19-rc1-qspi-v1-12-8ad505173e44@bootlin.com> References: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> In-Reply-To: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Renesas RZ/N1 QSPI controllers embed a modified version of the Cadence IP with the following settings: - a limited bus clock range - no DTR support - no DMA - no useful interrupt flag - only direct accesses (no INDAC mode) - write protection The controller has been tested by running the SPI NOR check list with a custom RZ/N1D400 based board mounted with a Spansion s25fl128s1 quad SPI. Signed-off-by: Miquel Raynal (Schneider Electric) --- Output of the SPI NOR test procedure: s25fl128s1 0120184d0180 spansion xxd: /sys/bus/spi/devices/spi0.0/spi-nor/sfdp: No such file or directory md5sum: can't open '/sys/bus/spi/devices/spi0.0/spi-nor/sfdp': No such file= or directory 1+0 records in 1+0 records out Copied 65536 bytes from qspi_test to address 0x00000000 in flash Erased 65536 bytes from address 0x00000000 in flash Copied 65536 bytes from address 0x00000000 in flash to qspi_read 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0010000 Copied 65536 bytes from qspi_test to address 0x00000000 in flash Copied 65536 bytes from address 0x00000000 in flash to qspi_read 71f8b056a4bf5f51639a972dc9aac55eb8654fdc qspi_test 71f8b056a4bf5f51639a972dc9aac55eb8654fdc qspi_read Read speed: * page read speed is 6464 KiB/s * 2 page read speed is 9014 KiB/s * eraseblock read speed is 14222 KiB/s Write speed: * page write speed is 621 KiB/s * 2 page write speed is 626 KiB/s * eraseblock write speed is 633 KiB/s Erase speed: * erase speed is 617 KiB/s --- drivers/spi/spi-cadence-quadspi.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index ef036a65c628..03963857664b 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -110,6 +110,7 @@ struct cqspi_st { bool apb_ahb_hazard; =20 bool is_jh7110; /* Flag for StarFive JH7110 SoC */ + bool is_rzn1; /* Flag for Renesas RZN1 SoC */ bool disable_stig_mode; refcount_t refcount; refcount_t inflight_ops; @@ -1343,8 +1344,9 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *= f_pdata, * mode. So, we can not use direct mode when in DTR mode for writing * data. */ - if (!op->cmd.dtr && cqspi->use_direct_mode && - cqspi->use_direct_mode_wr && ((to + len) <=3D cqspi->ahb_size)) { + if ((!op->cmd.dtr && cqspi->use_direct_mode && + cqspi->use_direct_mode_wr && ((to + len) <=3D cqspi->ahb_size)) || + (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { memcpy_toio(cqspi->ahb_base + to, buf, len); return cqspi_wait_idle(cqspi); } @@ -1518,6 +1520,7 @@ static int cqspi_exec_mem_op(struct spi_mem *mem, con= st struct spi_mem_op *op) static bool cqspi_supports_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { + struct cqspi_st *cqspi =3D spi_controller_get_devdata(mem->spi->controlle= r); bool all_true, all_false; =20 /* @@ -1544,6 +1547,9 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem, /* A single opcode is supported, it will be repeated */ if ((op->cmd.opcode >> 8) !=3D (op->cmd.opcode & 0xFF)) return false; + + if (cqspi->is_rzn1) + return false; } else if (!all_false) { /* Mixed DTR modes are not supported. */ return false; @@ -1804,6 +1810,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi =3D spi_controller_get_devdata(host); if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) cqspi->is_jh7110 =3D true; + if (of_device_is_compatible(pdev->dev.of_node, "renesas,rzn1-qspi")) + cqspi->is_rzn1 =3D true; =20 cqspi->pdev =3D pdev; cqspi->host =3D host; @@ -1898,7 +1906,12 @@ static int cqspi_probe(struct platform_device *pdev) reset_control_deassert(rstc_ocp); =20 cqspi->master_ref_clk_hz =3D clk_get_rate(cqspi->clks[CLK_QSPI_REF].clk); - host->max_speed_hz =3D cqspi->master_ref_clk_hz; + if (!cqspi->is_rzn1) { + host->max_speed_hz =3D cqspi->master_ref_clk_hz; + } else { + host->max_speed_hz =3D cqspi->master_ref_clk_hz / 2; + host->min_speed_hz =3D cqspi->master_ref_clk_hz / 32; + } =20 /* write completion is supported by default */ cqspi->wr_completion =3D true; @@ -1969,7 +1982,7 @@ static int cqspi_probe(struct platform_device *pdev) if (ddata && (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET)) cqspi_device_reset(cqspi); =20 - if (cqspi->use_direct_mode) { + if (cqspi->use_direct_mode && !cqspi->is_rzn1) { ret =3D cqspi_request_mmap_dma(cqspi); if (ret =3D=3D -EPROBE_DEFER) goto disable_controller; @@ -2148,6 +2161,12 @@ static const struct cqspi_driver_platdata mobileye_e= yeq5_ospi =3D { CQSPI_RD_NO_IRQ, }; =20 +static const struct cqspi_driver_platdata renesas_rzn1_qspi =3D { + .hwcaps_mask =3D CQSPI_SUPPORTS_QUAD, + .quirks =3D CQSPI_NO_SUPPORT_WR_COMPLETION | CQSPI_RD_NO_IRQ | + CQSPI_HAS_WR_PROTECT | CQSPI_NO_INDIRECT_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] =3D { { .compatible =3D "cdns,qspi-nor", @@ -2189,6 +2208,10 @@ static const struct of_device_id cqspi_dt_ids[] =3D { .compatible =3D "amd,versal2-ospi", .data =3D &versal2_ospi, }, + { + .compatible =3D "renesas,rzn1-qspi", + .data =3D &renesas_rzn1_qspi, + }, { /* end of table */ } }; =20 --=20 2.51.1 From nobody Mon Feb 9 17:01:38 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5808E341645; 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bh=vrDLpxHj859p8IRaJPL2VCFLfV/CO+dPXle53aPPG2k=; b=M/3jeLfso9QC3scrnbpbpxrwsUmwSgQLUO3qFkUgkza6vUkUB0aBGLOx3WGy3ZxGK7pxne 4pKPRfjPP+b4FpoJG4HQMbSf+mD3EOLlFW3z5EOUrinJprCaFTWIjlV93akavKxIGKFom8 0vEuUzUmqU6FrmJDSq0XUckPcOjjH0kppt9p7YmxMgCeoeYKKGaxof5DE0Pn+eOe6a0gi/ IMGQt2Jy4MuTvntv24zhYq6W1+n0k1muwsc6c6flFXlxoM/oJWUJfh+XNfeyG/mg8VUS0V YhwRep+emxIZ1mWpObXwRXXQ6eJEhQSoWstNMYS8sIvdfIuXi5i9C86JKdek5w== From: "Miquel Raynal (Schneider Electric)" Date: Fri, 19 Dec 2025 20:22:15 +0100 Subject: [PATCH 13/13] ARM: dts: r9a06g032: Describe the QSPI controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-schneider-6-19-rc1-qspi-v1-13-8ad505173e44@bootlin.com> References: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> In-Reply-To: <20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add a node describing the QSPI controller. There are 2 clocks feeding this controller: - one for the reference clock - one that feeds both the ahb and the apb interfaces As the binding expect either the ref clock, or all three (ref, ahb and apb) clocks, it makes sense to provide the same clock twice. Signed-off-by: Miquel Raynal (Schneider Electric) --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index 8debb77803bb..a6f4670f5c45 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -66,6 +66,20 @@ soc { #size-cells =3D <1>; ranges; =20 + qspi0: spi@40005000 { + compatible =3D "renesas,r9a06g032-qspi", "renesas,rzn1-qspi", "cdns,qsp= i-nor"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x40005000 0x1000>, <0x10000000 0x10000000>; + interrupts =3D ; + clocks =3D <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSP= I0>, + <&sysctrl R9A06G032_HCLK_QSPI0>; + clock-names =3D "ref", "ahb", "apb"; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0>; + status =3D "disabled"; + }; + rtc0: rtc@40006000 { compatible =3D "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; reg =3D <0x40006000 0x1000>; --=20 2.51.1