From nobody Tue Feb 10 08:27:41 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5696626A09B for ; Fri, 19 Dec 2025 21:47:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180855; cv=none; b=X2O7rNTZc3OidJAzznIc7gh86N7WosVZRbkAmg5AYZKznOwrzWzCTouW96XbESDJvXs/6upEHQWYnftXoxifgw3J0Q6OhBZqQtWRczXEm8CB1oqToyUUgyNg0CiExijzCMo9h7hawO4OnwAse7omjf3gYuSBDuxaHVGT4m4fMYI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766180855; c=relaxed/simple; bh=3F7gkFszEoR0NT5TOLcxciKsxJPDu+9gutzYVWO1WQo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Z9ZBbPR53YYQY9bwMVQfOfZgjd5swvmVJB5YG9pC+6BgGypKDkQLDCS2+c3pLvUO4Wp+0xXtbIRe1UDbjKNK3GsKxIZXT6iOTuQpMSmv6Zc81MXqNYfI4niNgA3gxRO40qERmzKFiA8u3MxDJFqPCG0SE6IQAd0HRq2nMoWouW4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=kDIj/Est; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="kDIj/Est" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1766180851; bh=3F7gkFszEoR0NT5TOLcxciKsxJPDu+9gutzYVWO1WQo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kDIj/EstpThdU+kNSLHa/j55SfyWSfRickGU8TENs3y7fgm5XBrmbCrrqj7VlkrsL t2f4mbROxLXcCmVnQNonilCCV0AOXp7nq7ZKji+fCPset7EIpO/mvmz1G2O5TeILIY qZCRPrFUOSZLQ/ckrhUGuetPUnO+muDBMigeOeDM0FUUyoCA6OjwCAMaUm2slMyJ2i UVwCa2fJ5uwGFeeCXfM6rOot3oZTNvaCK+7OBcT8aj/LxFvE21EtBaZXLVAjfF2iQw XBIxOrYG8CLSSlF1QzIACZ2EgEdruUQ9UOgnaSsKNDHRO+rYR6jVziC6SHqeDj+Nbn BGob/20MVxtyA== Received: from localhost (unknown [82.79.138.145]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 6B40B17E1407; Fri, 19 Dec 2025 22:47:31 +0100 (CET) From: Cristian Ciocaltea Date: Fri, 19 Dec 2025 23:47:01 +0200 Subject: [PATCH v4 4/4] drm/rockchip: vop2: Support setting custom background color Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-rk3588-bgcolor-v4-4-2ff1127ea757@collabora.com> References: <20251219-rk3588-bgcolor-v4-0-2ff1127ea757@collabora.com> In-Reply-To: <20251219-rk3588-bgcolor-v4-0-2ff1127ea757@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Louis Chauvet , Haneen Mohammed , Melissa Wen Cc: Robert Mader , kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.3 The Rockchip VOP2 display controller allows configuring the background color of each video output port. Since a previous patch introduced the BACKGROUND_COLOR CRTC property, which defaults to solid black, make use of it when programming the hardware. Note the maximum precision allowed by the display controller is 10bpc, while the alpha component is not supported, hence ignored. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 13 ++++++++++++- drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 4 ++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 498df0ce4680..3a232d0d4acb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1554,6 +1554,7 @@ static void vop2_post_config(struct drm_crtc *crtc) struct vop2_video_port *vp =3D to_vop2_video_port(crtc); struct vop2 *vop2 =3D vp->vop2; struct drm_display_mode *mode =3D &crtc->state->adjusted_mode; + u64 bgcolor =3D crtc->state->background_color; u16 vtotal =3D mode->crtc_vtotal; u16 hdisplay =3D mode->crtc_hdisplay; u16 hact_st =3D mode->crtc_htotal - mode->crtc_hsync_start; @@ -1599,7 +1600,11 @@ static void vop2_post_config(struct drm_crtc *crtc) vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val); } =20 - vop2_vp_write(vp, RK3568_VP_DSP_BG, 0); + /* Background color is programmed with 10 bits of precision */ + val =3D FIELD_PREP(RK3568_VP_DSP_BG__DSP_BG_RED, DRM_ARGB64_GETR(bgcolor)= >> 6); + val |=3D FIELD_PREP(RK3568_VP_DSP_BG__DSP_BG_GREEN, DRM_ARGB64_GETG(bgcol= or) >> 6); + val |=3D FIELD_PREP(RK3568_VP_DSP_BG__DSP_BG_BLUE, DRM_ARGB64_GETB(bgcolo= r) >> 6); + vop2_vp_write(vp, RK3568_VP_DSP_BG, val); } =20 static int us_to_vertical_line(struct drm_display_mode *mode, int us) @@ -1984,6 +1989,10 @@ static int vop2_crtc_state_dump(struct drm_crtc *crt= c, struct seq_file *s) drm_get_bus_format_name(vcstate->bus_format)); seq_printf(s, "\toutput_mode[%x]", vcstate->output_mode); seq_printf(s, " color_space[%d]\n", vcstate->color_space); + seq_printf(s, "\tbackground color (10bpc): r=3D0x%x g=3D0x%x b=3D0x%x\n", + DRM_ARGB64_GETR(cstate->background_color) >> 6, + DRM_ARGB64_GETG(cstate->background_color) >> 6, + DRM_ARGB64_GETB(cstate->background_color) >> 6); seq_printf(s, " Display mode: %dx%d%s%d\n", mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p", drm_mode_vrefresh(mode)); @@ -2473,6 +2482,8 @@ static int vop2_create_crtcs(struct vop2 *vop2) return dev_err_probe(drm->dev, ret, "crtc init for video_port%d failed\n", i); =20 + drm_crtc_attach_background_color_property(&vp->crtc); + drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs); if (vop2->lut_regs) { const struct vop2_video_port_data *vp_data =3D &vop2_data->vp[vp->id]; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.h index 9124191899ba..37722652844a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h @@ -658,6 +658,10 @@ enum dst_factor_mode { #define RK3588_VP_CLK_CTRL__DCLK_OUT_DIV GENMASK(3, 2) #define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV GENMASK(1, 0) =20 +#define RK3568_VP_DSP_BG__DSP_BG_RED GENMASK(29, 20) +#define RK3568_VP_DSP_BG__DSP_BG_GREEN GENMASK(19, 10) +#define RK3568_VP_DSP_BG__DSP_BG_BLUE GENMASK(9, 0) + #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1) #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0) =20 --=20 2.51.2