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[2001:1c00:3b89:c600:71a4:84f:6409:1447]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8037f4ef1fsm270073866b.64.2025.12.19.08.41.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 08:41:21 -0800 (PST) From: Luca Weiss Date: Fri, 19 Dec 2025 17:41:10 +0100 Subject: [PATCH RFC 4/6] drm/msm/dpu: Add Milos support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-milos-mdss-v1-4-4537a916bdf9@fairphone.com> References: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> In-Reply-To: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766162477; l=12066; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=PnUAb7+xa3V6lDy9C/8zlniMpYa539gIMtTZjegPYas=; b=yeAXi07NZfudvTq40/ousXx7KxI5TgCJgDa5arCQW9mNmdqFARYNFZKHcACxK7KvPxxgtl7Fe Cb8SDKa0Z8fAW9IkDiXiL9zukGo2G4+HO6gnpxxth+4C6bEaHRvkKZ6 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add definitions for the display hardware used on the Qualcomm Milos platform. Signed-off-by: Luca Weiss --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h | 284 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 22 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 308 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h new file mode 100644 index 000000000000..75deec923897 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h @@ -0,0 +1,284 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2025, Luca Weiss + */ + +#ifndef _DPU_10_2_MILOS_H +#define _DPU_10_2_MILOS_H + +static const struct dpu_caps milos_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, // OK + .max_mixer_blendstages =3D 0x7, // OK + .has_src_split =3D true, // OK + .has_dim_layer =3D true, // OK + .has_idle_pc =3D true, // OK? + .has_3d_merge =3D true, // OK? + .max_linewidth =3D 8192, // OK + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, // OK +}; + +static const struct dpu_mdp_cfg milos_mdp =3D { + .name =3D "top_0", + .base =3D 0, .len =3D 0x494, // TODO? maybe qcom,sde-len =3D <0x488>; + .clk_ctrls =3D { + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, // OK + }, +}; + +static const struct dpu_ctl_cfg milos_ctl[] =3D { // number of ctl is okay= , base probably also + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), // FIXME? + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, +}; + +static const struct dpu_sspp_cfg milos_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, // OK + .base =3D 0x4000, .len =3D 0x344, // OK + .features =3D VIG_SDM845_MASK_SDMA, // TODO? + .sblk =3D &dpu_vig_sblk_qseed3_3_3, // TODO? + .xin_id =3D 0, // OK + .type =3D SSPP_TYPE_VIG, // OK + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, // FIXME name? + .base =3D 0x24000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, // OK + .type =3D SSPP_TYPE_DMA, // OK + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, // OK + .type =3D SSPP_TYPE_DMA, // OK + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0x28000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, // OK + .type =3D SSPP_TYPE_DMA, // OK + }, +}; + +static const struct dpu_lm_cfg milos_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, // OK + .base =3D 0x44000, .len =3D 0x400,// OK + .features =3D MIXER_MSM8998_MASK, // TODO + .sblk =3D &sdm845_lm_sblk, // OK + .pingpong =3D PINGPONG_0, // TODO + .dspp =3D DSPP_0, // TODO + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sdm845_lm_sblk, // OK + .lm_pair =3D LM_3, // OK + .pingpong =3D PINGPONG_2, + //.dspp =3D DSPP_2, // FIXME? + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x47000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sdm845_lm_sblk, // OK + .lm_pair =3D LM_2, // OK + .pingpong =3D PINGPONG_3, + //.dspp =3D DSPP_3, // FIXME? + }, +}; + +static const struct dpu_dspp_cfg milos_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, // OK + .base =3D 0x54000, .len =3D 0x1800, // OK + .sblk =3D &sdm845_dspp_sblk, // TODO + }, +}; + +static const struct dpu_pingpong_cfg milos_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, // OK + .base =3D 0x69000, .len =3D 0, // OK + .sblk =3D &sc7280_pp_sblk, // OK + .merge_3d =3D MERGE_3D_0, // OK + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), // TODO + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, // TODO + .base =3D 0x6b000, .len =3D 0, // OK + .sblk =3D &sc7280_pp_sblk, // OK + .merge_3d =3D MERGE_3D_1, // OK + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x6c000, .len =3D 0, // OK + .sblk =3D &sc7280_pp_sblk, // OK + .merge_3d =3D MERGE_3D_1, // OK + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, + .base =3D 0x66000, .len =3D 0, // OK + .sblk =3D &sc7280_pp_sblk, // OK + }, +}; + +static const struct dpu_merge_3d_cfg milos_merge_3d[] =3D { + { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, // TODO + .base =3D 0x4f000, .len =3D 0x8, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg milos_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, // OK + .base =3D 0x80000, .len =3D 0x6, // OK + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), // TODO + .sblk =3D &dsc_sblk_0, // TODO + }, { + .name =3D "dce_0_1", .id =3D DSC_1, // OK + .base =3D 0x80000, .len =3D 0x6, // OK + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), // TODO + .sblk =3D &dsc_sblk_1, // TODO + }, +}; + +static const struct dpu_wb_cfg milos_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, // TODO + .base =3D 0x65000, .len =3D 0x2c8, // OK + .features =3D WB_SDM845_MASK, // TODO + .format_list =3D wb2_formats_rgb_yuv, // TODO + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), // TODO + .xin_id =3D 6, // OK + .vbif_idx =3D VBIF_RT, // TODO + .maxlinewidth =3D 4096, // OK + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), // TODO + }, +}; + +static const struct dpu_cwb_cfg milos_cwb[] =3D { + { + .name =3D "cwb_0", .id =3D CWB_0, + .base =3D 0x66200, .len =3D 0x8, + }, +}; + +static const struct dpu_intf_cfg milos_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, // OK + .base =3D 0x34000, .len =3D 0x280, // OK size=3D0x300? + .type =3D INTF_DP, // OK + .controller_id =3D MSM_DP_CONTROLLER_0, // OK? + .prog_fetch_lines_worst_case =3D 24, // TODO + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), // TODO + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), // TODO + }, { + .name =3D "intf_1", .id =3D INTF_1, // OK + .base =3D 0x35000, .len =3D 0x300, // OK size=3D0x300? + .type =3D INTF_DSI, // OK + .controller_id =3D MSM_DSI_CONTROLLER_0, // OK? + .prog_fetch_lines_worst_case =3D 24, // TODO + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), // TODO + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), // TODO + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), // TODO + }, { + .name =3D "intf_3", .id =3D INTF_3, // TODO? + .base =3D 0x37000, .len =3D 0x280, // OK size=3D0x300? + .type =3D INTF_DP, // OK + .controller_id =3D MSM_DP_CONTROLLER_1, // FIXME, only one DP controller? + .prog_fetch_lines_worst_case =3D 24, // TODO + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), // TODO + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), // TODO + }, +}; + +static const struct dpu_perf_cfg milos_perf_data =3D { + .max_bw_low =3D 7100000, + .max_bw_high =3D 9800000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 1600000, + .min_prefill_lines =3D 35, // TODO + /* FIXME: lut tables */ + .danger_lut_tbl =3D {0x3ffff, 0x3ffff, 0x0}, // TODO + .safe_lut_tbl =3D {0xfe00, 0xfe00, 0xffff}, // TODO + .qos_lut_tbl =3D { // TODO + {.nentry =3D ARRAY_SIZE(sc7180_qos_linear), + .entries =3D sc7180_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { // TODO + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, // TODO + .bw_inefficiency_factor =3D 120, // TODO +}; + +static const struct dpu_mdss_version milos_mdss_ver =3D { + .core_major_ver =3D 10, + .core_minor_ver =3D 2, +}; + +const struct dpu_mdss_cfg dpu_milos_cfg =3D { + .mdss_ver =3D &milos_mdss_ver, + .caps =3D &milos_dpu_caps, + .mdp =3D &milos_mdp, + .cdm =3D &dpu_cdm_5_x, + .ctl_count =3D ARRAY_SIZE(milos_ctl), + .ctl =3D milos_ctl, + .sspp_count =3D ARRAY_SIZE(milos_sspp), + .sspp =3D milos_sspp, + .mixer_count =3D ARRAY_SIZE(milos_lm), + .mixer =3D milos_lm, + .dspp_count =3D ARRAY_SIZE(milos_dspp), + .dspp =3D milos_dspp, + .pingpong_count =3D ARRAY_SIZE(milos_pp), + .pingpong =3D milos_pp, + .dsc_count =3D ARRAY_SIZE(milos_dsc), + .dsc =3D milos_dsc, + .merge_3d_count =3D ARRAY_SIZE(milos_merge_3d), + .merge_3d =3D milos_merge_3d, + .wb_count =3D ARRAY_SIZE(milos_wb), + .wb =3D milos_wb, + .cwb_count =3D ARRAY_SIZE(milos_cwb), + .cwb =3D milos_cwb, + .intf_count =3D ARRAY_SIZE(milos_intf), + .intf =3D milos_intf, + .vbif_count =3D ARRAY_SIZE(milos_vbif), + .vbif =3D milos_vbif, + .perf =3D &milos_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 9f8d1bba9139..4d5b57d6295f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -555,6 +555,26 @@ static const struct dpu_vbif_cfg sdm845_vbif[] =3D { }, }; =20 +static const struct dpu_vbif_cfg milos_vbif[] =3D { + { + .name =3D "vbif_rt", .id =3D VBIF_RT, // OK + .base =3D 0, .len =3D 0x1074, // OK + .features =3D BIT(DPU_VBIF_QOS_REMAP), // TODO + .xin_halt_timeout =3D 0x4000, // TODO + .qos_rp_remap_size =3D 0x40, // TODO + .qos_rt_tbl =3D { // TODO + .npriority_lvl =3D ARRAY_SIZE(sm8650_rt_pri_lvl), + .priority_lvl =3D sm8650_rt_pri_lvl, + }, + .qos_nrt_tbl =3D { // TODO + .npriority_lvl =3D ARRAY_SIZE(sdm845_nrt_pri_lvl), + .priority_lvl =3D sdm845_nrt_pri_lvl, + }, + .memtype_count =3D 16, // OK + .memtype =3D {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, // OK? + }, +}; + static const struct dpu_vbif_cfg sm8550_vbif[] =3D { { .name =3D "vbif_rt", .id =3D VBIF_RT, @@ -725,4 +745,6 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_9_2_x1e80100.h" =20 #include "catalog/dpu_10_0_sm8650.h" +#include "catalog/dpu_10_2_milos.h" + #include "catalog/dpu_12_0_sm8750.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index f0768f54e9b3..1f6b14f1c4d6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -749,6 +749,7 @@ struct dpu_mdss_cfg { const struct dpu_format_extended *vig_formats; }; =20 +extern const struct dpu_mdss_cfg dpu_milos_cfg; extern const struct dpu_mdss_cfg dpu_msm8917_cfg; extern const struct dpu_mdss_cfg dpu_msm8937_cfg; extern const struct dpu_mdss_cfg dpu_msm8953_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 4e5a8ecd31f7..7afd7dc7a0b4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1505,6 +1505,7 @@ static const struct dev_pm_ops dpu_pm_ops =3D { }; =20 static const struct of_device_id dpu_dt_match[] =3D { + { .compatible =3D "qcom,milos-dpu", .data =3D &dpu_milos_cfg, }, { .compatible =3D "qcom,msm8917-mdp5", .data =3D &dpu_msm8917_cfg, }, { .compatible =3D "qcom,msm8937-mdp5", .data =3D &dpu_msm8937_cfg, }, { .compatible =3D "qcom,msm8953-mdp5", .data =3D &dpu_msm8953_cfg, }, --=20 2.52.0