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[2001:1c00:3b89:c600:71a4:84f:6409:1447]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8037f4ef1fsm270073866b.64.2025.12.19.08.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 08:41:19 -0800 (PST) From: Luca Weiss Date: Fri, 19 Dec 2025 17:41:08 +0100 Subject: [PATCH RFC 2/6] drm/msm/dsi: add support for DSI-PHY on Milos Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-milos-mdss-v1-2-4537a916bdf9@fairphone.com> References: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> In-Reply-To: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766162477; l=2966; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=ohNmR27RG7BPFcETLws/RzDvloxNbzu49qmgmsyHzbg=; b=u8kMZZ5XCdBAQqVc75EEYESeLgtSwulD/FZN1Nv9WKgIfHtzElwwgfCg8ePkE2aG/YwOFsu88 +7CWnoGudYNBpfHSe96RbCE5NSbFfaFoIDAKT4j6P4V8E4RsRpxpuIQ X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add DSI PHY support for the Milos platform. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 24 ++++++++++++++++++++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index 4ea681130dba..0ac5029d3eb4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -571,6 +571,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_5nm_8350_cfgs }, { .compatible =3D "qcom,sm8450-dsi-phy-5nm", .data =3D &dsi_phy_5nm_8450_cfgs }, + { .compatible =3D "qcom,milos-dsi-phy-4nm", + .data =3D &dsi_phy_4nm_milos_cfgs }, { .compatible =3D "qcom,sm8550-dsi-phy-4nm", .data =3D &dsi_phy_4nm_8550_cfgs }, { .compatible =3D "qcom,sm8650-dsi-phy-4nm", diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index 3cbf08231492..011bee593199 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -61,6 +61,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_milos_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index c5e1d2016bcc..6ca45e5c2cc0 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -1436,6 +1436,30 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cf= gs =3D { .quirks =3D DSI_PHY_7NM_QUIRK_V5_2, }; =20 +const struct msm_dsi_phy_cfg dsi_phy_4nm_milos_cfgs =3D { + .has_phy_lane =3D true, + .regulator_data =3D dsi_phy_7nm_98000uA_regulators, + .num_regulators =3D ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), + .ops =3D { + .enable =3D dsi_7nm_phy_enable, + .disable =3D dsi_7nm_phy_disable, + .pll_init =3D dsi_pll_7nm_init, + .save_pll_state =3D dsi_7nm_pll_save_state, + .restore_pll_state =3D dsi_7nm_pll_restore_state, + .set_continuous_clock =3D dsi_7nm_set_continuous_clock, + }, + // FIXME not sure about these rate values + .min_pll_rate =3D 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate =3D 5000000000UL, +#else + .max_pll_rate =3D ULONG_MAX, +#endif + .io_start =3D { 0xae95000 }, + .num_dsi_phy =3D 1, + .quirks =3D DSI_PHY_7NM_QUIRK_V5_2, +}; + const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs =3D { .has_phy_lane =3D true, .regulator_data =3D dsi_phy_7nm_98400uA_regulators, --=20 2.52.0