From nobody Mon Feb 9 09:00:43 2026 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C708C329E46 for ; Fri, 19 Dec 2025 16:41:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766162485; cv=none; b=noBMr8+mz6j/EjenPl0uuj2jaoHwxGoAe6m1LszlYzZlDRhdWkHhTXfgh0fLmaVJEbKsMnsJe2psC6YNAlTHGdNdN2zfVwg1iDJhoKLi9owXhhdGgexwQdHP34ee89tQIsTKVPXqt7osj55QbI1XZixBxfsTtq20gMuLg3wtfxA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766162485; c=relaxed/simple; bh=t5HFnNXhnxSLu0HbcMB5zyaLqy0cPi/BThYL9zb/2sc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=D6lc5GNvla1N1OSaLy2AuQFz9S2uAdm101RshtKfVLd5OtkW5bTqBbn6pbvMRWqeu96fC3pv+bqIzgIlFXIOEpUDoU9OjrCSQ84alKx/Sd+UgwN0HM5HPCD71g1Eg11Ekd7kd+7Yd7UcDDTUaBvgTn86i664g8B/9MIB1EkEIGo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=EAuzqlZv; arc=none smtp.client-ip=209.85.208.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="EAuzqlZv" Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-64d02c01865so44491a12.1 for ; Fri, 19 Dec 2025 08:41:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1766162479; x=1766767279; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mFh6b7zgZI1HsA8s8Bqqbi9ow8eV3Aoe737Rsj3OItI=; b=EAuzqlZvGEuA4Dns0/pGJOnoH4TOeuXnSflTgprotvvtjilsboHqjLctUdDyEI6bER d5/+QVzMuzMVzlM0vemey8EHzlC0GeUCD9lTvk9pKqDX0MWkOfg0rM63coyzRRRkt6BL xuDdYy48+oy5ZPbe/eaVQuHdgoSPA83dlETnVz1zTQV0uJQ1xIa9TOgHJh48DK6b36iv ZFQn9JO/QaFq4BjjQI40yTvighVrSsg+x+HVYOIudIOZHdaJzEQS5lFx2XSzaGbfop0P 3Sbws0tEZixigMIMtjJokRogT6YH/1aSsjytJxgvMrO1Amf2Ls4EFEIrdOcAP6iohKvM gCXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766162479; x=1766767279; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=mFh6b7zgZI1HsA8s8Bqqbi9ow8eV3Aoe737Rsj3OItI=; b=JnX2dSKWhExNxXqdMYsUcWf9ZWcTXdi3UBjAiWV++ucDK4ms3FSuxO569Tb3Ogy0l5 JrCWC4Bj1J3X8ij2SXVWF/YF6XGNb4afHC1MfeOEBCo2lPV0Y94TwBu7eW4tApeG9SxB NwNR1oq+AUBSJA8oa9i6RI5tgll8yyxwhni6dwazvU8wLX8vtj2pWcDeSnkxoXv1Bsj9 Q1uhSPQA6SGlWHm8NpRdpBpsUB7XnkpnqcarKVcoF5RMxw/cftBZQPZRe9dvqotSK2ek qRVp2jE/3NQ77brPpt+AyIvQleWhRTfet3QBzrx6EDSn1uRmuvAuuY1ZzT/BlZH2aRqi fM2w== X-Forwarded-Encrypted: i=1; AJvYcCUNru40FwA24uuP2WaD0vRBdvZSdb6U4jMdX38yoinmLdB8xiXMRQQnoHc6Dehaj9RWNpb8F9gFBXVdM10=@vger.kernel.org X-Gm-Message-State: AOJu0YyCP5w1qhSxisoAr2yOORmJ1JKKv7mjPBms7NtEO9izm5XrRBhE zww04QDNdQ174siLOLYtgHkQ2iorEE2RMWyBbNQTCjhKEm3Dub9WaLnmvqbUaAMIg8c= X-Gm-Gg: AY/fxX5Y+F7vZIWHk2fpa3z1m1aEU3RBCm5pClUED0zRqXqVhJzlJ5MqVHaDMIS/pZ2 lEBI3iAOwDj50naZXpSukVbvznVn2ZUmAWhFwEIy/bhR4cuc1gjer4WzKpY+6lfAp5THEOByReh M4VZIuBP9evT+5Q8AvNH3CGQbkY0UzEp/d2EWoOZ3jh1IZSOzhALJy+1sDSDuT70ZIdayxbWxFQ /el4WvrryT9LT2fW2OhOqBq7baeHocY4DP//vJBigTj6l3G3wiGcSssWl7rtTN6dHxJx4TtTsG7 Xu13NeKZYF4q3VEPP81rK5XEPstvBs97okDmv+9Tob0ynZLZ/JRgLpl1GVDuGgAWaK2Ny85Gp+a oTS2feMbY8kZX8wuCz25svh6Vs6glKsI4YDRLlwqxliLHIr4ceBw6+PyB3AuaWASmji7BtYBaww DcIHWnHFcJLbKznAXD/a0S8ytxSO31KaMjSpyhIE858ZXZZK9jHHGwNMda2ZLXLKwiwoC7HahZ8 m5/Oy5DdzbxX392Qz8MXoANjpeoB+46H6Y= X-Google-Smtp-Source: AGHT+IG5xQQDju37djeKp8Zgcj7rgGU7z6CWHlLL/w7AfRHVUi9V/ccXZ3Gb0icbkIvDeWOUnP8NhQ== X-Received: by 2002:a17:907:1c1d:b0:b7c:f77c:42e7 with SMTP id a640c23a62f3a-b80371d37b9mr396657766b.43.1766162479431; Fri, 19 Dec 2025 08:41:19 -0800 (PST) Received: from [192.168.178.182] (2001-1c00-3b89-c600-71a4-084f-6409-1447.cable.dynamic.v6.ziggo.nl. [2001:1c00:3b89:c600:71a4:84f:6409:1447]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8037f4ef1fsm270073866b.64.2025.12.19.08.41.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 08:41:19 -0800 (PST) From: Luca Weiss Date: Fri, 19 Dec 2025 17:41:07 +0100 Subject: [PATCH RFC 1/6] soc: qcom: ubwc: Add config for Milos Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-milos-mdss-v1-1-4537a916bdf9@fairphone.com> References: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> In-Reply-To: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766162477; l=1527; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=t5HFnNXhnxSLu0HbcMB5zyaLqy0cPi/BThYL9zb/2sc=; b=EoGcG/sMLsZ+n/tQW2JV/CykTnYFk5wscZuExCSdKs6oC1UTb3wWbgCcx7IrWQcQSUcMonII5 z2uIyuCf5hSD4AWSUC+TFtP5nwTgjA9IkL9CUto62zfEZhNtEBAZwyD X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Describe the Universal Bandwidth Compression (UBWC) configuration for the Milos SoC. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/soc/qcom/ubwc_config.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 15d373bff231..790e67c7db3e 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -16,6 +16,17 @@ static const struct qcom_ubwc_cfg_data no_ubwc_data =3D { /* no UBWC, no HBB */ }; =20 +static const struct qcom_ubwc_cfg_data milos_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 14 for LP_DDR4 */ + .highest_bank_bit =3D 15, + .macrotile_mode =3D true, +}; + static const struct qcom_ubwc_cfg_data msm8937_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_1_0, @@ -223,6 +234,7 @@ static const struct of_device_id qcom_ubwc_configs[] __= maybe_unused =3D { { .compatible =3D "qcom,apq8026", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,apq8074", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,apq8096", .data =3D &msm8998_data }, + { .compatible =3D "qcom,milos", .data =3D &milos_data }, { .compatible =3D "qcom,msm8226", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,msm8916", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,msm8917", .data =3D &no_ubwc_data }, --=20 2.52.0 From nobody Mon Feb 9 09:00:43 2026 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 926002BDC34 for ; Fri, 19 Dec 2025 16:41:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766162487; cv=none; b=OWETCR57ntvy7+Hdrq6vVUPLv7LDaTL3RUnIc8PxrLzwVYbIfIPZPUvxWMDVsPnAMP9VCbAorL0WrYm6yjI8S2I8QzCMywe1ucvQUUO83b6A+6e8zpFdsiQlonBfQkDmm5XNoTXd7Kv9uMDJRE+OXHeTgMeQr6XIyhNPw5P2f5Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766162487; c=relaxed/simple; bh=ohNmR27RG7BPFcETLws/RzDvloxNbzu49qmgmsyHzbg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rr551NpAqggqvNbyMsNc58gXm4ZHtwA1fJsM0ejpMMbKj91mB6oSd8+YFHamqQi+TtWYPQH1PLSv5naNQq66XEUCRNBAIHK0QwaXbGuPanjNoDvlrgHA+t5vJLLhBgblXPT7/Vl9Ct7VbnSoAxwzlnuKApoAmt4CIsoy/SyTVaw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=G3O+x61n; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="G3O+x61n" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-64175dfc338so3837520a12.0 for ; Fri, 19 Dec 2025 08:41:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1766162480; x=1766767280; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=uWMS63VZAWh+LwVHiFL3RZByyF+lbmglu9thz5C4XBk=; b=G3O+x61nJGQ2v9gxlW9DoKQWs7FlDsR7e+iYSWtrvNdmW3VOwum19S21HI7t7JSjSx N7pjkhfoO3dzCGING/WbFXZiPxc8fPpetibizAnOBeO/Llk1eKLD8irIq7uttHfle9/k Pu6kXgj8HLeQZDAW7b5yXXllT9hofWQImtONCCBhvNUj8LGi5R82DKmT4toJcbusaxLd IM80nrE8iSK6yLBYeJqX/0nCmJKQ23vIP2RyIN3KClbRWrl+w6eiLBnEYgX4zWYgLdQf hYzW0r3Fa7gdY9GxoY6DuyDAWhU1skLPaJQBnSVBIjqHEs+DyY8bUgeD0/kHCfs3Ltil /HtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766162480; x=1766767280; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=uWMS63VZAWh+LwVHiFL3RZByyF+lbmglu9thz5C4XBk=; b=o/3OFegB9aCIu06yl0XgCGVelQnUX7wDizD/J0Td9BmLxhsKaXrDRoxX3WW4IFTV/e X/4cu/ulJwaQfKjLLU1oEDhJdGfu/O8NRP8pi+FT7NDsPq/rgxQGzoNOpP33HxMA+RQh OmqCyNlhaXfcfj+isu4XmXiDPWQvIr4YdS7Uhq2IItu/S66F8uxv/ORVgPmZdxaQpjcP +ggU4YUka2MEPvmf9879PgL5pZPxh8+7u+bquGSNzcLByODCx4zWaWFgRzNx3Ge3RpMs y4a9EHT9q6GyM94NxL4hq4AErQeEZidyXGSAK1AwymeZclRHFraN4U4lLUTxwQsC20VB 1RqA== X-Forwarded-Encrypted: i=1; AJvYcCWkdktRFLuWv21ufOUXcGwLkgtcX+ku7v//tLRczZn7my9OJrvmCvZXe13drgxpjoxAK5zEwW/2m93PdWc=@vger.kernel.org X-Gm-Message-State: AOJu0YzwuS9SeHYGQ8zcYDBg9JFVtuddJI+IXxYqCh+1sJUsEcBlStuT UYqkteaX6dyt+oYYg25DcQp6fQpFsq3dVCZ2hHsF13MFQbsEUt71SYAE1d+ieHEJdow= X-Gm-Gg: AY/fxX4kf8O2hpOKXiTVlLApkh0qPTC5bv2CYJB5BfCZbQd/F9gnc/Xs7GX6p2RbSY0 9JBVW7U+XA5C+UCoa1TN+J62NbYdNOTKY7XevZCiGTe2FaOd4aEwI8A39gYleHc5xXjzCbLP+gI QvsnNlvjEvBYEmvoJrJ6wPMxE5QWHu6tgf4kH/Z89+LY1vBjeSfmjFXZTe952M7F8k6jriGYKnZ nghAV62kdkKB2S9rTMOsloI/lgxz0o/cZspMbwWYO9ucp7DXbAOvdA8JpCXI8yRSTRdqNWvp5Ns S3TaUzSctNfmbC48XzzHSDUHS8u10/a8cT5ioXK31SLNOXbiLQ/LMYOMBec9ps+H+GzLXP8UMrF p0L1TE+vxe4917Dqd99aZhLw7F67dHi/cgMWZzuRL8XKj1gdzRPVoQHLEnC7rYI0q71XrrqaYXB iR0ste8VFvbyfqhiNOSxVAhAu3p5Sf4Va2DrIKEfwcQf7pz7EidscSYL7/EcA34Ww75T9pzRaNE KnOk84taR+GVs3prU3Rm9EtDWNxKG20mcs= X-Google-Smtp-Source: AGHT+IFeBLx34o/uuAUMdH45ClT+LNyEz+ShlvD87iHmO/mzLZ8v0c7+jV3dTjNrwelR4FlFcBNZ7w== X-Received: by 2002:a17:906:fd81:b0:b77:18a0:3c8b with SMTP id a640c23a62f3a-b8036f0a48bmr315593566b.1.1766162480371; Fri, 19 Dec 2025 08:41:20 -0800 (PST) Received: from [192.168.178.182] (2001-1c00-3b89-c600-71a4-084f-6409-1447.cable.dynamic.v6.ziggo.nl. [2001:1c00:3b89:c600:71a4:84f:6409:1447]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8037f4ef1fsm270073866b.64.2025.12.19.08.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 08:41:19 -0800 (PST) From: Luca Weiss Date: Fri, 19 Dec 2025 17:41:08 +0100 Subject: [PATCH RFC 2/6] drm/msm/dsi: add support for DSI-PHY on Milos Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-milos-mdss-v1-2-4537a916bdf9@fairphone.com> References: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> In-Reply-To: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766162477; l=2966; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=ohNmR27RG7BPFcETLws/RzDvloxNbzu49qmgmsyHzbg=; b=u8kMZZ5XCdBAQqVc75EEYESeLgtSwulD/FZN1Nv9WKgIfHtzElwwgfCg8ePkE2aG/YwOFsu88 +7CWnoGudYNBpfHSe96RbCE5NSbFfaFoIDAKT4j6P4V8E4RsRpxpuIQ X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add DSI PHY support for the Milos platform. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 24 ++++++++++++++++++++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index 4ea681130dba..0ac5029d3eb4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -571,6 +571,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_5nm_8350_cfgs }, { .compatible =3D "qcom,sm8450-dsi-phy-5nm", .data =3D &dsi_phy_5nm_8450_cfgs }, + { .compatible =3D "qcom,milos-dsi-phy-4nm", + .data =3D &dsi_phy_4nm_milos_cfgs }, { .compatible =3D "qcom,sm8550-dsi-phy-4nm", .data =3D &dsi_phy_4nm_8550_cfgs }, { .compatible =3D "qcom,sm8650-dsi-phy-4nm", diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index 3cbf08231492..011bee593199 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -61,6 +61,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_milos_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index c5e1d2016bcc..6ca45e5c2cc0 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -1436,6 +1436,30 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cf= gs =3D { .quirks =3D DSI_PHY_7NM_QUIRK_V5_2, }; =20 +const struct msm_dsi_phy_cfg dsi_phy_4nm_milos_cfgs =3D { + .has_phy_lane =3D true, + .regulator_data =3D dsi_phy_7nm_98000uA_regulators, + .num_regulators =3D ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), + .ops =3D { + .enable =3D dsi_7nm_phy_enable, + .disable =3D dsi_7nm_phy_disable, + .pll_init =3D dsi_pll_7nm_init, + .save_pll_state =3D dsi_7nm_pll_save_state, + .restore_pll_state =3D dsi_7nm_pll_restore_state, + .set_continuous_clock =3D dsi_7nm_set_continuous_clock, + }, + // FIXME not sure about these rate values + .min_pll_rate =3D 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate =3D 5000000000UL, +#else + .max_pll_rate =3D ULONG_MAX, +#endif + .io_start =3D { 0xae95000 }, + .num_dsi_phy =3D 1, + .quirks =3D DSI_PHY_7NM_QUIRK_V5_2, +}; + const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs =3D { .has_phy_lane =3D true, .regulator_data =3D dsi_phy_7nm_98400uA_regulators, --=20 2.52.0 From nobody Mon Feb 9 09:00:43 2026 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E232A3469E3 for ; Fri, 19 Dec 2025 16:41:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766162491; cv=none; b=KBe4HziMLNKjjQ8jn8GicIBlZC4TpaOj8CBaGumxj/awDTPgJNobV8fURCtGj0X3G04Y/OnxM/T5FdP2hZkx3nJZHNNoea1K32xNq1FYONq4XPBiG3K5jyutNx04v1kIHhgAX8NDyl79NiWmWCUr7H9y12Uor5ZXZlmze+HSfjE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766162491; c=relaxed/simple; bh=tR/wcXsSRSmMC9AuE79DxiyAbWm/TId46OBOFeIFTQM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tLPIFv14SRHLfhjKTQojBdjZXoO9lqUgdxeeCTgmy5XnQqO8cZN/4EzxtlTaHRHLDMy/55AJx4ylhJ0eRrY0O6p1Fg9bqH2xeawFwcDv726wzk2xbZLiw8llfLNLdFLRfj64EmZiy8XmaBFRLAsSQXM89oVgnmDlf/Api0D7haE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=ZbT3nkv1; arc=none smtp.client-ip=209.85.218.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="ZbT3nkv1" Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-b73a9592fb8so405439366b.1 for ; Fri, 19 Dec 2025 08:41:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1766162481; x=1766767281; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=O0HzFaVjwMvZjTaaJOfxP1smFpIabOwZw0I+saghW9I=; b=ZbT3nkv11u2Olqq0mGExyEXwT21iJNdqLuoAgf8qVymKqesz9+tLdTWLtVcjCK9nYb 1mLsf06DrDC/koQPQ4xV9PvLznqh7wQRJ4Qhc5DqVhxa8RTJY3MtKVX1EuKQg//A+p0D f21ro9MHDvIRG4CWCX6YFmeyZxw8n1vfeJhXp8//B1wkZuYDp/5nq4pyfn7WUlWCga+I HxbYTAWxW8wAvxK8BUvAgETJsx/HrAT1xqChq/JiFygAaXQZ/stX1yXcCX9Xr/CC6T2h PBiHQiJsNQVHMOa6dgNUJcHPjtGcNzAh+EAhpcd+jkGdzLH4D00MJ/v822mxl5fHlMt4 0xYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766162481; x=1766767281; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=O0HzFaVjwMvZjTaaJOfxP1smFpIabOwZw0I+saghW9I=; b=oo8k+qv2xxdjLw0Kq8aDAVnM0ME9W3cjaF/ywlUoMZ1EVNueu0DnPaMBTEr8uo/uHj DCAIjNigBUuMRetCyyX9HnuXU5yHw8+NBDkWxbP6MjRhW20LQ3FldCXl8GxxJHaazVqS wtZJGUlMweWre2ITb1CqcZvibqeh600Jq4ZBfAcyXb5k2ki38AZZQsUkPTYi9niBBWii 0RbOX4endwnIQVq5HenOVNcBIQMw5OdskmaJ9GUuK66AVXuPXb1JbY0KEWT7DFzuwFOa md612siN+u8dj8I+q/HNtvALzsIMgNbxcU5GUzdiWWdtPR/2mhF7tWldmlsUirNrOrQZ I8sw== X-Forwarded-Encrypted: i=1; AJvYcCXgZATjXOP4ATAo6KrooFjfpmM8rFWyhsMFnyLV+hRSa4vyiHtVknySOLuPDMlXQC54IldGQB+XmYzLNFg=@vger.kernel.org X-Gm-Message-State: AOJu0Yybb3n1yBBauS8Q8moPSFjVV1PrmM8/LfHARLDFRWkldQUXMf4g Taop0wB0gmDQhcqEf9+VsixtCjVB2u1K5o08lOZ6RTwcwCQTcR8TieTChXetHQeDmck= X-Gm-Gg: AY/fxX40Sgv1CILFb4jVBiHwZ/o5ZsrmM7i1ihVej1aQraAi4Y0vSOZ0JbNwf3843hN cVz80vaEEBAq3f/F8KijE8Yx38y2AqD4apOMKPPUKCYK0+fYVERKR+ogMnXqWNqh+k9MED+r7Oc w5ZrCJR1PX5I4DtRW53Xo4wRKSIjp4ktALqwqI4WWn2YrIXFX9nAh0kieCOOT0mwRvRDX5zyy4I wrbVcSmTHSlNljvSbwjOhfoVei4yHg3ITBeqPgBWgKyj0T+/2u33DTPKgRPXkdRTdnvgwa8rBYC y9Q6xXmcyHCqvGkM4nEDXqeE39GBXUJ2WIqC9LcOCNEtMGvrednSQjiFH98GjUt1lEE+6yi3UO6 gFD8TeojGMz8F2WLfeqmPAwSn4X/Fts/s84ctPJWoMaVEsXHJXsHfTmU2Wn9GUR/vf/lkSg24Bv M8rcROTNx2BIeFhVAe4lyEH0n/s5y7TUyQwBuyi+Qi7inJM+wf57YZcMRUsyluUOINQaLgJdZem NelkY+DU3/CaM7OsqEiJM8yCDGgIPNQNsw= X-Google-Smtp-Source: AGHT+IHWxjRwTQlRafEaSyCGoH5228OD0CyKH8COwa1Vo5glIpgVUvP069JTSjZ+iajU/yCWxg/e+Q== X-Received: by 2002:a17:907:7e9f:b0:b80:16:850b with SMTP id a640c23a62f3a-b803542da8cmr453536766b.0.1766162481221; Fri, 19 Dec 2025 08:41:21 -0800 (PST) Received: from [192.168.178.182] (2001-1c00-3b89-c600-71a4-084f-6409-1447.cable.dynamic.v6.ziggo.nl. [2001:1c00:3b89:c600:71a4:84f:6409:1447]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8037f4ef1fsm270073866b.64.2025.12.19.08.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 08:41:20 -0800 (PST) From: Luca Weiss Date: Fri, 19 Dec 2025 17:41:09 +0100 Subject: [PATCH RFC 3/6] drm/msm: mdss: Add Milos support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-milos-mdss-v1-3-4537a916bdf9@fairphone.com> References: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> In-Reply-To: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766162477; l=1078; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=tR/wcXsSRSmMC9AuE79DxiyAbWm/TId46OBOFeIFTQM=; b=C/2rJj/g80rHDRnltiMZEOcEAploGDh4/PX6r35eRIe0loQrjOFjPL/YrpppAgkRC0l/xHDie gbCJGLNqIaUDU0TzwF33KUnK8+cnJflwNKYcC2qUTOOC7gLTx5KaxHG X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add support for MDSS on Milos. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/msm_mdss.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 2d0e3e784c04..aa63c079d730 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -535,6 +535,10 @@ static void mdss_remove(struct platform_device *pdev) msm_mdss_destroy(mdss); } =20 +static const struct msm_mdss_data data_14k =3D { + .reg_bus_bw =3D 14000, +}; + static const struct msm_mdss_data data_57k =3D { .reg_bus_bw =3D 57000, }; @@ -553,6 +557,7 @@ static const struct msm_mdss_data data_153k6 =3D { =20 static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,mdss", .data =3D &data_153k6 }, + { .compatible =3D "qcom,milos-mdss", .data =3D &data_14k }, { .compatible =3D "qcom,msm8998-mdss", .data =3D &data_76k8 }, { .compatible =3D "qcom,qcm2290-mdss", .data =3D &data_76k8 }, { .compatible =3D "qcom,sa8775p-mdss", .data =3D &data_74k }, --=20 2.52.0 From nobody Mon Feb 9 09:00:43 2026 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9011034A3D9 for ; Fri, 19 Dec 2025 16:41:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766162496; cv=none; b=PWIF+6kkh7Pj7HY/PYJReJWVp85ZFrXwCmEY8+ZQZSVmj1eayJm/gs3Ka88INYwXSJIjMg3yo3Zbf22N+tMz2hhRqncKi0YYEvMjIoowiu7U/C4A2pCf0YHumLDz8MPaiOucbP80WISlfIenpTHkOLidfijU+o7EK0k2jkEkg4c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766162496; c=relaxed/simple; bh=PnUAb7+xa3V6lDy9C/8zlniMpYa539gIMtTZjegPYas=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Hm9eKfXymzz1pDcAMYeAd8Lt9Terb31LyBS3V7SeL+EjhniNof0YT+qSAIPgeDDFUbe7FRjMf81R+oDt9vn6JCi93XrwkuTnAAdDDkLkiUMhfIly+mBLIpm8Urjz3s3J9HkZVqnMJthybbCzCk+IjlWBxWXAHLUOtjrXNuCHbDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=l/aWzOfd; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="l/aWzOfd" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-b79d6a70fc8so337218266b.0 for ; Fri, 19 Dec 2025 08:41:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1766162482; x=1766767282; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=LnXlKVol+Ygu7DXj97MTCvj4fTNWQFpTYWEPQu/ZwkI=; b=l/aWzOfdysKmaCuYKxzsGU6mHwHrfTaI6AN0XQDnGsmHropn62Uv0skEP1z0L2c0FQ HesoLBMEajMZybrKYyr8uhBTcOVZrT8ygTaw/0CQ5jiMydqawHwn51uVe3JdZCUk5hhw +zCX1DAX3JsG+gILi6O4T72qA851PiXYjYuKGsYJm5ZsyVVGJ7W2P36cZVgprjk10qOR IwXc7jRkbRZbiFFNk+z7QLThgx2O9uI3Ws4gRhRh4HCQWMSNrsbAHkGT4kjK3y/ew2mm +vtWi3eDSwv0srWn3yml0lyXIrIqDG4vM5OYZVup7uYxOmtOJLPowI5pJWSeedlNfx/0 kkkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766162482; x=1766767282; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=LnXlKVol+Ygu7DXj97MTCvj4fTNWQFpTYWEPQu/ZwkI=; b=hGMV+bnod4ZRGNLHKOImgySiux3U1uMbejFiYGeRSWKuaqndqHRmYWx+s0nQWXxZC1 44Vm3r9wlOLIkqR0gg8OOq9cE3pBlR5VruxuRt4DBQr9NhCWntZuTB4TpOI9NhYN2Rue lcIo9uLFs9OZgMs/wtMxNbwwTcmEVCcrVGRorWrPWhsKIKiAEARAI8fSpI+IQCb6RzaU SPL/q2o30QMcNejxkfFPDzez9eo3NzFINGJerGvry4sDdN0YiHCr9Jined3/7J1IiI+l K1RKUyphLYtsMhVdEzkFAfJk77uj9uuku9UcgFsfdzSHcY6TtGX4hImsHQqcepWqqFMI L2bw== X-Forwarded-Encrypted: i=1; AJvYcCXEk26Y/jHi+qEv9kPkkJPICReK1gDacj6kZm3AmXWyw4hCdboiUH1/7+9oFwh0g7gtyxcPJRPu55Ik5eg=@vger.kernel.org X-Gm-Message-State: AOJu0YzXmLzGgnp22LRbPs6S7qW6Iq2WA+T97WJAq9zgndNVmShZjEXt yu+s4ekvWe4EXirR6B2GRJfGIK4Egt44GnzmAkrJJRYJ9amqePwFyAtaFqgF2Npp7Fc= X-Gm-Gg: AY/fxX5MHGCL0TKog3eqTGPOZdm2rsg/lLUcQdelRY9K41kCNZ0NzoknGDDqAtp4hFm XTSeo8vQFVzhuCHRWJGWKR+8vyWtZISaMkGnE+pbPOYUKwNAWTkAchycb6cGtL0AIkcEG4e7cy3 wWWyhGDSWHAvz/TXNN+TuKLQQA+OOcP5Sg3lKCv6oOw4MBzhiN/EQjnLPrriaEY5Y01UAE70zkc aDk6cielVPuXUcZ9durQVhzM9VCOuJouGpEVizh5+VMPu5WAUGH7fqB/YtkYt+lskKtyPhpsPPL Mj2ek5mNmEcMLaxfYf6WZs6YKW9zOwsTx6zWdj0+aP0UMRsV1gG7jfBIgcZaUzzO+rcM0V2G9U9 fEIGYz2//YNkv8vUbIcI8B8VYEzCPEKMcETn/ZEHORurw64fHLlchsVOrHuhs2BEyqa957iBWL7 IOLLvyOa3AcmQ1zTjUv8xszufxi9UZ4ngD3n8TSLhOB+8/GsBapOM+NsuyYbD3S+805xkA0/by9 1x+teLJztTATF23t+bPhY1ntBzYDycl7MM= X-Google-Smtp-Source: AGHT+IH1zB8ehYPh2ylwaH0SX9QWUv12Lrt9njJSas6gh9ZTueO/V1wIp/cPy5mYFDqEQmQkhEpb7w== X-Received: by 2002:a17:907:1c0a:b0:b7a:1bdc:aab8 with SMTP id a640c23a62f3a-b80372301femr341455366b.65.1766162482072; Fri, 19 Dec 2025 08:41:22 -0800 (PST) Received: from [192.168.178.182] (2001-1c00-3b89-c600-71a4-084f-6409-1447.cable.dynamic.v6.ziggo.nl. [2001:1c00:3b89:c600:71a4:84f:6409:1447]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8037f4ef1fsm270073866b.64.2025.12.19.08.41.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 08:41:21 -0800 (PST) From: Luca Weiss Date: Fri, 19 Dec 2025 17:41:10 +0100 Subject: [PATCH RFC 4/6] drm/msm/dpu: Add Milos support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-milos-mdss-v1-4-4537a916bdf9@fairphone.com> References: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> In-Reply-To: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766162477; l=12066; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=PnUAb7+xa3V6lDy9C/8zlniMpYa539gIMtTZjegPYas=; b=yeAXi07NZfudvTq40/ousXx7KxI5TgCJgDa5arCQW9mNmdqFARYNFZKHcACxK7KvPxxgtl7Fe Cb8SDKa0Z8fAW9IkDiXiL9zukGo2G4+HO6gnpxxth+4C6bEaHRvkKZ6 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add definitions for the display hardware used on the Qualcomm Milos platform. Signed-off-by: Luca Weiss --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h | 284 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 22 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 308 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h new file mode 100644 index 000000000000..75deec923897 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h @@ -0,0 +1,284 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2025, Luca Weiss + */ + +#ifndef _DPU_10_2_MILOS_H +#define _DPU_10_2_MILOS_H + +static const struct dpu_caps milos_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, // OK + .max_mixer_blendstages =3D 0x7, // OK + .has_src_split =3D true, // OK + .has_dim_layer =3D true, // OK + .has_idle_pc =3D true, // OK? + .has_3d_merge =3D true, // OK? + .max_linewidth =3D 8192, // OK + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, // OK +}; + +static const struct dpu_mdp_cfg milos_mdp =3D { + .name =3D "top_0", + .base =3D 0, .len =3D 0x494, // TODO? maybe qcom,sde-len =3D <0x488>; + .clk_ctrls =3D { + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, // OK + }, +}; + +static const struct dpu_ctl_cfg milos_ctl[] =3D { // number of ctl is okay= , base probably also + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), // FIXME? + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, +}; + +static const struct dpu_sspp_cfg milos_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, // OK + .base =3D 0x4000, .len =3D 0x344, // OK + .features =3D VIG_SDM845_MASK_SDMA, // TODO? + .sblk =3D &dpu_vig_sblk_qseed3_3_3, // TODO? + .xin_id =3D 0, // OK + .type =3D SSPP_TYPE_VIG, // OK + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, // FIXME name? + .base =3D 0x24000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, // OK + .type =3D SSPP_TYPE_DMA, // OK + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, // OK + .type =3D SSPP_TYPE_DMA, // OK + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0x28000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, // OK + .type =3D SSPP_TYPE_DMA, // OK + }, +}; + +static const struct dpu_lm_cfg milos_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, // OK + .base =3D 0x44000, .len =3D 0x400,// OK + .features =3D MIXER_MSM8998_MASK, // TODO + .sblk =3D &sdm845_lm_sblk, // OK + .pingpong =3D PINGPONG_0, // TODO + .dspp =3D DSPP_0, // TODO + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sdm845_lm_sblk, // OK + .lm_pair =3D LM_3, // OK + .pingpong =3D PINGPONG_2, + //.dspp =3D DSPP_2, // FIXME? + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x47000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sdm845_lm_sblk, // OK + .lm_pair =3D LM_2, // OK + .pingpong =3D PINGPONG_3, + //.dspp =3D DSPP_3, // FIXME? + }, +}; + +static const struct dpu_dspp_cfg milos_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, // OK + .base =3D 0x54000, .len =3D 0x1800, // OK + .sblk =3D &sdm845_dspp_sblk, // TODO + }, +}; + +static const struct dpu_pingpong_cfg milos_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, // OK + .base =3D 0x69000, .len =3D 0, // OK + .sblk =3D &sc7280_pp_sblk, // OK + .merge_3d =3D MERGE_3D_0, // OK + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), // TODO + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, // TODO + .base =3D 0x6b000, .len =3D 0, // OK + .sblk =3D &sc7280_pp_sblk, // OK + .merge_3d =3D MERGE_3D_1, // OK + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x6c000, .len =3D 0, // OK + .sblk =3D &sc7280_pp_sblk, // OK + .merge_3d =3D MERGE_3D_1, // OK + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, + .base =3D 0x66000, .len =3D 0, // OK + .sblk =3D &sc7280_pp_sblk, // OK + }, +}; + +static const struct dpu_merge_3d_cfg milos_merge_3d[] =3D { + { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, // TODO + .base =3D 0x4f000, .len =3D 0x8, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg milos_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, // OK + .base =3D 0x80000, .len =3D 0x6, // OK + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), // TODO + .sblk =3D &dsc_sblk_0, // TODO + }, { + .name =3D "dce_0_1", .id =3D DSC_1, // OK + .base =3D 0x80000, .len =3D 0x6, // OK + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), // TODO + .sblk =3D &dsc_sblk_1, // TODO + }, +}; + +static const struct dpu_wb_cfg milos_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, // TODO + .base =3D 0x65000, .len =3D 0x2c8, // OK + .features =3D WB_SDM845_MASK, // TODO + .format_list =3D wb2_formats_rgb_yuv, // TODO + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), // TODO + .xin_id =3D 6, // OK + .vbif_idx =3D VBIF_RT, // TODO + .maxlinewidth =3D 4096, // OK + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), // TODO + }, +}; + +static const struct dpu_cwb_cfg milos_cwb[] =3D { + { + .name =3D "cwb_0", .id =3D CWB_0, + .base =3D 0x66200, .len =3D 0x8, + }, +}; + +static const struct dpu_intf_cfg milos_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, // OK + .base =3D 0x34000, .len =3D 0x280, // OK size=3D0x300? + .type =3D INTF_DP, // OK + .controller_id =3D MSM_DP_CONTROLLER_0, // OK? + .prog_fetch_lines_worst_case =3D 24, // TODO + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), // TODO + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), // TODO + }, { + .name =3D "intf_1", .id =3D INTF_1, // OK + .base =3D 0x35000, .len =3D 0x300, // OK size=3D0x300? + .type =3D INTF_DSI, // OK + .controller_id =3D MSM_DSI_CONTROLLER_0, // OK? + .prog_fetch_lines_worst_case =3D 24, // TODO + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), // TODO + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), // TODO + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), // TODO + }, { + .name =3D "intf_3", .id =3D INTF_3, // TODO? + .base =3D 0x37000, .len =3D 0x280, // OK size=3D0x300? + .type =3D INTF_DP, // OK + .controller_id =3D MSM_DP_CONTROLLER_1, // FIXME, only one DP controller? + .prog_fetch_lines_worst_case =3D 24, // TODO + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), // TODO + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), // TODO + }, +}; + +static const struct dpu_perf_cfg milos_perf_data =3D { + .max_bw_low =3D 7100000, + .max_bw_high =3D 9800000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 1600000, + .min_prefill_lines =3D 35, // TODO + /* FIXME: lut tables */ + .danger_lut_tbl =3D {0x3ffff, 0x3ffff, 0x0}, // TODO + .safe_lut_tbl =3D {0xfe00, 0xfe00, 0xffff}, // TODO + .qos_lut_tbl =3D { // TODO + {.nentry =3D ARRAY_SIZE(sc7180_qos_linear), + .entries =3D sc7180_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { // TODO + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, // TODO + .bw_inefficiency_factor =3D 120, // TODO +}; + +static const struct dpu_mdss_version milos_mdss_ver =3D { + .core_major_ver =3D 10, + .core_minor_ver =3D 2, +}; + +const struct dpu_mdss_cfg dpu_milos_cfg =3D { + .mdss_ver =3D &milos_mdss_ver, + .caps =3D &milos_dpu_caps, + .mdp =3D &milos_mdp, + .cdm =3D &dpu_cdm_5_x, + .ctl_count =3D ARRAY_SIZE(milos_ctl), + .ctl =3D milos_ctl, + .sspp_count =3D ARRAY_SIZE(milos_sspp), + .sspp =3D milos_sspp, + .mixer_count =3D ARRAY_SIZE(milos_lm), + .mixer =3D milos_lm, + .dspp_count =3D ARRAY_SIZE(milos_dspp), + .dspp =3D milos_dspp, + .pingpong_count =3D ARRAY_SIZE(milos_pp), + .pingpong =3D milos_pp, + .dsc_count =3D ARRAY_SIZE(milos_dsc), + .dsc =3D milos_dsc, + .merge_3d_count =3D ARRAY_SIZE(milos_merge_3d), + .merge_3d =3D milos_merge_3d, + .wb_count =3D ARRAY_SIZE(milos_wb), + .wb =3D milos_wb, + .cwb_count =3D ARRAY_SIZE(milos_cwb), + .cwb =3D milos_cwb, + .intf_count =3D ARRAY_SIZE(milos_intf), + .intf =3D milos_intf, + .vbif_count =3D ARRAY_SIZE(milos_vbif), + .vbif =3D milos_vbif, + .perf =3D &milos_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 9f8d1bba9139..4d5b57d6295f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -555,6 +555,26 @@ static const struct dpu_vbif_cfg sdm845_vbif[] =3D { }, }; =20 +static const struct dpu_vbif_cfg milos_vbif[] =3D { + { + .name =3D "vbif_rt", .id =3D VBIF_RT, // OK + .base =3D 0, .len =3D 0x1074, // OK + .features =3D BIT(DPU_VBIF_QOS_REMAP), // TODO + .xin_halt_timeout =3D 0x4000, // TODO + .qos_rp_remap_size =3D 0x40, // TODO + .qos_rt_tbl =3D { // TODO + .npriority_lvl =3D ARRAY_SIZE(sm8650_rt_pri_lvl), + .priority_lvl =3D sm8650_rt_pri_lvl, + }, + .qos_nrt_tbl =3D { // TODO + .npriority_lvl =3D ARRAY_SIZE(sdm845_nrt_pri_lvl), + .priority_lvl =3D sdm845_nrt_pri_lvl, + }, + .memtype_count =3D 16, // OK + .memtype =3D {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, // OK? + }, +}; + static const struct dpu_vbif_cfg sm8550_vbif[] =3D { { .name =3D "vbif_rt", .id =3D VBIF_RT, @@ -725,4 +745,6 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_9_2_x1e80100.h" =20 #include "catalog/dpu_10_0_sm8650.h" +#include "catalog/dpu_10_2_milos.h" + #include "catalog/dpu_12_0_sm8750.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index f0768f54e9b3..1f6b14f1c4d6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -749,6 +749,7 @@ struct dpu_mdss_cfg { const struct dpu_format_extended *vig_formats; }; =20 +extern const struct dpu_mdss_cfg dpu_milos_cfg; extern const struct dpu_mdss_cfg dpu_msm8917_cfg; extern const struct dpu_mdss_cfg dpu_msm8937_cfg; extern const struct dpu_mdss_cfg dpu_msm8953_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 4e5a8ecd31f7..7afd7dc7a0b4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1505,6 +1505,7 @@ static const struct dev_pm_ops dpu_pm_ops =3D { }; =20 static const struct of_device_id dpu_dt_match[] =3D { + { .compatible =3D "qcom,milos-dpu", .data =3D &dpu_milos_cfg, }, { .compatible =3D "qcom,msm8917-mdp5", .data =3D &dpu_msm8917_cfg, }, { .compatible =3D "qcom,msm8937-mdp5", .data =3D &dpu_msm8937_cfg, }, { .compatible =3D "qcom,msm8953-mdp5", .data =3D &dpu_msm8953_cfg, }, --=20 2.52.0 From nobody Mon Feb 9 09:00:43 2026 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EF5C33D4F3 for ; Fri, 19 Dec 2025 16:41:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766162491; cv=none; b=B55u4An3FWVtFiSA1G14rZe1zm9A3wjQ+7Lrv3kqdvLMBaq27SOiqQDGg/2vW6dPU8/8jeAgCgPWJsLPgG3ccrmeznKnxq7rOkb45/iO7T5r7j+TSpHe+4kEOtJPUL10WN6407+N24P8gLNhXmvHwSkVx76lvbplxv8LpiSH/d8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766162491; c=relaxed/simple; bh=ZPY/+FNr1/I/jCjPIrjQ2ntydK3ydgHgE/NHLtUlLqI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hyUYX9VJ6X/uc+jXEEuYd8Cy4qpEcVXeZ309BtjBPNUnNrV5PHDnJXjj+oOoLJH8CeloMHi8La1bMyidgzfm7Uq2yW2vEYLwsl+85eK5TdGs3bCmqKGwtm1L1+XcV6W4zd9jqpG7YbKWzeJur7vsaIq/gsdyh7vtke6/5vp/s4o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=zZVgpvB/; arc=none smtp.client-ip=209.85.218.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="zZVgpvB/" Received: by mail-ej1-f52.google.com with SMTP id a640c23a62f3a-b79f8f7ea43so451052666b.2 for ; Fri, 19 Dec 2025 08:41:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1766162483; x=1766767283; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=BUxnJEEvA236F8NBMU+pi14SjYgYMC3mWtbkAiJbgJA=; b=zZVgpvB/it2R6xjifk7VjCSX74bp6+kAD+pwx2yAErZetdTNmQyLkWWfO+xV8kKJkd tO2xoQ/RGsGp2z1apCtfTPK8mcvai+e5WI8XT1UNrhFoIDDnRbWyp0DDS3oJGPd0pIAy agEdxXM7nRGF70uOyD2MaYW4vsoynxdKw/1+l1EOAb9oEqw4Im5HGcefFHiDw7Rx/nwa UBUPNaWm9zGCzv/1IqUhJGn/udp1Kl8rYBCrJ3Esof1r5hmgDpwgKIyerihC2n6aUIis hGF4KCl2msjqrtgNOBDLmUOA1Kq935OsjO4moualmKpM7UbFZutEFSvSdu69Ann7uScm soTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766162483; x=1766767283; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=BUxnJEEvA236F8NBMU+pi14SjYgYMC3mWtbkAiJbgJA=; b=dEIl+kroXYuBdIl1S2cIB82+m1s8S4RpcS68EDbalAOF3dMV6WlI54jeQwoQgxIIMa fQ+mJA7xFS9SWvdgTNzP6NoKwydpKwAF7IVO0epe6OybmaoQz1VlpJuzyHHipEdGfwl5 wZgxnwW9d/pJb4yf81Yd3mwD5LdkboAC1Vs07sg4uyp3VFK048Qh8B+bQx5qxjvgTl/D J0n2IWV3FZIkvJNQHvEqgZFJUkapsyEYVPIGTAA+xlFPzwLH+XO3362QX31xqVopr8Kt YK5O1GxR8NtYGEN3ppfIN6qiC+ipsIbNUFdd25TrcjTaqes+XeGTSTU8PwGFN5O2QK/L FKRA== X-Forwarded-Encrypted: i=1; AJvYcCX0HZOK4cTRmsA4xV8bUzHnMAXVkbMwJY4MuXgT7NcD3ECUuwh4K2WVNOtNE+igg4uO+OhdohSUz7ywqvE=@vger.kernel.org X-Gm-Message-State: AOJu0YzbWm5WVIW09gAITvlR9xzrWdP5A9ExMcFloFDuUq1vK/vNMuHz UQXJcuQq9bN4XM4Q7ReNuhPjeMzwmwdHhSi1uqSpmgQ038MsTL63OHsPXuLOD3MXHL8= X-Gm-Gg: AY/fxX5lQKTfEMLrh6LtFSvB5Nja00gBTCZL4C+8gWCvxh7NMDsvuFR+Qg4B2mjK2RN LI05ipJc1L9zkuHLbEz/epIMIFMMtJcYW7yYdACKZPdAEZ9h9921YN3mhXkmK4WkcZZh6TknwWu pb3vMxhbYVOH3kjPWX6MbZUwm1hQ6518/ARV2AWV88V3ZCG/Ytw7dRMAhGmPHF4OPtkHtcwWY/D jkhJ0skQnX6J5oUN0FFfzic7/xzYPXjddsLZFUbk+2qkJfPOZ6SAzlK6Nq5nPIoiTWp3LoGLsS0 pyaqTUuepoqIr7UIXFGhVjRLzVNiqkidsI/DaaFJV9aY+719r8KraFZGpWox0/VvwSNApTRmX/n KkOfGKhDWCuswhQD8T1hxnWIHTRZ+2iL1WbiwTN/W6VJLMnv2NWO5G+mwa9dP13A2+mGmi+6hBs hbwC1AYC9bOBb95ALB21cnjrvsm3lR7mg7Za3VXaqkaOYq+DgdPaK8OiM3UoqcCe35Mg0MtQ31/ Zt0Xwllz/RlaizXFEsFME3xuS5qu6u51xt4AeOMlpuRDw== X-Google-Smtp-Source: AGHT+IE7/rDvAirOTWuD+BVN5TbR1N6ti7H+jP3ySf2yYQJ6aR8Hobv4GJ5Cw25G9s0WT629tUqWPQ== X-Received: by 2002:a17:907:6e8d:b0:b7a:1be1:823 with SMTP id a640c23a62f3a-b80371f4980mr307764866b.64.1766162483081; Fri, 19 Dec 2025 08:41:23 -0800 (PST) Received: from [192.168.178.182] (2001-1c00-3b89-c600-71a4-084f-6409-1447.cable.dynamic.v6.ziggo.nl. [2001:1c00:3b89:c600:71a4:84f:6409:1447]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8037f4ef1fsm270073866b.64.2025.12.19.08.41.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 08:41:22 -0800 (PST) From: Luca Weiss Date: Fri, 19 Dec 2025 17:41:11 +0100 Subject: [PATCH RFC 5/6] arm64: dts: qcom: milos: Add MDSS Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-milos-mdss-v1-5-4537a916bdf9@fairphone.com> References: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> In-Reply-To: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766162477; l=6457; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=ZPY/+FNr1/I/jCjPIrjQ2ntydK3ydgHgE/NHLtUlLqI=; b=bTYroNnX9nmEp+PvxNLxIefBtVd4tBPLovBupbfVOdJ8HI0UiqL0WfH/MKEvYwKQ+t8e+eZOC EsYuqD5T1+tB1FhWAdiM4maIun2YecmssvG6Cy1ETDN3K03Ie2h0iZ/ X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/milos.dtsi | 211 ++++++++++++++++++++++++++++++++= +++- 1 file changed, 209 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index 0756cf5fb888..2477f0d97278 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2025, Luca Weiss */ =20 +#include #include #include #include @@ -1821,6 +1822,212 @@ camcc: clock-controller@adb0000 { #power-domain-cells =3D <1>; }; =20 + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,milos-mdss"; + reg =3D <0x0 0x0ae00000 0x0 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects =3D <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + power-domains =3D <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus =3D <&apps_smmu 0x1c00 0x2>; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,milos-dpu"; + reg =3D <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names =3D "mdp", + "vbif"; + + interrupts-extended =3D <&mdss 0>; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-342000000 { + opp-hz =3D /bits/ 64 <342000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-402000000 { + opp-hz =3D /bits/ 64 <402000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-535000000 { + opp-hz =3D /bits/ 64 <535000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + required-opps =3D <&rpmhpd_opp_nom_l1>; + }; + + opp-630000000 { + opp-hz =3D /bits/ 64 <630000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible =3D "qcom,milos-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0 0x0ae94000 0x0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible =3D "qcom,milos-dsi-phy-4nm"; + reg =3D <0x0 0x0ae95000 0x0 0x200>, + <0x0 0x0ae95200 0x0 0x280>, + <0x0 0x0ae95500 0x0 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible =3D "qcom,milos-dispcc"; reg =3D <0x0 0x0af00000 0x0 0x20000>; @@ -1829,8 +2036,8 @@ dispcc: clock-controller@af00000 { <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <0>, /* dsi0_phy_pll_out_byteclk */ - <0>, /* dsi0_phy_pll_out_dsiclk */ + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, /* dp0_phy_pll_link_clk */ <0>; /* dp0_phy_pll_vco_div_clk */ =20 --=20 2.52.0 From nobody Mon Feb 9 09:00:43 2026 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2C5B34844F for ; Fri, 19 Dec 2025 16:41:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766162494; cv=none; b=DpS3kALR0cHLaXrwU2yljM6yyjsWYnpHrLYbWStGcZAXinhMYC6fTH8iKH2GtkuFEryis4vrUTKGm0PpkHE2BZUSWj43oFBZVRfGyMrMRRTWzYK8nPgCgExXHrZIFx0kKnSAGfhSf3jSuQTuKpM7AD+KAtgqSDGmu8UO0ShTedY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766162494; c=relaxed/simple; bh=LbaF66ke8LZxZbzBSqWF+LbtIQHMEYFknVPL8JPpg/I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=u2MqWPhPA3eu3aL1tcs4h9fsCwM/XYBF/4i/GecoSS2oVzQOoSbjMfPLGKW4emKlnjIl99d3k8o7BKnbxxMmMU2DUufiNnOk40782dvAXCMvOMijtHddzydrzqOg1uTcZh0xQ0ifY1xTGZthbrDYRSml0fmhOMHrnsC4eviLSCo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=iR/HRyWy; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="iR/HRyWy" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-b7277324054so346780266b.0 for ; Fri, 19 Dec 2025 08:41:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1766162484; x=1766767284; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=e2Cw2KB1P5Y6mcnQJX0NULNND1p0iocVjya6HA4fgP4=; b=iR/HRyWytBvsluQHGs1uWbZEyhdPClEaoT+6qL2mpen5W8cwT16x/EKBTRCLrVnH/R 0Z6KI0JJjxzMvtzUZwHXX1AeDtT1KNqo7y0d1xOIgrDqZJHGINyrqOIgnDYSj4u/UlRS Lge7gKT4q93y2b+mSRklybGNo0Y+HKvkm4IC3Yiz/aQVJj2cg31QsckiRTtA8QkgBhx8 j+cDWpA0ECla214yE1h4uPUUzOfPsnfC63Fxy1xKDuo/FQKEm5qU65GG6IodRM/PkZEJ AsfCna+CZvjwRbTl5y6repf0fc1rj6pMbHEnSUgbknAj9WTOfDWljTcIOEf+uS3Y35PX 6lNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766162484; x=1766767284; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=e2Cw2KB1P5Y6mcnQJX0NULNND1p0iocVjya6HA4fgP4=; b=rmVZO4L7kNsczdEUng4wMi9quv8rxwlarPUQKvao4xWvzvxqH2k5Fb1H4T6eITivxO QyNXiIwN6tkV/ReORukqbX5A+fSUWrbTpbrVn58rHew59KuGThQEiia6ZaFeZzcpdoIk Z6a52ZScIScDUxeJIqmFhSlmldsl+vxuxTx3Q3JcfAnOpnAXtSo4EhoMiCjdxkGYIQAp oLeUAQMTONVOS36vMSdNmZff5O76PxeBfzpDysEHRO2k0Fmo0ZE1Ulb12JMle1qgaCeH 6z8/YPw2eNfsqT8ojvojDKfjDlnGrA3PyaiILLNQnI2Tr1LOABrYWpNm5Lr+C1LWqD7A XKEQ== X-Forwarded-Encrypted: i=1; AJvYcCULayaSXkFZJezarw8G+Y8nOQTdpqt0ez6x61WYnGqepkUYMuhXgg4SZA2ePE8DSlt0ygorh6iieCs/X+g=@vger.kernel.org X-Gm-Message-State: AOJu0Yzf3RcX6gK74aUf+kTdRxJV14L/IiEODepeRGWIPKZ+c8Ezl4Sb xhPCvusRAtmA5WIPASi6YrbKBfIEIiXPSuM/VkQsQRNw/I+sIX3S5ZE2erbJLKelJqg= X-Gm-Gg: AY/fxX6YoLXq1rN2V3OfzENsn6U8xevQorGm96ndqhrTVNg8YOtIguD2p+3B4pgo6AK jqIrvDx+psUmnt4iWHiP2umDTPxFgGX97tes3JLhUMynx5w6/fik6OizWzaUoZxqoNZOgIYnFyz IQGld2OzY7zlzw1h+/AqOFwOGaRU2VyqUah668vTz4qO5Xp3iH7DPBZ7dZMS2ysFSgICLiihI+1 oMHYb9xY1w6/BT8/ZLpug2kdifOtivI84uXtM+zBT9Oxnc0PZvpF2O/zpZdbe1z8ja5U+XTuq+F tGXymO8+Jzabklv9NSSy5kM3RshYNd0WRltedVfQl2rSbaQ9i8pbTy9TVuG8Rq5gMrVFM0u/pSu 6Hr4O9K6AHrRJKkfe530qIGyRgWsSsWx0sk/phk/LMIcAeTe9By42+RMMRshV7oXpYAabydUIMr 8WaIoeoiQdlaCGn6+bh1oi8n2IPJ9LRKEnpayt9mDHOZ+pfEKVdLufrPclffku5tNXc3e9kPIFn h2HfDy92ZA97dyzQ9ow1SkaoH9w12jMB8A= X-Google-Smtp-Source: AGHT+IHcMyLakLOiabV0zgp9j2BbCuOpJ/ILNqwAtFawoKOVX3o7aGBaAA9adOk/BitF1e97wb/uow== X-Received: by 2002:a17:907:6d23:b0:b7d:266a:7728 with SMTP id a640c23a62f3a-b80371f8f50mr342762466b.44.1766162483979; Fri, 19 Dec 2025 08:41:23 -0800 (PST) Received: from [192.168.178.182] (2001-1c00-3b89-c600-71a4-084f-6409-1447.cable.dynamic.v6.ziggo.nl. [2001:1c00:3b89:c600:71a4:84f:6409:1447]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8037f4ef1fsm270073866b.64.2025.12.19.08.41.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 08:41:23 -0800 (PST) From: Luca Weiss Date: Fri, 19 Dec 2025 17:41:12 +0100 Subject: [PATCH RFC 6/6] arm64: dts: qcom: milos-fairphone-fp6: Enable panel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-milos-mdss-v1-6-4537a916bdf9@fairphone.com> References: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> In-Reply-To: <20251219-milos-mdss-v1-0-4537a916bdf9@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766162477; l=2578; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=LbaF66ke8LZxZbzBSqWF+LbtIQHMEYFknVPL8JPpg/I=; b=Rv0hSkSQEMyym7EIZ+cVRBj/6SP1f7dhM4pzbEWfaCF2YNFHzOP6VQw+YLffiycuav+hx1xjB GC1ASefj0LAB0zCj980vbPgQ3vI8SRE/lnefKNNv4uybbds++qyTiBv X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 71 ++++++++++++++++++++= ++-- 1 file changed, 66 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/= boot/dts/qcom/milos-fairphone-fp6.dts index 92b40ab56c26..8cddab412581 100644 --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -612,11 +612,6 @@ eeprom@51 { }; }; =20 -&dispcc { - /* Disable for now so simple-framebuffer continues working */ - status =3D "disabled"; -}; - &gcc { protected-clocks =3D , , , , @@ -725,6 +720,51 @@ &ipa { status =3D "okay"; }; =20 +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l4b>; + + status =3D "okay"; + + panel@0 { + compatible =3D "boe,bj631jhm-t71-d900"; + reg =3D <0>; + + reset-gpios =3D <&tlmm 12 GPIO_ACTIVE_LOW>; + + vci-supply =3D <&vreg_l19b>; + vddio-supply =3D <&vreg_l9b>; + dvdd-supply =3D <&vreg_oled_dvdd_1p2>; + // avdd-supply =3D <&pmiv0104_oledb> (VREG_OLEDB): 5V-8V + // elvss-supply =3D <&pmiv0104_elvss> (VREG_ELVSS): -8V-0V + // elvdd-supply =3D <&pmiv0104_elvdd> (VREG_ELVDD - OLEDB): 0-8V + + pinctrl-0 =3D <&disp_reset_n_active>, <&mdp_vsync>; + pinctrl-1 =3D <&disp_reset_n_suspend>, <&mdp_vsync>; + pinctrl-names =3D "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&panel_in>; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l2b>; + + status =3D "okay"; +}; + &pm8550vs_c { status =3D "okay"; }; @@ -883,6 +923,20 @@ &tlmm { <13 1>, /* NC */ <63 2>; /* WLAN UART */ =20 + disp_reset_n_active: disp-reset-n-active-state { + pins =3D "gpio12"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + disp_reset_n_suspend: disp-reset-n-suspend-state { + pins =3D "gpio12"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + ts_active: ts-irq-active-state { pins =3D "gpio19"; function =3D "gpio"; @@ -910,6 +964,13 @@ pm8008_int_default: pm8008-int-default-state { drive-strength =3D <2>; bias-disable; }; + + mdp_vsync: mdp-vsync-state { + pins =3D "gpio129"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; }; =20 &uart5 { --=20 2.52.0