From nobody Mon Feb 9 17:06:56 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED6102FBE1D for ; Fri, 19 Dec 2025 10:39:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766140769; cv=none; b=WXTtMGXEi3DTUgIbyTvK3Dh6CihmdITRX8DY4H7KPV29VprxBXWzQDNtnOZ4Lweybi5XWt3aQ3ZZ1BPd974btgrkP7CsaAv9QmhtJMuK4DA3WhEASKOREj+8F9FKevGXa7Y/hzzIvM3yVl4NsK1NbKVjR0p/ekku0KK+rB/zS+Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766140769; c=relaxed/simple; bh=wi1kWeqVtCbWuNJMTQVYzt1uY9+WlvJ3lb5IAUH9c3k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LSmyReuI2F++alwJnTHX9VEXt0YZrJm3M0UD9xW6zx35W418SeJmLRHfCymah/lHioTfer2BK0jfklx0rFCo0TjH7P7cR+JGhz5PSpw4ySjTwCKID6yrs4c1VTVM/u1SDZPovNqnM+YBXI1dJ9G688wb+RghlRVw9Orm81Kv5Y4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=YfO7yHca; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=IWPhJA5J; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="YfO7yHca"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="IWPhJA5J" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJ4c4UT091384 for ; Fri, 19 Dec 2025 10:39:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= VVlnWUp/w4USs5e7cXU6pqhnQwBXjqF4j7dJKWoQwZ0=; b=YfO7yHcaTUf6xUoC o2pNkJSSi1wyvHqS0u7m4SXXRhZaubF9KCdON5/BCXNlX+s2TVzuP2L6bIMG0jDY 0o5WckxEMkQ1Mfr9zGoGp1J72R9s7sIPZJHSHUV1Vv2+8zCEKemFRZeC0RwBtIOV Xo9AcfoplddS9UhAuFNWZ0waOm6AQYrHTc8yC+wQKEae8t0lQffQuvbaCmELuAxx PMopIhinmdCoe3jErvhmGvXnr7/5lb6U/onB6wNtTUne6y1SuKRlpHj7OlYbzR32 PMHrh3POuWzy0r+DNKPFCeVbh/mKqHL+Q0A9jlmgFZNsuBvbPr0mQEhsg6oD5cWV hjBZAw== Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r2eab6p-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 10:39:23 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-4ed6ceab125so37109071cf.1 for ; Fri, 19 Dec 2025 02:39:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766140763; x=1766745563; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VVlnWUp/w4USs5e7cXU6pqhnQwBXjqF4j7dJKWoQwZ0=; b=IWPhJA5JWH5C/2GX71LHlufltlDKKtMCnR9ouglv3RepaMScruBEsPGUGLzVX2NyBC /cF+OhB4/5wafoimQ7CRnsmVajAfC08iKX8D5gR79uTBUrG59AOR945GbmDgQOBd0Zjz JTlFx/Doz+e6fzSVHLrGV33fkcpH4ARyT9Vbs0v5GKPXn+vVgTfR5sAjyUNDuEr7egC3 WsiAdTbFNHyQRy49Ny4WXf1MV1k7ftvOZezsEIu0Xfv9fEqr7dfYi2fUhaewWqqLV34d BaH7lAT4MAE9kWe4sQgmWNsbaYbuRvlKQWaRuxf6PsytmwnV5BpsgF/0ypApwH4pgHqk S1KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766140763; x=1766745563; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=VVlnWUp/w4USs5e7cXU6pqhnQwBXjqF4j7dJKWoQwZ0=; b=qOtyl/9bfCmCNauDO4guG3mATGdyo9f3j/5Swkxp7kT+NL/j7Ih/WsSqcjWHMHMkmf LzEhTJ2dT6MOGCsO82a0QmJPcz90jG9qDTQECyHzGzjLwDbDH7Kxp1vv4a8SBhRnW1xj ocW0Eya2mWbW/Ld2A5LuluFQTxpLWATFxk86iNdCqOCfZ3Rdoj2LclwcfE1BX1xmXkzy 3YGEvTGDC2hzULouYsUkOqtpBKEBL8wsztlUVvR/+D4Pn6xkF/bo2tpnULRBjS1uwnBF hJKZrbmP8c1U4RF+2jJL/ArOoEV9pow1XjYMmRukSc3i66MY4styPWDuaLIuhb6t6WnO T5Zw== X-Forwarded-Encrypted: i=1; AJvYcCUaTEnSzFJ5G1p7HDwooF7C0nNNpL6M6RvLWOhBhLTT1baDFxt1NuL+GTwlgI3IIzQRz3OQC5lg+WmAJwI=@vger.kernel.org X-Gm-Message-State: AOJu0YxnncK+4R+WbhdWJr+nFsEYHRWweYSOUIOTJ8l2JwsNXEtM5BNN pjQD003yq7f/7ICYtrOCnLTBqO/HfePD4NFcYtOIOmA63nExOvRugb/OAiT1aH+SScxlyMbOXNh P10lcfHLt7Db++mzf0X4pNExLQ34GDCIk5NwUKQNuQNCa8DYFALEYQ5b8NNhk1iqCGhY= X-Gm-Gg: AY/fxX4icVY0NpYuEyTevdAcLKCN/HjwJlwodozp9vq31ezFsCXg25gz6qSYbH9qEsy Yat0yQtY8uWe/C4Vm+cUAGDtikoycP97tisT2Gsn1DYx5gHbD/v06rCjLCCKtMVzWLV+g5EaGZo 237wI8dWUG4tQ/+dhhnB9GSUG+2PT9aClfzxCRFUhIQuDajNtd4CxZBq+clnYuRs2uTF/bU0WN3 97Ha84ojqM6Td5JRNl6aVjicBPHx7eHdMqe/k7Ps6f/ElYjWeRXrNjwu78fJPYRQeJRF86X1q5k gK4pI13DiCaBP99MjBzt5iVAjbfFxZDcBiMZNp1srUO1T3akCw7PRMWBYpBUIE9q6pMORZP66jd y5bLKP0WRqWWtQAw= X-Received: by 2002:a05:622a:1991:b0:4f1:ccdd:ffde with SMTP id d75a77b69052e-4f4abcf1055mr32817501cf.21.1766140763073; Fri, 19 Dec 2025 02:39:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IFYl99OZQKs8AtrtbfkNPE8W0xYzxNA5YLSWYIo4XjVNxmPz4iliXF1DDLRwLnrCWoR8UukLg== X-Received: by 2002:a05:622a:1991:b0:4f1:ccdd:ffde with SMTP id d75a77b69052e-4f4abcf1055mr32817251cf.21.1766140762510; Fri, 19 Dec 2025 02:39:22 -0800 (PST) Received: from hackbox.lan ([86.121.7.169]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8037ad8577sm198142066b.24.2025.12.19.02.39.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 02:39:21 -0800 (PST) From: Abel Vesa Date: Fri, 19 Dec 2025 12:39:01 +0200 Subject: [PATCH 1/2] Revert "drm/msm/dpu: support plane splitting in quad-pipe case" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-drm-msm-dpu-revert-quad-pipe-broken-v1-1-654b46505f84@oss.qualcomm.com> References: <20251219-drm-msm-dpu-revert-quad-pipe-broken-v1-0-654b46505f84@oss.qualcomm.com> In-Reply-To: <20251219-drm-msm-dpu-revert-quad-pipe-broken-v1-0-654b46505f84@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: Jun Nie , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=openpgp-sha256; l=9496; i=abel.vesa@oss.qualcomm.com; h=from:subject:message-id; bh=wi1kWeqVtCbWuNJMTQVYzt1uY9+WlvJ3lb5IAUH9c3k=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBpRStUOq76iHmqLPdmQr0S1+R8z5u08yLvJKN0Q VHa8kQIsluJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaUUrVAAKCRAbX0TJAJUV Vs8AEACiTCATHLFheaEYCFwIbHZvGn2vHLdIFCyOdtzrGispO2wzN6Gmqb/J8ImT7Ezft/H3y1G KSR6MOf2q4QP2cxr129uNV0CS4i0H3pVgzoNlymGPvOIwAkWfT5G2fdOfpNi64yUJQCMqNcFsmy cU9SiD91Yrh8Gyf6LuOKhzMfyWK4avWFbrWS0yIzSLOaFo2L0a4B325gdn64Z20E5P8FEynj0fb EMS4KhnhM1AugH1GP3+777GmF+U0F8XassrBbZ6Ore7Ud+GZul/9l0fuL7OSPpzV3VMI2Y6JGH5 qmYId4mU6RJ5uo7jqGMTeCpDf7NOC5/OnakAJVkGkG+8MAzsVtNG10XrfK9YbItsKGPgBnPZp7t f/e/T6gunhpOSzZbrBjqfod8G+b+qIKVa1xkIhm2vZBsmRuOVrkoLhN9SHSXciHYOK/7I3q9sv6 b0CfeALyB5rgiDuIdP4lZY2gER2Vup7lAgTib/Ws9BjWHxOTA2Rg9ZePqcgHfDTCVAKOInSDE8a BVZXw4nh8tmgCblvOMjVZmzW7HIKqyy0TB/YJWT87HAjmoj+3Y5XDdZ1/jvbZlALe0GhpGc7A3k QAJAghbwN4QIuj/ehb4pmsjo/SdZdItwFISGYoTDKiXfdVK5xa7OKVEIwc049tstGrPfooyGWXU BiPHpi6Qh7lipDA== X-Developer-Key: i=abel.vesa@oss.qualcomm.com; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA4NyBTYWx0ZWRfX/blBysb2jQhE 0Hp2YhYLrE7Eoj+YhH94aFcLhxJXKQUgkeAxBDQMokMu6fRGgnnJd3V6fmVa5z05GWz5t9/xJ+8 H23MimZVF9YtxfO4JlTLHpTQDCmAknW2pU+aqie0Ag79QHYtZ0XrsVx83NQqXCQ4Uwm+Nq7AzRG NTcJj+LSkD5H+5L7sN6/TQzlK32qY4BxuFI1GU91Y1R+IngNPUuJeKWq2U0iMPYt1zUY3W1kx/j VMY0SWTuuzmOZr0vwGHtf+l4gjkjOpPzbr03cG7gwqBmf7UZqC2wZ8QXvn8wTqqPDw6wPfqtFax BonOfkso9zz4sustaXPZra2mL0IupLKQqmTBnNl40qTxCLCP4573/6v5vU03oxC5y8kxHnfO5x+ nzS/fRypkshQRXYIWa2xn7pdW+NkJQ+r2E/N3FbfUaF5cJkY3uUZVYXBCZIdrITr9QLUxmFJrg+ ct5pudXC9rFzIVDXs9A== X-Authority-Analysis: v=2.4 cv=W+c1lBWk c=1 sm=1 tr=0 ts=69452b5b cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=DdBtMnqNxkYIvXj6ev4VzQ==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=sWKEhP36mHoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=_o1CLn_ACWsE2PuA_oEA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-ORIG-GUID: zXDo12xEjZxBy6Ax5JlxxB486pAr2sQN X-Proofpoint-GUID: zXDo12xEjZxBy6Ax5JlxxB486pAr2sQN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_03,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 bulkscore=0 impostorscore=0 spamscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190087 This reverts commit 5978864e34b66bdae4d7613834c03dd5d0a0c891. At least on Hamoa based devices, there are IOMMU faults: arm-smmu 15000000.iommu: Unhandled context fault: fsr=3D0x402, iova=3D0x000= 00000, fsynr=3D0x3d0023, cbfrsynra=3D0x1c00, cb=3D13 arm-smmu 15000000.iommu: FSR =3D 00000402 [Format=3D2 TF], SID=3D0x1c00 arm-smmu 15000000.iommu: FSYNR0 =3D 003d0023 [S1CBNDX=3D61 PNU PLVL=3D3] While on some of these devices, there are also all sorts of artifacts on eD= P. Reverting this fixes these issues. Closes: https://lore.kernel.org/r/z75wnahrp7lrl5yhfdysr3np3qrs6xti2i4otkng4= ex3blfgrx@xyiucge3xykb/ Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 - drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 137 +++++++++-----------------= ---- 3 files changed, 40 insertions(+), 110 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index c39f1908ea65..011946bbf5a2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1620,17 +1620,6 @@ int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) return 0; } =20 -/** - * dpu_crtc_get_num_lm - Get mixer number in this CRTC pipeline - * @state: Pointer to drm crtc state object - */ -unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state) -{ - struct dpu_crtc_state *cstate =3D to_dpu_crtc_state(state); - - return cstate->num_mixers; -} - #ifdef CONFIG_DEBUG_FS static int _dpu_debugfs_status_show(struct seq_file *s, void *data) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.h index 455073c7025b..2c83f1578fc3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -267,6 +267,4 @@ static inline enum dpu_crtc_client_type dpu_crtc_get_cl= ient_type( =20 void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event); =20 -unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state); - #endif /* _DPU_CRTC_H_ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index d07a6ab6e7ee..9b7a8b46bfa9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -826,12 +826,8 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pl= ane *plane, struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); struct dpu_sw_pipe_cfg *pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg; - struct dpu_sw_pipe_cfg init_pipe_cfg; struct drm_rect fb_rect =3D { 0 }; - const struct drm_display_mode *mode =3D &crtc_state->adjusted_mode; uint32_t max_linewidth; - u32 num_lm; - int stage_id, num_stages; =20 min_scale =3D FRAC_16_16(1, MAX_UPSCALE_RATIO); max_scale =3D MAX_DOWNSCALE_RATIO << 16; @@ -854,10 +850,13 @@ static int dpu_plane_atomic_check_nosspp(struct drm_p= lane *plane, return -EINVAL; } =20 - num_lm =3D dpu_crtc_get_num_lm(crtc_state); - + /* move the assignment here, to ease handling to another pairs later */ + pipe_cfg =3D &pstate->pipe_cfg[0]; + r_pipe_cfg =3D &pstate->pipe_cfg[1]; /* state->src is 16.16, src_rect is not */ - drm_rect_fp_to_int(&init_pipe_cfg.src_rect, &new_plane_state->src); + drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); + + pipe_cfg->dst_rect =3D new_plane_state->dst; =20 fb_rect.x2 =3D new_plane_state->fb->width; fb_rect.y2 =3D new_plane_state->fb->height; @@ -882,94 +881,35 @@ static int dpu_plane_atomic_check_nosspp(struct drm_p= lane *plane, =20 max_linewidth =3D pdpu->catalog->caps->max_linewidth; =20 - drm_rect_rotate(&init_pipe_cfg.src_rect, + drm_rect_rotate(&pipe_cfg->src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); =20 - /* - * We have 1 mixer pair cfg for 1:1:1 and 2:2:1 topology, 2 mixer pair - * configs for left and right half screen in case of 4:4:2 topology. - * But we may have 2 rect to split wide plane that exceeds limit with 1 - * config for 2:2:1. So need to handle both wide plane splitting, and - * two halves of screen splitting for quad-pipe case. Check dest - * rectangle left/right clipping first, then check wide rectangle - * splitting in every half next. - */ - num_stages =3D (num_lm + 1) / 2; - /* iterate mixer configs for this plane, to separate left/right with the = id */ - for (stage_id =3D 0; stage_id < num_stages; stage_id++) { - struct drm_rect mixer_rect =3D { - .x1 =3D stage_id * mode->hdisplay / num_stages, - .y1 =3D 0, - .x2 =3D (stage_id + 1) * mode->hdisplay / num_stages, - .y2 =3D mode->vdisplay - }; - int cfg_idx =3D stage_id * PIPES_PER_STAGE; - - pipe_cfg =3D &pstate->pipe_cfg[cfg_idx]; - r_pipe_cfg =3D &pstate->pipe_cfg[cfg_idx + 1]; - - drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); - pipe_cfg->dst_rect =3D new_plane_state->dst; - - DPU_DEBUG_PLANE(pdpu, "checking src " DRM_RECT_FMT - " vs clip window " DRM_RECT_FMT "\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), - DRM_RECT_ARG(&mixer_rect)); - - /* - * If this plane does not fall into mixer rect, check next - * mixer rect. - */ - if (!drm_rect_clip_scaled(&pipe_cfg->src_rect, - &pipe_cfg->dst_rect, - &mixer_rect)) { - memset(pipe_cfg, 0, 2 * sizeof(struct dpu_sw_pipe_cfg)); - - continue; + if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || + _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_= clk_rate) { + if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; } =20 - pipe_cfg->dst_rect.x1 -=3D mixer_rect.x1; - pipe_cfg->dst_rect.x2 -=3D mixer_rect.x1; - - DPU_DEBUG_PLANE(pdpu, "Got clip src:" DRM_RECT_FMT " dst: " DRM_RECT_FMT= "\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), DRM_RECT_ARG(&pipe_cfg->dst_rect)); - - /* Split wide rect into 2 rect */ - if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || - _dpu_plane_calc_clk(mode, pipe_cfg) > max_mdp_clk_rate) { - - if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; - } - - memcpy(r_pipe_cfg, pipe_cfg, sizeof(struct dpu_sw_pipe_cfg)); - pipe_cfg->src_rect.x2 =3D (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x= 2) >> 1; - pipe_cfg->dst_rect.x2 =3D (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x= 2) >> 1; - r_pipe_cfg->src_rect.x1 =3D pipe_cfg->src_rect.x2; - r_pipe_cfg->dst_rect.x1 =3D pipe_cfg->dst_rect.x2; - DPU_DEBUG_PLANE(pdpu, "Split wide plane into:" - DRM_RECT_FMT " and " DRM_RECT_FMT "\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), - DRM_RECT_ARG(&r_pipe_cfg->src_rect)); - } else { - memset(r_pipe_cfg, 0, sizeof(struct dpu_sw_pipe_cfg)); - } + *r_pipe_cfg =3D *pipe_cfg; + pipe_cfg->src_rect.x2 =3D (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2= ) >> 1; + pipe_cfg->dst_rect.x2 =3D (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2= ) >> 1; + r_pipe_cfg->src_rect.x1 =3D pipe_cfg->src_rect.x2; + r_pipe_cfg->dst_rect.x1 =3D pipe_cfg->dst_rect.x2; + } else { + memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg)); + } =20 - drm_rect_rotate_inv(&pipe_cfg->src_rect, - new_plane_state->fb->width, - new_plane_state->fb->height, + drm_rect_rotate_inv(&pipe_cfg->src_rect, + new_plane_state->fb->width, new_plane_state->fb->height, + new_plane_state->rotation); + if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) + drm_rect_rotate_inv(&r_pipe_cfg->src_rect, + new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); =20 - if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) - drm_rect_rotate_inv(&r_pipe_cfg->src_rect, - new_plane_state->fb->width, - new_plane_state->fb->height, - new_plane_state->rotation); - } - pstate->needs_qos_remap =3D drm_atomic_crtc_needs_modeset(crtc_state); =20 return 0; @@ -1045,17 +985,20 @@ static int dpu_plane_atomic_check_sspp(struct drm_pl= ane *plane, drm_atomic_get_new_plane_state(state, plane); struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe *pipe; - struct dpu_sw_pipe_cfg *pipe_cfg; - int ret =3D 0, i; + struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; + int ret =3D 0; =20 - for (i =3D 0; i < PIPES_PER_PLANE; i++) { - pipe =3D &pstate->pipe[i]; - pipe_cfg =3D &pstate->pipe_cfg[i]; - if (!drm_rect_width(&pipe_cfg->src_rect)) - continue; - DPU_DEBUG_PLANE(pdpu, "pipe %d is in use, validate it\n", i); - ret =3D dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, + ret =3D dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, + &crtc_state->adjusted_mode, + new_plane_state); + if (ret) + return ret; + + if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) { + ret =3D dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, &crtc_state->adjusted_mode, new_plane_state); if (ret) --=20 2.48.1 From nobody Mon Feb 9 17:06:56 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A78B2D97B4 for ; Fri, 19 Dec 2025 10:39:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766140769; cv=none; b=HbLvTRO1EuGMNb4d+QQ7VuTTHwowNSFYI4YUAjQaL3gLiMvM84ay2guS7hrWA4n/qtxWI/vSsEvx3n0AKHKFNAclVuXd0Q71uZUEEIpvIgSsH1TFLhJ7htBlmZJ0daK1InP080FlhRZm4qVxZpaiRzUNVtTrRUjszMwdeuVn7vQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766140769; c=relaxed/simple; bh=xi0isO2zj7u63F4efQxBlJHUzywGMfOEhn2zIGrUuP0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AlSEhx7o7HhyId+7zIWDR5fHVxg68Dg462gyA/k2967wlHm9lg3T99q8MrwnDeYkX7Ihwum66BmbkFLxKwIx9uvmduvORGxMGxMuq7Gw19iOQlDOXhMkx9c6lA6TryEeEumBaE5vFtwK9rs6pe/vcleH47OxnaMNXAlrQ3YTsng= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=PL6mbnBv; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=WvCKXwO/; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="PL6mbnBv"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="WvCKXwO/" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJ4d7CP3561009 for ; Fri, 19 Dec 2025 10:39:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= sbDgyYqjBiwisdufx8Q+hYVd73Qfr9p891HKLDe9eZs=; b=PL6mbnBv7EfMa/B3 G/A19Ugs8x7no5uZnLc29BKl5Vn8kvur6C1cWp0BD6B1yAEL46bhrEpfcdmUJYlA MlUhdBP13GpNKF7CztRp2h3Rl/X+GwnC+iphFCsnCl7LXcBxunss8sfRgfeduSwY NQulyM566QcMI+8rgGko+9m8/K1S7D5MmjNzzlZx7nvROqa5FIFPAL/OHxZ66NR9 OyedHIjhIsqSVTv3pBbl/6/8r7WnQYdsY4ma6gMPrB7MHKBElv+Ov1CrdTHxZbMu ZJgrti+EpWkMyNssU+vC7PcmKI5W1AUxaLJHh9LOWSDp9k6mq3jr74AvbchRF3vn Hh5fgg== Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r2cac81-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 10:39:26 +0000 (GMT) Received: by mail-qt1-f199.google.com with SMTP id d75a77b69052e-4f1d2aa793fso36112651cf.3 for ; Fri, 19 Dec 2025 02:39:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766140765; x=1766745565; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=sbDgyYqjBiwisdufx8Q+hYVd73Qfr9p891HKLDe9eZs=; b=WvCKXwO/O4+Ee6au2ZhTGMOn7msgu5k3k4liWFb3bdkfY8PNeAzNULeedkLfLq1Bog 5sIDk/eZ3Q6D+frVbzKJbW0ytjrrd+Xo5v975Q+nzHwNV+Fh2NnFlR3CpwVqx5B0jbdv 9G9vqIMOK+LbT/XhwVnV6/7yf7s7FSO8cohkc3xMWM7Vsoq4WblXy6Q7V0LFGYSBjFug 9DYhl0LkfKT64nZ9f2Tfz5Gd37EWMGFe79GqgmL7G4n6vqaBmqQv4JmvMY+KsqT6AjYK TK9EPIYs66/0p90wpOnJXssUTLIQ7G9vRzsgBWGWSF2aECTSVuTHIvLFioU/t2uZNQvt 2C2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766140765; x=1766745565; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=sbDgyYqjBiwisdufx8Q+hYVd73Qfr9p891HKLDe9eZs=; b=nAGj1jE5xMVclC92iDoShxiQ8uoiYR5lDYomTqPPcqNUMsHj6PU3Ol+3Q6lYTfCvVl Q4eWsmM10uPmlGCWCVUReOuDiC1biQnw/KNxiFgoT/O5YOm6aj4k8tVAG1GmT8YxBbmN XX9VkijpgnF3yxjv/xFF/YjA/T1ktE8Ydgjif/GDwbcyrcqr+3onEVFy2mdiCLasXNBn cd6pubOIGvkVRxqzt8s8AAIaif6f39CkVhuVMlipZwlNZ8EkBEpPj3AIYCMmzYrL7K4V OyJGeJiSRvcjksAkkv9cllnBlU3OBwo4YKhso0Sv7uUgr8Holk7H19btJp2LLW1C3tcZ dBCA== X-Forwarded-Encrypted: i=1; AJvYcCXap1KzYfev/UkpnxWGgcnrZIekv17fHaC9SGDZ6vC4d/dPtUcuTvXgWc+6H7dK/SVnEW+51AynuLRLUg0=@vger.kernel.org X-Gm-Message-State: AOJu0YxmSYexBZJFkpKXUYiOIR//sVlSJtTHLXQbY+SJezjAwgu+w0Xj wsImAdddIxtWp2JmwesGdK3LEPbf+Mq8et79H3CBc47lT+jx1nIw4GzzVYHIAXtEf9Lx5Q3FZ1u uYufLUURvrRuh4RPU4H6OE6oHscH1KflpDMf1tr6+OUnRI7BLRrxt1gfsnCmcA8A6f4g= X-Gm-Gg: AY/fxX4198kM5213/w/CgKJt1s2AEchtb54YEWgn1IPzHmvdagO+F0LeRlran80+6AC ryG1aUTeZQQlpo75t0kCLSUoGFzIsysBl1DAk8ZT2NO8ZG1dsaD3IdgiA/v1IbECN6myiynJJAg MfEKBiOoAtv25vB2EENbcaNGZO/UFpGo2V34X5rfNhPvG+XzfLopVCv0RgW1D0rKigsoA5jSRuU mxDTslCVdbfX7c7nHllyIu1QNtfnj50nkbuVOpj69e/aTJuoOXirjMC8JiRI6TQWEI1It4PW5lF rRK4v9zygO8iykgVde7hjmwuByOWVynQrsPFBDMhzwnD6PyeTjS0yahg6J6Md1blVKkP3xwIw6I zhgLrg3RKs5MQw2M= X-Received: by 2002:a05:622a:244a:b0:4f1:dfc8:50b with SMTP id d75a77b69052e-4f4abdb50afmr28813831cf.76.1766140764936; Fri, 19 Dec 2025 02:39:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IE8DdSG740C5NPtMnK++fiGar0BQXZYGFlOhBwei0Gw+oZGsGEVWCVcw5gfBcVRV33F8o/4LA== X-Received: by 2002:a05:622a:244a:b0:4f1:dfc8:50b with SMTP id d75a77b69052e-4f4abdb50afmr28813631cf.76.1766140764354; Fri, 19 Dec 2025 02:39:24 -0800 (PST) Received: from hackbox.lan ([86.121.7.169]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8037ad8577sm198142066b.24.2025.12.19.02.39.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 02:39:23 -0800 (PST) From: Abel Vesa Date: Fri, 19 Dec 2025 12:39:02 +0200 Subject: [PATCH 2/2] Revert "drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-drm-msm-dpu-revert-quad-pipe-broken-v1-2-654b46505f84@oss.qualcomm.com> References: <20251219-drm-msm-dpu-revert-quad-pipe-broken-v1-0-654b46505f84@oss.qualcomm.com> In-Reply-To: <20251219-drm-msm-dpu-revert-quad-pipe-broken-v1-0-654b46505f84@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: Jun Nie , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=openpgp-sha256; l=7927; i=abel.vesa@oss.qualcomm.com; h=from:subject:message-id; bh=xi0isO2zj7u63F4efQxBlJHUzywGMfOEhn2zIGrUuP0=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBpRStWe971J3fXTWEto13F48xEAWlKpa5UIoGw+ D+K2Ywjo9CJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaUUrVgAKCRAbX0TJAJUV Vhq2EACMJmriHKHHwDFtldQFgURBx4XUWuTs2XtI6i/Lz1PK+mNP3KE6bb02hHOT9IQv5viiWMu Q7f/wqUQX8WTlW27jFbpxXs+AusXdLV5Tjkx+KlAtjuJ1GkRiKGBCa6nvc8Zml+m9mTsA4sCm6R xN8/Nqf1955BF2X+9qS7t27e1dHFl0Z6bov60B55+1+V9DQmHARRDBnabvRTn2ttIrfapZfxj6S 9PsJG0d4MCqPZ+6Ap2TAVP/1x5qL9Le1vDR3dChYL3rlxYXLjIpzKDwqvw20rolUk2HPBoKOhZA IoumZx27B8wJP1fouA4tXkP3sklTjaedbdvZbBdfdtJ2Oqw6S6cSUJ+P+sF5V4t0QytGRm8lVIV m1M6h8hgIl6fEE+OIF+MdOHxie9RpgNV+Bn/Au0X7MaXx3hAEAMllohmUrvn+erTNzSzuRxwS7w U60+NY2ypnELM3YT6p6ZVwdAQdpH2eTFiSyqaxMGQRXbFD4y0KulWSWCb2rt6/2FrkIo7NI0/0y lKSYhb60Q6tAStYRyJBTNVOJWNwzX274eH2zLVIqR9D8MX0sQ+shMiRPN+2WQlasy4UQUiAKGNe 3LXjhrbdhacEsctzY9VMnAboKO09+7NpxVh2h4afqs6wY6yU2cOh79KjXyVXBTKlW4Q7wZl6N5c sfQV7olIOinz7XQ== X-Developer-Key: i=abel.vesa@oss.qualcomm.com; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Authority-Analysis: v=2.4 cv=cpSWUl4i c=1 sm=1 tr=0 ts=69452b5e cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=DdBtMnqNxkYIvXj6ev4VzQ==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=tVI0ZWmoAAAA:8 a=EUspDBNiAAAA:8 a=ZMc9qBuXswDIMKfH7wMA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 a=-BPWgnxRz2uhmvdm1NTO:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA4NyBTYWx0ZWRfX9MPg6V2Xz214 T+JboPN04yqjR643lHx01lpg+yerO7ZX3XppEwu5FpqNAfld0qYjka9zLw3j8QAjalW0BhLqsBA F6J9BcQ76GbXh7h/iqCeTri0/tDZpqTH78GU2hmmak78C+sU6cYhBbQgoIkpOWQ5nE7PSpKxtCt FuuPmwbHunFhGnw++Y+ER1oJIH1pRjLoh0W7PtmSFWBuBtJSTOzvfr+i/v0wUpkY0arOK30+AUQ i/q7WM4eUtjYV5jnE2Cy1nwlw4aojblm2OOPZJ5k7Zu/DBLijoAgtWxev/0ZeRvgchU1RkIWrzy iZpJW0LHSaU4ArsihaSiOt8lTulkVW2tJoIAaDAL2+t5FVY/ZhTmeT/wkaePgmhGJmk7CUA553G 98BT6b9fDhuyQAcSwX/8ahKRSSCdmTrm3mvrhNstr3Fqky9oRcDkns2DS93sgp2oLqw7dKDTDwG 1dHTsF3WlD6/cfbFQkA== X-Proofpoint-GUID: cOSbn79NtvXsMzfknXRwQe1dywjQv3V7 X-Proofpoint-ORIG-GUID: cOSbn79NtvXsMzfknXRwQe1dywjQv3V7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_03,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 suspectscore=0 bulkscore=0 phishscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190087 This reverts commit d7ec9366b15cd04508fa015cb94d546b1c01edfb. The dual-DSI dual-DSC scenario seems to be broken by this commit. Reported-by: Marijn Suijten Closes: https://lore.kernel.org/r/aUR2b3FOSisTfDFj@SoMainline.org Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 27 ++++++--------------= -- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 ++++++++++++++++----= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +- 6 files changed, 33 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 011946bbf5a2..2d06c950e814 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -200,7 +200,7 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc, struct dpu_crtc_state *crtc_state) { struct dpu_crtc_mixer *m; - u32 crcs[CRTC_QUAD_MIXERS]; + u32 crcs[CRTC_DUAL_MIXERS]; =20 int rc =3D 0; int i; @@ -1328,7 +1328,6 @@ static struct msm_display_topology dpu_crtc_get_topol= ogy( struct drm_display_mode *mode =3D &crtc_state->adjusted_mode; struct msm_display_topology topology =3D {0}; struct drm_encoder *drm_enc; - u32 num_rt_intf; =20 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask) dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state, @@ -1342,14 +1341,11 @@ static struct msm_display_topology dpu_crtc_get_top= ology( * Dual display * 2 LM, 2 INTF ( Split display using 2 interfaces) * - * If DSC is enabled, try to use 4:4:2 topology if there is enough - * resource. Otherwise, use 2:2:2 topology. - * * Single display * 1 LM, 1 INTF * 2 LM, 1 INTF (stream merge to support high resolution interfaces) * - * If DSC is enabled, use 2:2:1 topology + * If DSC is enabled, use 2 LMs for 2:2:1 topology * * Add dspps to the reservation requirements if ctm is requested * @@ -1361,23 +1357,14 @@ static struct msm_display_topology dpu_crtc_get_top= ology( * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check. */ =20 - num_rt_intf =3D topology.num_intf; - if (topology.cwb_enabled) - num_rt_intf--; - - if (topology.num_dsc) { - if (dpu_kms->catalog->dsc_count >=3D num_rt_intf * 2) - topology.num_dsc =3D num_rt_intf * 2; - else - topology.num_dsc =3D num_rt_intf; - topology.num_lm =3D topology.num_dsc; - } else if (num_rt_intf =3D=3D 2) { + if (topology.num_intf =3D=3D 2 && !topology.cwb_enabled) + topology.num_lm =3D 2; + else if (topology.num_dsc =3D=3D 2) topology.num_lm =3D 2; - } else if (dpu_kms->catalog->caps->has_3d_merge) { + else if (dpu_kms->catalog->caps->has_3d_merge) topology.num_lm =3D (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; - } else { + else topology.num_lm =3D 1; - } =20 if (crtc_state->ctm) topology.num_dspp =3D topology.num_lm; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.h index 2c83f1578fc3..94392b9b9245 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -210,7 +210,7 @@ struct dpu_crtc_state { =20 bool bw_control; bool bw_split_vote; - struct drm_rect lm_bounds[CRTC_QUAD_MIXERS]; + struct drm_rect lm_bounds[CRTC_DUAL_MIXERS]; =20 uint64_t input_fence_timeout_ns; =20 @@ -218,10 +218,10 @@ struct dpu_crtc_state { =20 /* HW Resources reserved for the crtc */ u32 num_mixers; - struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS]; + struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS]; =20 u32 num_ctls; - struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS]; + struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS]; =20 enum dpu_crtc_crc_source crc_source; int crc_frame_skip_count; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index d1cfe81a3373..9f3957f24c6a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -55,7 +55,7 @@ #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) =20 -#define MAX_CHANNELS_PER_ENC 4 +#define MAX_CHANNELS_PER_ENC 2 #define MAX_CWB_PER_ENC 2 =20 #define IDLE_SHORT_TIMEOUT 1 @@ -661,6 +661,7 @@ void dpu_encoder_update_topology(struct drm_encoder *dr= m_enc, struct dpu_encoder_virt *dpu_enc =3D to_dpu_encoder_virt(drm_enc); struct msm_drm_private *priv =3D dpu_enc->base.dev->dev_private; struct msm_display_info *disp_info =3D &dpu_enc->disp_info; + struct dpu_kms *dpu_kms =3D to_dpu_kms(priv->kms); struct drm_connector *connector; struct drm_connector_state *conn_state; struct drm_framebuffer *fb; @@ -674,12 +675,22 @@ void dpu_encoder_update_topology(struct drm_encoder *= drm_enc, =20 dsc =3D dpu_encoder_get_dsc_config(drm_enc); =20 - /* - * Set DSC number as 1 to mark the enabled status, will be adjusted - * in dpu_crtc_get_topology() - */ - if (dsc) - topology->num_dsc =3D 1; + /* We only support 2 DSC mode (with 2 LM and 1 INTF) */ + if (dsc) { + /* + * Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces + * when Display Stream Compression (DSC) is enabled, + * and when enough DSC blocks are available. + * This is power-optimal and can drive up to (including) 4k + * screens. + */ + WARN(topology->num_intf > 2, + "DSC topology cannot support more than 2 interfaces\n"); + if (topology->num_intf >=3D 2 || dpu_kms->catalog->dsc_count >=3D 2) + topology->num_dsc =3D 2; + else + topology->num_dsc =3D 1; + } =20 connector =3D drm_atomic_get_new_connector_for_encoder(state, drm_enc); if (!connector) @@ -2169,8 +2180,8 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) { int i, num_lm; struct dpu_global_state *global_state; - struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; - struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_blk *hw_lm[2]; + struct dpu_hw_mixer *hw_mixer[2]; struct dpu_hw_ctl *ctl =3D phys_enc->hw_ctl; =20 /* reset all mixers for this encoder */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu= /drm/msm/disp/dpu1/dpu_encoder_phys.h index 09395d7910ac..61b22d949454 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -302,7 +302,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper= _get_3d_blend_mode( =20 /* Use merge_3d unless DSC MERGE topology is used */ if (phys_enc->split_role =3D=3D ENC_ROLE_SOLO && - (dpu_cstate->num_mixers !=3D 1) && + dpu_cstate->num_mixers =3D=3D CRTC_DUAL_MIXERS && !dpu_encoder_use_dsc_merge(phys_enc->parent)) return BLEND_3D_H_ROW_INT; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 336757103b5a..4964e70610d1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -24,7 +24,7 @@ #define DPU_MAX_IMG_WIDTH 0x3fff #define DPU_MAX_IMG_HEIGHT 0x3fff =20 -#define CRTC_QUAD_MIXERS 4 +#define CRTC_DUAL_MIXERS 2 =20 #define MAX_XIN_COUNT 16 =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index 31451241f083..046b683d4c66 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -34,7 +34,7 @@ #define DPU_MAX_PLANES 4 #endif =20 -#define STAGES_PER_PLANE 2 +#define STAGES_PER_PLANE 1 #define PIPES_PER_STAGE 2 #define PIPES_PER_PLANE (PIPES_PER_STAGE * STAGES_PER_PLANE) #ifndef DPU_MAX_DE_CURVES --=20 2.48.1