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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3d74bbbsm18164435ad.94.2025.12.19.02.04.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Dec 2025 02:04:57 -0800 (PST) From: Jie Gan Date: Fri, 19 Dec 2025 18:04:19 +0800 Subject: [PATCH v5 1/3] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251219-add_sysfs_nodes_to_configure_tpda-v5-1-ca93ddfe9d30@oss.qualcomm.com> References: <20251219-add_sysfs_nodes_to_configure_tpda-v5-0-ca93ddfe9d30@oss.qualcomm.com> In-Reply-To: <20251219-add_sysfs_nodes_to_configure_tpda-v5-0-ca93ddfe9d30@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jie Gan , Tao Zhang X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766138690; l=11494; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=pYkWJ39bXMAgla+YRut4Ot+Wr3AUNmRRPeXCaTiOkcA=; b=mICP7fyWmwQuBtLJ8evjUCT3HDSruND5oM0Rhwtr2X3x2XZbxbBoY+AJztD/aeqfuco18adYn sK/QRELQHIcD2kxERIksDVA6QGqaHbXz8dZRnZlUzyylOI92AKg+1Y1 X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Authority-Analysis: v=2.4 cv=NODYOk6g c=1 sm=1 tr=0 ts=6945234c cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=HmS9xeJcQxVnfQIoWMEA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: nUTRbM4oxP-u-uISGQpfljTJrqrfIG1x X-Proofpoint-GUID: nUTRbM4oxP-u-uISGQpfljTJrqrfIG1x X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDA4MiBTYWx0ZWRfX7p0oMTvfLrNJ hpKJZCblzHNQG3C0+FoZwyXQ426/MRBfTy0N7hIWD0qJ05xj7cyd2b5rIW+/39/am5v0k6JTV0T VDc9TNk6gbNwFJqZn5K8vsfj8Q5zyP26R1ohFF+8374nGNSsuUe4sjK42djyOk1v4s6RbA8NcCQ lYafmQELs2PX5Qu6hpPs601rbj8HB5g8u9LGVJq+W64OVJ2wPNUNxRFm5JEYcr0DrPDsKbRKqae oFYOlon9PavuIJ6pkjYI+zf1kUC/BkJO6NF5x0evHyE9dooaKIXNuNKm7iRjqDmxVwmniwsjCkZ /KzRQvDiwd+1E0S8J56Aq6GRXCs8pCZwxZyV3ixFXtNd/QsiKdjW2y44CMIKQpjQJ3+T1eJ99JX pZmMDJWY8yiF6ZvKurDliLKamVzMyWCiKulHgKnnbJgBisRxSqt21wmzbc1Py6+vH8SgJAKkQHG Im3QjjC6Cg3Nu2wyScw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_03,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 suspectscore=0 impostorscore=0 bulkscore=0 adultscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190082 From: Tao Zhang Introduce sysfs nodes to configure cross-trigger parameters for TPDA. These registers define the characteristics of cross-trigger packets, including generation frequency and flag values. Signed-off-by: Tao Zhang Reviewed-by: James Clark Co-developed-by: Jie Gan Signed-off-by: Jie Gan --- .../ABI/testing/sysfs-bus-coresight-devices-tpda | 43 +++++++ drivers/hwtracing/coresight/coresight-tpda.c | 138 +++++++++++++++++= +++- drivers/hwtracing/coresight/coresight-tpda.h | 69 ++++++++++- 3 files changed, 243 insertions(+), 7 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-tpda new file mode 100644 index 000000000000..a7855922328e --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda @@ -0,0 +1,43 @@ +What: /sys/bus/coresight/devices//global_cr/trig_async_enable +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable cross trigger synchronization sequence interface. + +What: /sys/bus/coresight/devices//global_cr/trig_flag_ts_enable +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable cross trigger FLAG packet request interface. + +What: /sys/bus/coresight/devices//global_cr/trig_freq_enable +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable cross trigger FREQ packet request interface. + +What: /sys/bus/coresight/devices//global_cr/freq_ts_enable +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable the timestamp for all FREQ packets. + +What: /sys/bus/coresight/devices//global_cr/global_flush_req +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Set global (all ports) flush request bit. The bit remains set until= a + global flush request sequence completes. + +What: /sys/bus/coresight/devices//global_cr/cmbchan_mode +Date: December 2025 +KernelVersion: 6.19 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Configure the CMB/MCMB channel mode for all enabled ports. + Value 0 means raw channel mapping mode. Value 1 means channel pair marki= ng mode. diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtraci= ng/coresight/coresight-tpda.c index 3a3825d27f86..d25a8bcfb3d4 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -137,12 +137,32 @@ static int tpda_get_element_size(struct tpda_drvdata = *drvdata, /* Settings pre enabling port control register */ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) { - u32 val; + u32 val =3D 0; =20 - val =3D readl_relaxed(drvdata->base + TPDA_CR); - val &=3D ~TPDA_CR_ATID; val |=3D FIELD_PREP(TPDA_CR_ATID, drvdata->atid); + if (drvdata->trig_async) + val |=3D TPDA_CR_SRIE; + + if (drvdata->trig_flag_ts) + val |=3D TPDA_CR_FLRIE; + + if (drvdata->trig_freq) + val |=3D TPDA_CR_FRIE; + + if (drvdata->freq_ts) + val |=3D TPDA_CR_FREQTS; + + if (drvdata->cmbchan_mode) + val |=3D TPDA_CR_CMBCHANMODE; + writel_relaxed(val, drvdata->base + TPDA_CR); + + /* + * If FLRIE bit is set, set the master and channel + * id as zero + */ + if (drvdata->trig_flag_ts) + writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); } =20 static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) @@ -258,6 +278,116 @@ static const struct coresight_ops tpda_cs_ops =3D { .link_ops =3D &tpda_link_ops, }; =20 +/* Read cross-trigger register member */ +static ssize_t tpda_trig_sysfs_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_trig_sysfs_attribute *tpda_attr =3D + container_of(attr, struct tpda_trig_sysfs_attribute, attr); + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + guard(spinlock)(&drvdata->spinlock); + switch (tpda_attr->mem) { + case FLREQ: + if (!drvdata->csdev->refcnt) + return -EINVAL; + + val =3D readl_relaxed(drvdata->base + TPDA_CR); + /* read global flush request bit only */ + val &=3D TPDA_CR_FLREQ; + return sysfs_emit(buf, "%lu\n", val); + case FREQTS: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->freq_ts); + case FRIE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_freq); + case FLRIE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_flag_ts); + case SRIE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async); + case CMBCHANMODE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->cmbchan_mode); + + } + return -EINVAL; +} + +static ssize_t tpda_trig_sysfs_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_trig_sysfs_attribute *tpda_attr =3D + container_of(attr, struct tpda_trig_sysfs_attribute, attr); + struct tpda_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + ssize_t ret =3D -EINVAL; + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return ret; + + guard(spinlock)(&drvdata->spinlock); + switch (tpda_attr->mem) { + case FLREQ: + if (!drvdata->csdev->refcnt || !val) + return ret; + + val =3D readl_relaxed(drvdata->base + TPDA_CR); + /* set global flush request bit */ + val |=3D TPDA_CR_FLREQ; + CS_UNLOCK(drvdata->base); + writel_relaxed(val, drvdata->base + TPDA_CR); + CS_LOCK(drvdata->base); + ret =3D size; + break; + case FREQTS: + drvdata->freq_ts =3D !!val; + ret =3D size; + break; + case FRIE: + drvdata->trig_freq =3D !!val; + ret =3D size; + break; + case FLRIE: + drvdata->trig_flag_ts =3D !!val; + ret =3D size; + break; + case SRIE: + drvdata->trig_async =3D !!val; + ret =3D size; + break; + case CMBCHANMODE: + drvdata->cmbchan_mode =3D !!val; + ret =3D size; + break; + default: + break; + } + + return ret; +} + +static struct attribute *tpda_global_cr_attrs[] =3D { + tpda_trig_sysfs_rw(global_flush_req, FLREQ), + tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), + tpda_trig_sysfs_rw(trig_freq_enable, FRIE), + tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), + tpda_trig_sysfs_rw(trig_async_enable, SRIE), + tpda_trig_sysfs_rw(cmbchan_mode, CMBCHANMODE), + NULL, +}; + +static struct attribute_group tpda_global_cr_attr_grp =3D { + .attrs =3D tpda_global_cr_attrs, + .name =3D "global_cr", +}; + +static const struct attribute_group *tpda_attr_grps[] =3D { + &tpda_global_cr_attr_grp, + NULL, +}; + static int tpda_init_default_data(struct tpda_drvdata *drvdata) { int atid; @@ -273,6 +403,7 @@ static int tpda_init_default_data(struct tpda_drvdata *= drvdata) return atid; =20 drvdata->atid =3D atid; + drvdata->freq_ts =3D true; return 0; } =20 @@ -316,6 +447,7 @@ static int tpda_probe(struct amba_device *adev, const s= truct amba_id *id) desc.ops =3D &tpda_cs_ops; desc.pdata =3D adev->dev.platform_data; desc.dev =3D &adev->dev; + desc.groups =3D tpda_attr_grps; desc.access =3D CSDEV_ACCESS_IOMEM(base); drvdata->csdev =3D coresight_register(&desc); if (IS_ERR(drvdata->csdev)) diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtraci= ng/coresight/coresight-tpda.h index c6af3d2da3ef..8a075cfbc3cc 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023,2025 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 #ifndef _CORESIGHT_CORESIGHT_TPDA_H @@ -8,6 +8,30 @@ =20 #define TPDA_CR (0x000) #define TPDA_Pn_CR(n) (0x004 + (n * 4)) +#define TPDA_FPID_CR (0x084) + +/* Cross trigger Global (all ports) flush request bit */ +#define TPDA_CR_FLREQ BIT(0) +/* Cross trigger FREQ packets timestamp bit */ +#define TPDA_CR_FREQTS BIT(2) +/* Cross trigger FREQ packet request bit */ +#define TPDA_CR_FRIE BIT(3) +/* Cross trigger FLAG packet request interface bit */ +#define TPDA_CR_FLRIE BIT(4) +/* Cross trigger synchronization bit */ +#define TPDA_CR_SRIE BIT(5) +/* Bits 6 ~ 12 is for atid value */ +#define TPDA_CR_ATID GENMASK(12, 6) +/* Bits 13 ~ 19 is for mid value */ +/* Assign a unique master ID to identify the TPDA device */ +#define TPDA_CR_MID GENMASK(19, 13) +/* + * Channel mode bit of the packetization of CMB/MCB traffic + * 0 - raw channel mapping mode + * 1 - channel pair marking mode + */ +#define TPDA_CR_CMBCHANMODE BIT(20) + /* Aggregator port enable bit */ #define TPDA_Pn_CR_ENA BIT(0) /* Aggregator port CMB data set element size bit */ @@ -17,9 +41,6 @@ =20 #define TPDA_MAX_INPORTS 32 =20 -/* Bits 6 ~ 12 is for atid value */ -#define TPDA_CR_ATID GENMASK(12, 6) - /** * struct tpda_drvdata - specifics associated to an TPDA component * @base: memory mapped base address for this component. @@ -29,6 +50,11 @@ * @enable: enable status of the component. * @dsb_esize Record the DSB element size. * @cmb_esize Record the CMB element size. + * @trig_async: Enable/disable cross trigger synchronization sequence inte= rface. + * @trig_flag_ts: Enable/disable cross trigger FLAG packet request interfa= ce. + * @trig_freq: Enable/disable cross trigger FREQ packet request interface. + * @freq_ts: Enable/disable the timestamp for all FREQ packets. + * @cmbchan_mode: Configure the CMB/MCMB channel mode. */ struct tpda_drvdata { void __iomem *base; @@ -38,6 +64,41 @@ struct tpda_drvdata { u8 atid; u32 dsb_esize; u32 cmb_esize; + bool trig_async; + bool trig_flag_ts; + bool trig_freq; + bool freq_ts; + bool cmbchan_mode; +}; + +/* Enumerate members of global control register(cr) */ +enum tpda_cr_mem { + FLREQ, + FREQTS, + FRIE, + FLRIE, + SRIE, + CMBCHANMODE +}; + +/** + * struct tpda_trig_sysfs_attribute - Record the member variables of cross + * trigger register that need to be operated by sysfs file + * @attr: The device attribute + * @mem: The member in the control register data structure + */ +struct tpda_trig_sysfs_attribute { + struct device_attribute attr; + enum tpda_cr_mem mem; }; =20 +#define tpda_trig_sysfs_rw(name, mem) \ + (&((struct tpda_trig_sysfs_attribute[]) { \ + { \ + __ATTR(name, 0644, tpda_trig_sysfs_show, \ + tpda_trig_sysfs_store), \ + mem, \ + } \ + })[0].attr.attr) + #endif /* _CORESIGHT_CORESIGHT_TPDA_H */ --=20 2.34.1