From nobody Fri Dec 19 08:54:51 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FE992FE07F; Thu, 18 Dec 2025 15:15:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766070921; cv=none; b=g7vtl35rMN9gsR6evVpHnBszQVNX1KbXCb82WMBL4k45fKoyZLmdREKvCC0amopWqrhJ6qHNrORstrfTYSBZ6THlifTy2p5UGjE9XUPx/FGtf1TeduJgIbDY+mG5WGWoE3TOO3eDF9p8a9jykD++0FQxpsEMuW7W17JUZyUYT5Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766070921; c=relaxed/simple; bh=Smckrg7+KnbhrTERu00VP73ZnleaknC3grp6RThlXuY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=S2QXSoeeMLyWdB2mXmkQSHyeC3lZULnbdgWYSgJ7rO/O0pp9n9l9AH5IMyFUrPLcaTWy8j4VtLb2671/BPra5ZAl6ZUOAMPYk8gacqMed7MhI9sWvGJOFFpM+cV8BwKb8s5/itV5xsZsjydvr9gNzCoeSabriHbiDOgidisvQGM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NICkP0e8; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NICkP0e8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1766070918; x=1797606918; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Smckrg7+KnbhrTERu00VP73ZnleaknC3grp6RThlXuY=; b=NICkP0e81rJqgx60IMYb3UV5so1NKPJ7Hy8NO05j91ljeoOcHzzZrPY5 RXaDA7JEc2tmT81hiPpOaCGsp68euR26kuqhPfgP/NB4eGzwRxGFqnzze t08X2FpKl3U9deH0LZaA4dj3vniyqGf9jM91vnsoqSW5zNVcCOpnv29f0 uWaWxxRiY6hV2EEMfIQl37hIiMYWdx5gVbBBh/jiA5bNBoTBp1JfkgNYe dWJcLZR4q827Hp2cHYr2wIRaiJNBEmlbw274a+JU0M3U8DnijlpJ+axx1 +hRtNaDxLCP1jvDN949r6Pt3J9XKv9G/cReceunK+cg8zvoRxcGvpven8 Q==; X-CSE-ConnectionGUID: 22tLWWmzQ/W9kPC4IaLZYw== X-CSE-MsgGUID: xpZ8jvY2TaKkz2PGMhRH3g== X-IronPort-AV: E=McAfee;i="6800,10657,11646"; a="78739517" X-IronPort-AV: E=Sophos;i="6.21,158,1763452800"; d="scan'208";a="78739517" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Dec 2025 07:15:14 -0800 X-CSE-ConnectionGUID: iRsxyoQvScS0jzXGhQDb+g== X-CSE-MsgGUID: GOlqyDczQ1uRAdst+VM4Yg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,158,1763452800"; d="scan'208";a="197857486" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa010.jf.intel.com with ESMTP; 18 Dec 2025 07:15:13 -0800 From: Heikki Krogerus To: Andi Shyti , Mika Westerberg Cc: Andy Shevchenko , Jan Dabros , Raag Jadav , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/6] i2c: designware: Remove useless driver specific option for I2C target Date: Thu, 18 Dec 2025 16:15:00 +0100 Message-ID: <20251218151509.361617-2-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251218151509.361617-1-heikki.krogerus@linux.intel.com> References: <20251218151509.361617-1-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The generic option for I2C target is already user selectable, which makes the DesignWare specific option completely unnecessary. The DesignWare option also silently selected I2C_SLAVE instead of depending on it without any real need for it. Reviewed-by: Andy Shevchenko Signed-off-by: Heikki Krogerus Acked-by: Mika Westerberg --- drivers/i2c/busses/Kconfig | 10 ++-------- drivers/i2c/busses/Makefile | 2 +- drivers/i2c/busses/i2c-designware-core.h | 2 +- 3 files changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 09ba55bae1fa..860812e224a0 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -569,20 +569,14 @@ config I2C_DESIGNWARE_CORE help This option enables support for the Synopsys DesignWare I2C adapter. This driver includes support for the I2C host on the Synopsys - Designware I2C adapter. + Designware I2C adapter, and the I2C slave when enabled (select + I2C_SLAVE). =20 To compile the driver as a module, choose M here: the module will be called i2c-designware-core. =20 if I2C_DESIGNWARE_CORE =20 -config I2C_DESIGNWARE_SLAVE - bool "Synopsys DesignWare Slave" - select I2C_SLAVE - help - If you say yes to this option, support will be included for the - Synopsys DesignWare I2C slave adapter. - config I2C_DESIGNWARE_PLATFORM tristate "Synopsys DesignWare Platform driver" depends on (ACPI && COMMON_CLK) || !ACPI diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index fb985769f5ff..547123ab351f 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -53,7 +53,7 @@ obj-$(CONFIG_I2C_DAVINCI) +=3D i2c-davinci.o obj-$(CONFIG_I2C_DESIGNWARE_CORE) +=3D i2c-designware-core.o i2c-designware-core-y :=3D i2c-designware-common.o i2c-designware-core-y +=3D i2c-designware-master.o -i2c-designware-core-$(CONFIG_I2C_DESIGNWARE_SLAVE) +=3D i2c-designware-sl= ave.o +i2c-designware-core-$(CONFIG_I2C_SLAVE) +=3D i2c-designware-slave.o obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) +=3D i2c-designware-platform.o i2c-designware-platform-y :=3D i2c-designware-platdrv.o i2c-designware-platform-$(CONFIG_I2C_DESIGNWARE_AMDPSP) +=3D i2c-designwar= e-amdpsp.o diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/= i2c-designware-core.h index bb5ce0a382f9..2a7decc24931 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -386,7 +386,7 @@ void i2c_dw_disable(struct dw_i2c_dev *dev); extern void i2c_dw_configure_master(struct dw_i2c_dev *dev); extern int i2c_dw_probe_master(struct dw_i2c_dev *dev); =20 -#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE) +#if IS_ENABLED(CONFIG_I2C_SLAVE) extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev); extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev); #else --=20 2.50.1 From nobody Fri Dec 19 08:54:51 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 722E21CEAB2; Thu, 18 Dec 2025 15:15:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766070923; cv=none; b=QLatm0LC1A9BajjxkG1zgr/uFrrNn7uX2etjGfXaCgewCLW67lFEW4oOyJ0cSZkRye19oMSDDms9KPkydQjO+Q6dFH+wAPoVIZFYpKlimVGbd8pOe57jymBlgB3fNT2hQEVEg6F0Q4mWRWkfbQD9r1TSSYwneNH2l8xAJZ49Ht4= ARC-Message-Signature: i=1; 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d="scan'208";a="197857491" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa010.jf.intel.com with ESMTP; 18 Dec 2025 07:15:15 -0800 From: Heikki Krogerus To: Andi Shyti , Mika Westerberg Cc: Andy Shevchenko , Jan Dabros , Raag Jadav , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/6] i2c: designware: Remove unnecessary function exports Date: Thu, 18 Dec 2025 16:15:01 +0100 Message-ID: <20251218151509.361617-3-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251218151509.361617-1-heikki.krogerus@linux.intel.com> References: <20251218151509.361617-1-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The master and slave probe functions are only called from the core. Reviewed-by: Andy Shevchenko Signed-off-by: Heikki Krogerus Acked-by: Mika Westerberg --- drivers/i2c/busses/i2c-designware-master.c | 1 - drivers/i2c/busses/i2c-designware-slave.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busse= s/i2c-designware-master.c index f247cf323207..15b3a46f0132 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -1101,7 +1101,6 @@ int i2c_dw_probe_master(struct dw_i2c_dev *dev) =20 return ret; } -EXPORT_SYMBOL_GPL(i2c_dw_probe_master); =20 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter"); MODULE_LICENSE("GPL"); diff --git a/drivers/i2c/busses/i2c-designware-slave.c b/drivers/i2c/busses= /i2c-designware-slave.c index 6eb16b7d75a6..1995be79544d 100644 --- a/drivers/i2c/busses/i2c-designware-slave.c +++ b/drivers/i2c/busses/i2c-designware-slave.c @@ -277,7 +277,6 @@ int i2c_dw_probe_slave(struct dw_i2c_dev *dev) =20 return ret; } -EXPORT_SYMBOL_GPL(i2c_dw_probe_slave); =20 MODULE_AUTHOR("Luis Oliveira "); MODULE_DESCRIPTION("Synopsys DesignWare I2C bus slave adapter"); --=20 2.50.1 From nobody Fri Dec 19 08:54:51 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 823C92EC0A7; Thu, 18 Dec 2025 15:15:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766070928; cv=none; b=I9ztXjhAU4eLOaer9rsIXem80Uk3dgrsjXDQN9oH6egb1ZOiNOw9cqkjE8ZkDlplOAfNTdkBrso2HrttGKT9mnVXDmA6vC/fXLIPu4uFb9rBLnbNQDYM4VQNQwwfx9V+FwUhRRmtbCLyGrTAERJwRDXGlA1ZfEIewW8C0yM0NqM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766070928; c=relaxed/simple; bh=LOFyzY+s40BW9OGVVI9S8t54tp2Xdd8z4HLtupMLEH0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QQfG/SGX0J9ZYp7EULD2XfSzj51UcucaP5SnVQQWH9+bWfu5CoQ7OnXyMzpaY7nqNtldA1TqW95D5XQUsgf0ESBYESOLh3S8YfSXTVYDlO/Jr+ihBM6f1waW7xWZqPQO+xyc44gLAviSMZ6DqpNhWPZ6AJPyS85uaQiDdc4qY0g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YC3Wcv+y; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YC3Wcv+y" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1766070921; x=1797606921; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LOFyzY+s40BW9OGVVI9S8t54tp2Xdd8z4HLtupMLEH0=; b=YC3Wcv+yNAQ6hIs4HgYLvMKwaI3cHxscwju5cHZI5+6UC4xQbje3jPof oyZr7hSDXlO2+LJFRddKsVViVlKCT5rU5aForELtmaWuwgajB97P/EyWI 2sRHEkgS0C27j/hJMYM/thmm2nviObHu9/+gOvSAxwEVISQxYZduHblWt e2/rcjw1NRYfWeBy4zjWRDUgn4jMmtirrpduvDPOa2iI/eBWXqNihdG46 H6w4RH9rOB5I1kO1MZmAMo0tY4y8sTYXCzA2bcJn/tYr735iVxUMkLzKv jd2ZJmSEA57RZP2faoUtvNi+sjLMCMhD8s6LaMpsd3lKczS5Fi4HB/tfb g==; X-CSE-ConnectionGUID: jIpi+1oNRlCBq19K+jCHcQ== X-CSE-MsgGUID: Nqr2DVj+RF2dpLLgtkAWaw== X-IronPort-AV: E=McAfee;i="6800,10657,11646"; a="78739540" X-IronPort-AV: E=Sophos;i="6.21,158,1763452800"; d="scan'208";a="78739540" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Dec 2025 07:15:18 -0800 X-CSE-ConnectionGUID: Cmny67/RS/mMPhmmKq5mYQ== X-CSE-MsgGUID: ztlFSxUXQ9OrDlaGTKmC2w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,158,1763452800"; d="scan'208";a="197857498" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa010.jf.intel.com with ESMTP; 18 Dec 2025 07:15:17 -0800 From: Heikki Krogerus To: Andi Shyti , Mika Westerberg Cc: Andy Shevchenko , Jan Dabros , Raag Jadav , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/6] i2c: designware: Combine some of the common functions Date: Thu, 18 Dec 2025 16:15:02 +0100 Message-ID: <20251218151509.361617-4-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251218151509.361617-1-heikki.krogerus@linux.intel.com> References: <20251218151509.361617-1-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The adapter can be registered just in the core instead of separately in the master and slave drivers. The same applies to the interrupt. Signed-off-by: Heikki Krogerus Acked-by: Mika Westerberg --- drivers/i2c/busses/i2c-designware-common.c | 108 +++++++++++++++++++-- drivers/i2c/busses/i2c-designware-core.h | 11 ++- drivers/i2c/busses/i2c-designware-master.c | 97 +++--------------- drivers/i2c/busses/i2c-designware-slave.c | 53 ++-------- 4 files changed, 126 insertions(+), 143 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busse= s/i2c-designware-common.c index 5b1e8f74c4ac..1823e4b71004 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -131,7 +131,7 @@ static int dw_reg_write_word(void *context, unsigned in= t reg, unsigned int val) * * Return: 0 on success, or negative errno otherwise. */ -int i2c_dw_init_regmap(struct dw_i2c_dev *dev) +static int i2c_dw_init_regmap(struct dw_i2c_dev *dev) { struct regmap_config map_cfg =3D { .reg_bits =3D 32, @@ -457,7 +457,7 @@ u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned in= t reg, u32 ic_clk, return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) - 1 + offs= et; } =20 -int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev) +static int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev) { unsigned int reg; int ret; @@ -672,7 +672,7 @@ int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) return -EIO; } =20 -int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev) +static int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev) { u32 tx_fifo_depth, rx_fifo_depth; unsigned int param; @@ -741,19 +741,113 @@ void i2c_dw_disable(struct dw_i2c_dev *dev) } EXPORT_SYMBOL_GPL(i2c_dw_disable); =20 +static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) +{ + struct dw_i2c_dev *dev =3D dev_id; + + if (dev->mode =3D=3D DW_IC_SLAVE) + return i2c_dw_isr_slave(dev); + + return i2c_dw_isr_master(dev); +} + +static const struct i2c_algorithm i2c_dw_algo =3D { + .xfer =3D i2c_dw_xfer, + .functionality =3D i2c_dw_func, +#if IS_ENABLED(CONFIG_I2C_SLAVE) + .reg_slave =3D i2c_dw_reg_slave, + .unreg_slave =3D i2c_dw_unreg_slave, +#endif +}; + +static const struct i2c_adapter_quirks i2c_dw_quirks =3D { + .flags =3D I2C_AQ_NO_ZERO_LEN, +}; + int i2c_dw_probe(struct dw_i2c_dev *dev) { + struct i2c_adapter *adap =3D &dev->adapter; + unsigned long irq_flags; + int ret; + device_set_node(&dev->adapter.dev, dev_fwnode(dev->dev)); =20 + ret =3D i2c_dw_init_regmap(dev); + if (ret) + return ret; + + ret =3D i2c_dw_set_sda_hold(dev); + if (ret) + return ret; + + ret =3D i2c_dw_set_fifo_size(dev); + if (ret) + return ret; + switch (dev->mode) { case DW_IC_SLAVE: - return i2c_dw_probe_slave(dev); + ret =3D i2c_dw_probe_slave(dev); + break; case DW_IC_MASTER: - return i2c_dw_probe_master(dev); + ret =3D i2c_dw_probe_master(dev); + break; default: - dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode); - return -EINVAL; + ret =3D -EINVAL; + break; } + if (ret) + return ret; + + ret =3D dev->init(dev); + if (ret) + return ret; + + if (!adap->name[0]) + strscpy(adap->name, "Synopsys DesignWare I2C adapter"); + + adap->retries =3D 3; + adap->algo =3D &i2c_dw_algo; + adap->quirks =3D &i2c_dw_quirks; + adap->dev.parent =3D dev->dev; + i2c_set_adapdata(adap, dev); + + /* + * REVISIT: The mode check may not be necessary. + * For now keeping the flags as they were originally. + */ + if (dev->mode =3D=3D DW_IC_SLAVE) + irq_flags =3D IRQF_SHARED; + else if (dev->flags & ACCESS_NO_IRQ_SUSPEND) + irq_flags =3D IRQF_NO_SUSPEND; + else + irq_flags =3D IRQF_SHARED | IRQF_COND_SUSPEND; + + ret =3D i2c_dw_acquire_lock(dev); + if (ret) + return ret; + + __i2c_dw_write_intr_mask(dev, 0); + i2c_dw_release_lock(dev); + + if (!(dev->flags & ACCESS_POLLING)) { + ret =3D devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, + irq_flags, dev_name(dev->dev), dev); + if (ret) + return ret; + } + + /* + * Increment PM usage count during adapter registration in order to + * avoid possible spurious runtime suspend when adapter device is + * registered to the device core and immediate resume in case bus has + * registered I2C slaves that do I2C transfers in their probe. + */ + ACQUIRE(pm_runtime_noresume, pm)(dev->dev); + ret =3D ACQUIRE_ERR(pm_runtime_noresume, &pm); + if (ret) + return ret; + + return i2c_add_numbered_adapter(adap); } EXPORT_SYMBOL_GPL(i2c_dw_probe); =20 diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/= i2c-designware-core.h index 2a7decc24931..0f58c4b50377 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -333,20 +334,18 @@ struct i2c_dw_semaphore_callbacks { int (*probe)(struct dw_i2c_dev *dev); }; =20 -int i2c_dw_init_regmap(struct dw_i2c_dev *dev); u32 i2c_dw_scl_hcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, u32 tSYMBOL, u32 tf, int offset); u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, u32 tLOW, u32 tf, int offset); -int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev); u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev); int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare); int i2c_dw_acquire_lock(struct dw_i2c_dev *dev); void i2c_dw_release_lock(struct dw_i2c_dev *dev); int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev); int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev); -int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev); u32 i2c_dw_func(struct i2c_adapter *adap); +irqreturn_t i2c_dw_isr_master(struct dw_i2c_dev *dev); =20 extern const struct dev_pm_ops i2c_dw_dev_pm_ops; =20 @@ -386,12 +385,18 @@ void i2c_dw_disable(struct dw_i2c_dev *dev); extern void i2c_dw_configure_master(struct dw_i2c_dev *dev); extern int i2c_dw_probe_master(struct dw_i2c_dev *dev); =20 +int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num); + #if IS_ENABLED(CONFIG_I2C_SLAVE) extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev); extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev); +irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev); +int i2c_dw_reg_slave(struct i2c_client *client); +int i2c_dw_unreg_slave(struct i2c_client *client); #else static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { } static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EIN= VAL; } +static inline irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev) { retur= n IRQ_NONE; } #endif =20 static inline void i2c_dw_configure(struct dw_i2c_dev *dev) diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busse= s/i2c-designware-master.c index 15b3a46f0132..91540a4520a3 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -191,10 +191,6 @@ static int i2c_dw_set_timings_master(struct dw_i2c_dev= *dev) dev->hs_hcnt, dev->hs_lcnt); } =20 - ret =3D i2c_dw_set_sda_hold(dev); - if (ret) - return ret; - dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)= ); return 0; } @@ -353,9 +349,8 @@ static int i2c_dw_status(struct dw_i2c_dev *dev) * Initiate and continue master read/write transaction with polling * based transfer routine afterward write messages into the Tx buffer. */ -static int amd_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg = *msgs, int num_msgs) +static int amd_i2c_dw_xfer_quirk(struct dw_i2c_dev *dev, struct i2c_msg *m= sgs, int num_msgs) { - struct dw_i2c_dev *dev =3D i2c_get_adapdata(adap); int msg_wrt_idx, msg_itr_lmt, buf_len, data_idx; int cmd =3D 0, status; u8 *tx_buf; @@ -752,9 +747,8 @@ static void i2c_dw_process_transfer(struct dw_i2c_dev *= dev, unsigned int stat) * Interrupt service routine. This gets called whenever an I2C master inte= rrupt * occurs. */ -static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) +irqreturn_t i2c_dw_isr_master(struct dw_i2c_dev *dev) { - struct dw_i2c_dev *dev =3D dev_id; unsigned int stat, enabled; =20 regmap_read(dev->map, DW_IC_ENABLE, &enabled); @@ -815,9 +809,8 @@ static int i2c_dw_wait_transfer(struct dw_i2c_dev *dev) * Prepare controller for a transaction and call i2c_dw_xfer_msg. */ static int -i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) +i2c_dw_xfer_common(struct dw_i2c_dev *dev, struct i2c_msg msgs[], int num) { - struct dw_i2c_dev *dev =3D i2c_get_adapdata(adap); int ret; =20 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); @@ -908,19 +901,15 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg = msgs[], int num) return ret; } =20 -static const struct i2c_algorithm i2c_dw_algo =3D { - .xfer =3D i2c_dw_xfer, - .functionality =3D i2c_dw_func, -}; +int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +{ + struct dw_i2c_dev *dev =3D i2c_get_adapdata(adap); =20 -static const struct i2c_algorithm amd_i2c_dw_algo =3D { - .xfer =3D amd_i2c_dw_xfer_quirk, - .functionality =3D i2c_dw_func, -}; + if ((dev->flags & MODEL_MASK) =3D=3D MODEL_AMD_NAVI_GPU) + return amd_i2c_dw_xfer_quirk(dev, msgs, num); =20 -static const struct i2c_adapter_quirks i2c_dw_quirks =3D { - .flags =3D I2C_AQ_NO_ZERO_LEN, -}; + return i2c_dw_xfer_common(dev, msgs, num); +} =20 void i2c_dw_configure_master(struct dw_i2c_dev *dev) { @@ -1005,8 +994,6 @@ static int i2c_dw_init_recovery_info(struct dw_i2c_dev= *dev) =20 int i2c_dw_probe_master(struct dw_i2c_dev *dev) { - struct i2c_adapter *adap =3D &dev->adapter; - unsigned long irq_flags; unsigned int ic_con; int ret; =20 @@ -1014,18 +1001,10 @@ int i2c_dw_probe_master(struct dw_i2c_dev *dev) =20 dev->init =3D i2c_dw_init_master; =20 - ret =3D i2c_dw_init_regmap(dev); - if (ret) - return ret; - ret =3D i2c_dw_set_timings_master(dev); if (ret) return ret; =20 - ret =3D i2c_dw_set_fifo_size(dev); - if (ret) - return ret; - /* Lock the bus for accessing DW_IC_CON */ ret =3D i2c_dw_acquire_lock(dev); if (ret) @@ -1045,61 +1024,7 @@ int i2c_dw_probe_master(struct dw_i2c_dev *dev) if (ic_con & DW_IC_CON_BUS_CLEAR_CTRL) dev->master_cfg |=3D DW_IC_CON_BUS_CLEAR_CTRL; =20 - ret =3D dev->init(dev); - if (ret) - return ret; - - if (!adap->name[0]) - scnprintf(adap->name, sizeof(adap->name), - "Synopsys DesignWare I2C adapter"); - adap->retries =3D 3; - if ((dev->flags & MODEL_MASK) =3D=3D MODEL_AMD_NAVI_GPU) - adap->algo =3D &amd_i2c_dw_algo; - else - adap->algo =3D &i2c_dw_algo; - adap->quirks =3D &i2c_dw_quirks; - adap->dev.parent =3D dev->dev; - i2c_set_adapdata(adap, dev); - - if (dev->flags & ACCESS_NO_IRQ_SUSPEND) { - irq_flags =3D IRQF_NO_SUSPEND; - } else { - irq_flags =3D IRQF_SHARED | IRQF_COND_SUSPEND; - } - - ret =3D i2c_dw_acquire_lock(dev); - if (ret) - return ret; - - __i2c_dw_write_intr_mask(dev, 0); - i2c_dw_release_lock(dev); - - if (!(dev->flags & ACCESS_POLLING)) { - ret =3D devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, - irq_flags, dev_name(dev->dev), dev); - if (ret) - return dev_err_probe(dev->dev, ret, - "failure requesting irq %i: %d\n", - dev->irq, ret); - } - - ret =3D i2c_dw_init_recovery_info(dev); - if (ret) - return ret; - - /* - * Increment PM usage count during adapter registration in order to - * avoid possible spurious runtime suspend when adapter device is - * registered to the device core and immediate resume in case bus has - * registered I2C slaves that do I2C transfers in their probe. - */ - pm_runtime_get_noresume(dev->dev); - ret =3D i2c_add_numbered_adapter(adap); - if (ret) - dev_err(dev->dev, "failure adding adapter: %d\n", ret); - pm_runtime_put_noidle(dev->dev); - - return ret; + return i2c_dw_init_recovery_info(dev); } =20 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter"); diff --git a/drivers/i2c/busses/i2c-designware-slave.c b/drivers/i2c/busses= /i2c-designware-slave.c index 1995be79544d..c0baf53e97d8 100644 --- a/drivers/i2c/busses/i2c-designware-slave.c +++ b/drivers/i2c/busses/i2c-designware-slave.c @@ -63,7 +63,7 @@ static int i2c_dw_init_slave(struct dw_i2c_dev *dev) return 0; } =20 -static int i2c_dw_reg_slave(struct i2c_client *slave) +int i2c_dw_reg_slave(struct i2c_client *slave) { struct dw_i2c_dev *dev =3D i2c_get_adapdata(slave->adapter); =20 @@ -88,7 +88,7 @@ static int i2c_dw_reg_slave(struct i2c_client *slave) return 0; } =20 -static int i2c_dw_unreg_slave(struct i2c_client *slave) +int i2c_dw_unreg_slave(struct i2c_client *slave) { struct dw_i2c_dev *dev =3D i2c_get_adapdata(slave->adapter); =20 @@ -152,9 +152,8 @@ static u32 i2c_dw_read_clear_intrbits_slave(struct dw_i= 2c_dev *dev) * Interrupt service routine. This gets called whenever an I2C slave inter= rupt * occurs. */ -static irqreturn_t i2c_dw_isr_slave(int this_irq, void *dev_id) +irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev) { - struct dw_i2c_dev *dev =3D dev_id; unsigned int raw_stat, stat, enabled, tmp; u8 val =3D 0, slave_activity; =20 @@ -217,12 +216,6 @@ static irqreturn_t i2c_dw_isr_slave(int this_irq, void= *dev_id) return IRQ_HANDLED; } =20 -static const struct i2c_algorithm i2c_dw_algo =3D { - .functionality =3D i2c_dw_func, - .reg_slave =3D i2c_dw_reg_slave, - .unreg_slave =3D i2c_dw_unreg_slave, -}; - void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { dev->functionality =3D I2C_FUNC_SLAVE; @@ -236,46 +229,12 @@ EXPORT_SYMBOL_GPL(i2c_dw_configure_slave); =20 int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { - struct i2c_adapter *adap =3D &dev->adapter; - int ret; + if (dev->flags & ACCESS_POLLING) + return -EOPNOTSUPP; =20 dev->init =3D i2c_dw_init_slave; =20 - ret =3D i2c_dw_init_regmap(dev); - if (ret) - return ret; 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X-CSE-ConnectionGUID: bX/k/k1kQ/mBIhfSjA+L1Q== X-CSE-MsgGUID: 1Z8FZIqaSFy8YL/ZPZjpkw== X-IronPort-AV: E=McAfee;i="6800,10657,11646"; a="78739549" X-IronPort-AV: E=Sophos;i="6.21,158,1763452800"; d="scan'208";a="78739549" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Dec 2025 07:15:21 -0800 X-CSE-ConnectionGUID: tFHgD5oSQrOwcWUe/bM1VA== X-CSE-MsgGUID: ve0SfNXtQYmEONRwIkaQVw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,158,1763452800"; d="scan'208";a="197857504" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa010.jf.intel.com with ESMTP; 18 Dec 2025 07:15:19 -0800 From: Heikki Krogerus To: Andi Shyti , Mika Westerberg Cc: Andy Shevchenko , Jan Dabros , Raag Jadav , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/6] i2c: designware: Combine the init functions Date: Thu, 18 Dec 2025 16:15:03 +0100 Message-ID: <20251218151509.361617-5-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251218151509.361617-1-heikki.krogerus@linux.intel.com> References: <20251218151509.361617-1-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Providing a single function for controller initialisation. The controller initialisation has the same steps for master and slave modes, except the timing parameters are only needed in master mode. Signed-off-by: Heikki Krogerus Acked-by: Mika Westerberg --- drivers/i2c/busses/i2c-designware-amdisp.c | 4 +- drivers/i2c/busses/i2c-designware-common.c | 81 +++++++++++++++++++++- drivers/i2c/busses/i2c-designware-core.h | 3 +- drivers/i2c/busses/i2c-designware-master.c | 70 +------------------ drivers/i2c/busses/i2c-designware-slave.c | 44 ------------ 5 files changed, 85 insertions(+), 117 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-amdisp.c b/drivers/i2c/busse= s/i2c-designware-amdisp.c index 450793d5f839..ec9259dd2a4f 100644 --- a/drivers/i2c/busses/i2c-designware-amdisp.c +++ b/drivers/i2c/busses/i2c-designware-amdisp.c @@ -163,8 +163,8 @@ static int amd_isp_dw_i2c_plat_runtime_resume(struct de= vice *dev) =20 if (!i_dev->shared_with_punit) i2c_dw_prepare_clk(i_dev, true); - if (i_dev->init) - i_dev->init(i_dev); + + i2c_dw_init(i_dev); =20 return 0; } diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busse= s/i2c-designware-common.c index 1823e4b71004..8e99549b37a3 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -358,6 +358,83 @@ static inline u32 i2c_dw_acpi_round_bus_speed(struct d= evice *device) { return 0; =20 #endif /* CONFIG_ACPI */ =20 +static void i2c_dw_configure_mode(struct dw_i2c_dev *dev) +{ + switch (dev->mode) { + case DW_IC_MASTER: + regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); + regmap_write(dev->map, DW_IC_RX_TL, 0); + regmap_write(dev->map, DW_IC_CON, dev->master_cfg); + break; + case DW_IC_SLAVE: + regmap_write(dev->map, DW_IC_TX_TL, 0); + regmap_write(dev->map, DW_IC_RX_TL, 0); + regmap_write(dev->map, DW_IC_CON, dev->slave_cfg); + regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK); + break; + default: + return; + } +} + +static void i2c_dw_write_timings(struct dw_i2c_dev *dev) +{ + /* Write standard speed timing parameters */ + regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); + regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); + + /* Write fast mode/fast mode plus timing parameters */ + regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); + regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); + + /* Write high speed timing parameters if supported */ + if (dev->hs_hcnt && dev->hs_lcnt) { + regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); + regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); + } +} + +/** + * i2c_dw_init() - Initialize the DesignWare I2C hardware + * @dev: device private data + * + * This functions configures and enables the DesigWare I2C hardware. + * + * Return: 0 on success, or negative errno otherwise. + */ +int i2c_dw_init(struct dw_i2c_dev *dev) +{ + int ret; + + ret =3D i2c_dw_acquire_lock(dev); + if (ret) + return ret; + + /* Disable the adapter */ + __i2c_dw_disable(dev); + + /* + * Mask SMBus interrupts to block storms from broken + * firmware that leaves IC_SMBUS=3D1; the handler never + * services them. + */ + regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0); + + if (dev->mode =3D=3D DW_IC_MASTER) + i2c_dw_write_timings(dev); + + /* Write SDA hold time if supported */ + if (dev->sda_hold_time) + regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); + + i2c_dw_configure_mode(dev); + + i2c_dw_release_lock(dev); + + return 0; +} +EXPORT_SYMBOL_GPL(i2c_dw_init); + static void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev) { u32 acpi_speed =3D i2c_dw_acpi_round_bus_speed(dev->dev); @@ -798,7 +875,7 @@ int i2c_dw_probe(struct dw_i2c_dev *dev) if (ret) return ret; =20 - ret =3D dev->init(dev); + ret =3D i2c_dw_init(dev); if (ret) return ret; =20 @@ -891,7 +968,7 @@ static int i2c_dw_runtime_resume(struct device *device) if (!dev->shared_with_punit) i2c_dw_prepare_clk(dev, true); =20 - dev->init(dev); + i2c_dw_init(dev); =20 return 0; } diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/= i2c-designware-core.h index 0f58c4b50377..82465b134c34 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -240,7 +240,6 @@ struct reset_control; * @semaphore_idx: Index of table with semaphore type attached to the bus.= It's * -1 if there is no semaphore. * @shared_with_punit: true if this bus is shared with the SoC's PUNIT - * @init: function to initialize the I2C hardware * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE * @rinfo: I=C2=B2C GPIO recovery information @@ -301,7 +300,6 @@ struct dw_i2c_dev { void (*release_lock)(void); int semaphore_idx; bool shared_with_punit; - int (*init)(struct dw_i2c_dev *dev); int (*set_sda_hold_time)(struct dw_i2c_dev *dev); int mode; struct i2c_bus_recovery_info rinfo; @@ -408,6 +406,7 @@ static inline void i2c_dw_configure(struct dw_i2c_dev *= dev) } =20 int i2c_dw_probe(struct dw_i2c_dev *dev); +int i2c_dw_init(struct dw_i2c_dev *dev); =20 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL) int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev); diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busse= s/i2c-designware-master.c index 91540a4520a3..33432bbaec1f 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -31,16 +31,6 @@ #define AMD_TIMEOUT_MAX_US 250 #define AMD_MASTERCFG_MASK GENMASK(15, 0) =20 -static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev) -{ - /* Configure Tx/Rx FIFO threshold levels */ - regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); - regmap_write(dev->map, DW_IC_RX_TL, 0); - - /* Configure the I2C master */ - regmap_write(dev->map, DW_IC_CON, dev->master_cfg); -} - static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev) { unsigned int comp_param1; @@ -195,58 +185,6 @@ static int i2c_dw_set_timings_master(struct dw_i2c_dev= *dev) return 0; } =20 -/** - * i2c_dw_init_master() - Initialize the DesignWare I2C master hardware - * @dev: device private data - * - * This functions configures and enables the I2C master. - * This function is called during I2C init function, and in case of timeou= t at - * run time. - * - * Return: 0 on success, or negative errno otherwise. - */ -static int i2c_dw_init_master(struct dw_i2c_dev *dev) -{ - int ret; - - ret =3D i2c_dw_acquire_lock(dev); - if (ret) - return ret; - - /* Disable the adapter */ - __i2c_dw_disable(dev); - - /* - * Mask SMBus interrupts to block storms from broken - * firmware that leaves IC_SMBUS=3D1; the handler never - * services them. - */ - regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0); - - /* Write standard speed timing parameters */ - regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); - regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); - - /* Write fast mode/fast mode plus timing parameters */ - regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); - regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); - - /* Write high speed timing parameters if supported */ - if (dev->hs_hcnt && dev->hs_lcnt) { - regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); - regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); - } - - /* Write SDA hold time if supported */ - if (dev->sda_hold_time) - regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); - - i2c_dw_configure_fifo_master(dev); - i2c_dw_release_lock(dev); - - return 0; -} - static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) { struct i2c_msg *msgs =3D dev->msgs; @@ -843,9 +781,9 @@ i2c_dw_xfer_common(struct dw_i2c_dev *dev, struct i2c_m= sg msgs[], int num) ret =3D i2c_dw_wait_transfer(dev); if (ret) { dev_err(dev->dev, "controller timed out\n"); - /* i2c_dw_init_master() implicitly disables the adapter */ + /* i2c_dw_init() implicitly disables the adapter */ i2c_recover_bus(&dev->adapter); - i2c_dw_init_master(dev); + i2c_dw_init(dev); goto done; } =20 @@ -950,7 +888,7 @@ static void i2c_dw_unprepare_recovery(struct i2c_adapte= r *adap) =20 i2c_dw_prepare_clk(dev, true); reset_control_deassert(dev->rst); - i2c_dw_init_master(dev); + i2c_dw_init(dev); } =20 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev) @@ -999,8 +937,6 @@ int i2c_dw_probe_master(struct dw_i2c_dev *dev) =20 init_completion(&dev->cmd_complete); =20 - dev->init =3D i2c_dw_init_master; - ret =3D i2c_dw_set_timings_master(dev); if (ret) return ret; diff --git a/drivers/i2c/busses/i2c-designware-slave.c b/drivers/i2c/busses= /i2c-designware-slave.c index c0baf53e97d8..9fc8faa33735 100644 --- a/drivers/i2c/busses/i2c-designware-slave.c +++ b/drivers/i2c/busses/i2c-designware-slave.c @@ -21,48 +21,6 @@ =20 #include "i2c-designware-core.h" =20 -static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev) -{ - /* Configure Tx/Rx FIFO threshold levels. */ - regmap_write(dev->map, DW_IC_TX_TL, 0); - regmap_write(dev->map, DW_IC_RX_TL, 0); - - /* Configure the I2C slave. */ - regmap_write(dev->map, DW_IC_CON, dev->slave_cfg); - regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK); -} - -/** - * i2c_dw_init_slave() - Initialize the DesignWare i2c slave hardware - * @dev: device private data - * - * This function configures and enables the I2C in slave mode. - * This function is called during I2C init function, and in case of timeou= t at - * run time. - * - * Return: 0 on success, or negative errno otherwise. - */ -static int i2c_dw_init_slave(struct dw_i2c_dev *dev) -{ - int ret; - - ret =3D i2c_dw_acquire_lock(dev); - if (ret) - return ret; - - /* Disable the adapter. */ - __i2c_dw_disable(dev); - - /* Write SDA hold time if supported */ - if (dev->sda_hold_time) - regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); - - i2c_dw_configure_fifo_slave(dev); - i2c_dw_release_lock(dev); - - return 0; -} - int i2c_dw_reg_slave(struct i2c_client *slave) { struct dw_i2c_dev *dev =3D i2c_get_adapdata(slave->adapter); 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18 Dec 2025 07:15:22 -0800 From: Heikki Krogerus To: Andi Shyti , Mika Westerberg Cc: Andy Shevchenko , Jan Dabros , Raag Jadav , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/6] i2c: designware: Enable mode swapping Date: Thu, 18 Dec 2025 16:15:04 +0100 Message-ID: <20251218151509.361617-6-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251218151509.361617-1-heikki.krogerus@linux.intel.com> References: <20251218151509.361617-1-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The DesignWare I2C can not be operated as I2C master and I2C slave simultaneously, but that does not actually mean master and slave modes can not be supported at the same time. It just means an explicit mode swap needs to be executed when the mode is changed. The DesignWare I2C documentation actually describes a couple of cases where the mode is excepted to be changed. The I2C master will now always be supported. Both modes are now always configured in i2c_dw_configure(), but the slave mode will continue to be available only when the Kconfig option I2C_SLAVE is enabled. The driver will now start in master mode and then swap to slave mode when a slave device is registered. After a slave device is registered, the controller is swapped to master mode when a transfer in master mode is started and then back to slave mode again after the transfer is completed. The DesignWare I2C can now be used with protocols such as MCTP (drivers/net/mctp/mctp-i2c.c) and IPMI (drivers/char/ipmi/) that require support for both I2C master and I2C slave. It is now also possible to support the SMBus Host Notification Protocol as I2C master if needed. Signed-off-by: Heikki Krogerus Acked-by: Mika Westerberg --- drivers/i2c/busses/i2c-designware-common.c | 50 +++++++++++++++------- drivers/i2c/busses/i2c-designware-core.h | 9 ++-- drivers/i2c/busses/i2c-designware-master.c | 6 ++- drivers/i2c/busses/i2c-designware-slave.c | 35 +++++++-------- 4 files changed, 57 insertions(+), 43 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busse= s/i2c-designware-common.c index 8e99549b37a3..aac7b1f4710f 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -358,21 +358,25 @@ static inline u32 i2c_dw_acpi_round_bus_speed(struct = device *device) { return 0; =20 #endif /* CONFIG_ACPI */ =20 -static void i2c_dw_configure_mode(struct dw_i2c_dev *dev) +static void i2c_dw_configure_mode(struct dw_i2c_dev *dev, int mode) { - switch (dev->mode) { + switch (mode) { case DW_IC_MASTER: regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); regmap_write(dev->map, DW_IC_RX_TL, 0); regmap_write(dev->map, DW_IC_CON, dev->master_cfg); break; case DW_IC_SLAVE: + dev->status =3D 0; regmap_write(dev->map, DW_IC_TX_TL, 0); regmap_write(dev->map, DW_IC_RX_TL, 0); regmap_write(dev->map, DW_IC_CON, dev->slave_cfg); + regmap_write(dev->map, DW_IC_SAR, dev->slave->addr); regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK); + __i2c_dw_enable(dev); break; default: + WARN(1, "Invalid mode %d\n", mode); return; } } @@ -394,6 +398,31 @@ static void i2c_dw_write_timings(struct dw_i2c_dev *de= v) } } =20 +/** + * i2c_dw_set_mode() - Select the controller mode of operation - master or= slave + * @dev: device private data + * @mode: I2C mode of operation + * + * Configures the controller to operate in @mode. This function needs to be + * called when ever a mode swap is required. + * + * Setting the slave mode does not have an effect before a slave device is + * registered. So before the slave device is registered, the controller is= kept + * in master mode regardless of @mode. + * + * The controller must be disabled before this function is called. + */ +void i2c_dw_set_mode(struct dw_i2c_dev *dev, int mode) +{ + if (mode =3D=3D DW_IC_SLAVE && !dev->slave) + mode =3D DW_IC_MASTER; + if (dev->mode =3D=3D mode) + return; + + i2c_dw_configure_mode(dev, mode); + dev->mode =3D mode; +} + /** * i2c_dw_init() - Initialize the DesignWare I2C hardware * @dev: device private data @@ -420,14 +449,13 @@ int i2c_dw_init(struct dw_i2c_dev *dev) */ regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0); =20 - if (dev->mode =3D=3D DW_IC_MASTER) - i2c_dw_write_timings(dev); + i2c_dw_write_timings(dev); =20 /* Write SDA hold time if supported */ if (dev->sda_hold_time) regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); =20 - i2c_dw_configure_mode(dev); + i2c_dw_configure_mode(dev, dev->mode); =20 i2c_dw_release_lock(dev); =20 @@ -861,17 +889,7 @@ int i2c_dw_probe(struct dw_i2c_dev *dev) if (ret) return ret; =20 - switch (dev->mode) { - case DW_IC_SLAVE: - ret =3D i2c_dw_probe_slave(dev); - break; - case DW_IC_MASTER: - ret =3D i2c_dw_probe_master(dev); - break; - default: - ret =3D -EINVAL; - break; - } + ret =3D i2c_dw_probe_master(dev); if (ret) return ret; =20 diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/= i2c-designware-core.h index 82465b134c34..5d783d585406 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -387,26 +387,23 @@ int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_= msg *msgs, int num); =20 #if IS_ENABLED(CONFIG_I2C_SLAVE) extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev); -extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev); irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev); int i2c_dw_reg_slave(struct i2c_client *client); int i2c_dw_unreg_slave(struct i2c_client *client); #else static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { } -static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EIN= VAL; } static inline irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev) { retur= n IRQ_NONE; } #endif =20 static inline void i2c_dw_configure(struct dw_i2c_dev *dev) { - if (i2c_detect_slave_mode(dev->dev)) - i2c_dw_configure_slave(dev); - else - i2c_dw_configure_master(dev); + i2c_dw_configure_slave(dev); + i2c_dw_configure_master(dev); } =20 int i2c_dw_probe(struct dw_i2c_dev *dev); int i2c_dw_init(struct dw_i2c_dev *dev); +void i2c_dw_set_mode(struct dw_i2c_dev *dev, int mode); =20 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL) int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev); diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busse= s/i2c-designware-master.c index 33432bbaec1f..ba2ee526ecc6 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -194,6 +194,8 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) /* Disable the adapter */ __i2c_dw_disable(dev); =20 + i2c_dw_set_mode(dev, DW_IC_MASTER); + /* If the slave address is ten bit address, enable 10BITADDR */ if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { ic_con =3D DW_IC_CON_10BITADDR_MASTER; @@ -831,6 +833,8 @@ i2c_dw_xfer_common(struct dw_i2c_dev *dev, struct i2c_m= sg msgs[], int num) ret =3D -EIO; =20 done: + i2c_dw_set_mode(dev, DW_IC_SLAVE); + i2c_dw_release_lock(dev); =20 done_nolock: @@ -853,7 +857,7 @@ void i2c_dw_configure_master(struct dw_i2c_dev *dev) { struct i2c_timings *t =3D &dev->timings; =20 - dev->functionality =3D I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; + dev->functionality |=3D I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; =20 dev->master_cfg =3D DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | DW_IC_CON_RESTART_EN; diff --git a/drivers/i2c/busses/i2c-designware-slave.c b/drivers/i2c/busses= /i2c-designware-slave.c index 9fc8faa33735..ad0d5fbfa6d5 100644 --- a/drivers/i2c/busses/i2c-designware-slave.c +++ b/drivers/i2c/busses/i2c-designware-slave.c @@ -24,24 +24,25 @@ int i2c_dw_reg_slave(struct i2c_client *slave) { struct dw_i2c_dev *dev =3D i2c_get_adapdata(slave->adapter); + int ret; =20 + if (!i2c_check_functionality(slave->adapter, I2C_FUNC_SLAVE)) + return -EOPNOTSUPP; if (dev->slave) return -EBUSY; if (slave->flags & I2C_CLIENT_TEN) return -EAFNOSUPPORT; - pm_runtime_get_sync(dev->dev); =20 - /* - * Set slave address in the IC_SAR register, - * the address to which the DW_apb_i2c responds. - */ + ret =3D i2c_dw_acquire_lock(dev); + if (ret) + return ret; + + pm_runtime_get_sync(dev->dev); __i2c_dw_disable_nowait(dev); - regmap_write(dev->map, DW_IC_SAR, slave->addr); dev->slave =3D slave; + i2c_dw_set_mode(dev, DW_IC_SLAVE); =20 - __i2c_dw_enable(dev); - - dev->status =3D 0; + i2c_dw_release_lock(dev); =20 return 0; } @@ -54,6 +55,7 @@ int i2c_dw_unreg_slave(struct i2c_client *slave) i2c_dw_disable(dev); synchronize_irq(dev->irq); dev->slave =3D NULL; + i2c_dw_set_mode(dev, DW_IC_MASTER); pm_runtime_put_sync_suspend(dev->dev); =20 return 0; @@ -176,23 +178,16 @@ irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev) =20 void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { - dev->functionality =3D I2C_FUNC_SLAVE; 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d="scan'208";a="78739562" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Dec 2025 07:15:25 -0800 X-CSE-ConnectionGUID: X+9nPRnLRxy047bHEcrcPQ== X-CSE-MsgGUID: QzIdjzu2SbikTLirXzpdyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,158,1763452800"; d="scan'208";a="197857520" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa010.jf.intel.com with ESMTP; 18 Dec 2025 07:15:24 -0800 From: Heikki Krogerus To: Andi Shyti , Mika Westerberg Cc: Andy Shevchenko , Jan Dabros , Raag Jadav , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/6] i2c: designware: Remove an unnecessary condition Date: Thu, 18 Dec 2025 16:15:05 +0100 Message-ID: <20251218151509.361617-7-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251218151509.361617-1-heikki.krogerus@linux.intel.com> References: <20251218151509.361617-1-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Writing also the high speed timing registers unconditionally. The reset value for these registers is 0, so this should always be safe. Suggested-by: Andy Shevchenko Signed-off-by: Heikki Krogerus Acked-by: Mika Westerberg --- drivers/i2c/busses/i2c-designware-common.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busse= s/i2c-designware-common.c index aac7b1f4710f..1981dbfa260f 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -391,11 +391,9 @@ static void i2c_dw_write_timings(struct dw_i2c_dev *de= v) regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); =20 - /* Write high speed timing parameters if supported */ - if (dev->hs_hcnt && dev->hs_lcnt) { - regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); - regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); - } + /* Write high speed timing parameters */ + regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); + regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); } =20 /** --=20 2.50.1