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[75.72.117.212]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8beeb5d6952sm186866985a.3.2025.12.18.07.12.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 07:12:47 -0800 (PST) From: Alex Elder To: dlan@gentoo.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, guodong@riscstar.com, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v7 5/5] riscv: dts: spacemit: PCIe and PHY-related updates Date: Thu, 18 Dec 2025 09:12:31 -0600 Message-ID: <20251218151235.454997-6-elder@riscstar.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251218151235.454997-1-elder@riscstar.com> References: <20251218151235.454997-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define PCIe and PHY-related Device Tree nodes for the SpacemiT K1 SoC. Enable the combo PHY and the two PCIe-only PHYs on the Banana Pi BPI-F3 board. The combo PHY is used for USB on this board, and that will be enabled when USB 3 support is accepted. The combo PHY must perform a calibration step to determine configuration values used by the PCIe-only PHYs. As a result, it must be enabled if either of the other two PHYs is enabled. Signed-off-by: Alex Elder Reviewed-by: Yixun Lan --- .../boot/dts/spacemit/k1-bananapi-f3.dts | 36 ++++ arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 33 ++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 176 ++++++++++++++++++ 3 files changed, 245 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/b= oot/dts/spacemit/k1-bananapi-f3.dts index 71f48454ba47c..3f10efd925dc8 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -61,6 +61,12 @@ reg_vcc_4v: vcc-4v { }; }; =20 +&combo_phy { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_3_cfg>; + status =3D "okay"; +}; + &emmc { bus-width =3D <8>; mmc-hs400-1_8v; @@ -272,6 +278,36 @@ dldo7 { }; }; =20 +&pcie1_phy { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_3_cfg>; + status =3D "okay"; +}; + +&pcie1_port { + phys =3D <&pcie1_phy>; +}; + +&pcie1 { + vpcie3v3-supply =3D <&pcie_vcc_3v3>; + status =3D "okay"; +}; + +&pcie2_phy { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_4_cfg>; + status =3D "okay"; +}; + +&pcie2_port { + phys =3D <&pcie2_phy>; +}; + +&pcie2 { + vpcie3v3-supply =3D <&pcie_vcc_3v3>; + status =3D "okay"; +}; + &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0_2_cfg>; diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot= /dts/spacemit/k1-pinctrl.dtsi index e922e05ff856d..b13dcb10f4d66 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -530,6 +530,39 @@ uart9-2-pins { }; }; =20 + pcie0_3_cfg: pcie0-3-cfg { + pcie0-3-pins { + pinmux =3D , /* PERST# */ + , /* WAKE# */ + ; /* CLKREQ# */ + + bias-pull-up =3D <0>; + drive-strength =3D <21>; + }; + }; + + pcie1_3_cfg: pcie1-3-cfg { + pcie1-3-pins { + pinmux =3D , /* PERST# */ + , /* WAKE# */ + ; /* CLKREQ# */ + + bias-pull-up =3D <0>; + drive-strength =3D <21>; + }; + }; + + pcie2_4_cfg: pcie2-4-cfg { + pcie2-4-pins { + pinmux =3D , /* PERST# */ + , /* WAKE# */ + ; /* CLKREQ# */ + + bias-pull-up =3D <0>; + drive-strength =3D <21>; + }; + }; + pwm14_1_cfg: pwm14-1-cfg { pwm14-1-pins { pinmux =3D ; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index 7818ca4979b6a..86d1db14e2ee4 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -4,6 +4,7 @@ */ =20 #include +#include =20 /dts-v1/; / { @@ -423,6 +424,52 @@ i2c5: i2c@d4013800 { status =3D "disabled"; }; =20 + combo_phy: phy@c0b10000 { + compatible =3D "spacemit,k1-combo-phy"; + reg =3D <0x0 0xc0b10000 0x0 0x1000>; + clocks =3D <&vctcxo_24m>, + <&syscon_apmu CLK_PCIE0_DBI>, + <&syscon_apmu CLK_PCIE0_MASTER>, + <&syscon_apmu CLK_PCIE0_SLAVE>; + clock-names =3D "refclk", + "dbi", + "mstr", + "slv"; + resets =3D <&syscon_apmu RESET_PCIE0_GLOBAL>, + <&syscon_apmu RESET_PCIE0_DBI>, + <&syscon_apmu RESET_PCIE0_MASTER>, + <&syscon_apmu RESET_PCIE0_SLAVE>; + reset-names =3D "phy", + "dbi", + "mstr", + "slv"; + #phy-cells =3D <1>; + spacemit,apmu =3D <&syscon_apmu>; + status =3D "disabled"; + }; + + pcie1_phy: phy@c0c10000 { + compatible =3D "spacemit,k1-pcie-phy"; + reg =3D <0x0 0xc0c10000 0x0 0x1000>; + clocks =3D <&vctcxo_24m>; + clock-names =3D "refclk"; + resets =3D <&syscon_apmu RESET_PCIE1_GLOBAL>; + reset-names =3D "phy"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + pcie2_phy: phy@c0d10000 { + compatible =3D "spacemit,k1-pcie-phy"; + reg =3D <0x0 0xc0d10000 0x0 0x1000>; + clocks =3D <&vctcxo_24m>; + clock-names =3D "refclk"; + resets =3D <&syscon_apmu RESET_PCIE2_GLOBAL>; + reset-names =3D "phy"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + syscon_apbc: system-controller@d4015000 { compatible =3D "spacemit,k1-syscon-apbc"; reg =3D <0x0 0xd4015000 0x0 0x1000>; @@ -969,6 +1016,135 @@ pcie-bus { #size-cells =3D <2>; dma-ranges =3D <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; + pcie0: pcie@ca000000 { + device_type =3D "pci"; + compatible =3D "spacemit,k1-pcie"; + reg =3D <0x0 0xca000000 0x0 0x00001000>, + <0x0 0xca300000 0x0 0x0001ff24>, + <0x0 0x8f000000 0x0 0x00002000>, + <0x0 0xc0b20000 0x0 0x00001000>; + reg-names =3D "dbi", + "atu", + "config", + "link"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, + <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>; + interrupts =3D <141>; + interrupt-names =3D "msi"; + clocks =3D <&syscon_apmu CLK_PCIE0_DBI>, + <&syscon_apmu CLK_PCIE0_MASTER>, + <&syscon_apmu CLK_PCIE0_SLAVE>; + clock-names =3D "dbi", + "mstr", + "slv"; + resets =3D <&syscon_apmu RESET_PCIE0_DBI>, + <&syscon_apmu RESET_PCIE0_MASTER>, + <&syscon_apmu RESET_PCIE0_SLAVE>; + reset-names =3D "dbi", + "mstr", + "slv"; + spacemit,apmu =3D <&syscon_apmu 0x03cc>; + status =3D "disabled"; + + pcie0_port: pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie1: pcie@ca400000 { + device_type =3D "pci"; + compatible =3D "spacemit,k1-pcie"; + reg =3D <0x0 0xca400000 0x0 0x00001000>, + <0x0 0xca700000 0x0 0x0001ff24>, + <0x0 0x9f000000 0x0 0x00002000>, + <0x0 0xc0c20000 0x0 0x00001000>; + reg-names =3D "dbi", + "atu", + "config", + "link"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, + <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>; + interrupts =3D <142>; + interrupt-names =3D "msi"; + clocks =3D <&syscon_apmu CLK_PCIE1_DBI>, + <&syscon_apmu CLK_PCIE1_MASTER>, + <&syscon_apmu CLK_PCIE1_SLAVE>; + clock-names =3D "dbi", + "mstr", + "slv"; + resets =3D <&syscon_apmu RESET_PCIE1_DBI>, + <&syscon_apmu RESET_PCIE1_MASTER>, + <&syscon_apmu RESET_PCIE1_SLAVE>; + reset-names =3D "dbi", + "mstr", + "slv"; + spacemit,apmu =3D <&syscon_apmu 0x3d4>; + status =3D "disabled"; + + pcie1_port: pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie2: pcie@ca800000 { + device_type =3D "pci"; + compatible =3D "spacemit,k1-pcie"; + reg =3D <0x0 0xca800000 0x0 0x00001000>, + <0x0 0xcab00000 0x0 0x0001ff24>, + <0x0 0xb7000000 0x0 0x00002000>, + <0x0 0xc0d20000 0x0 0x00001000>; + reg-names =3D "dbi", + "atu", + "config", + "link"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, + <0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>, + <0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>; + interrupts =3D <143>; + interrupt-names =3D "msi"; + clocks =3D <&syscon_apmu CLK_PCIE2_DBI>, + <&syscon_apmu CLK_PCIE2_MASTER>, + <&syscon_apmu CLK_PCIE2_SLAVE>; + clock-names =3D "dbi", + "mstr", + "slv"; + resets =3D <&syscon_apmu RESET_PCIE2_DBI>, + <&syscon_apmu RESET_PCIE2_MASTER>, + <&syscon_apmu RESET_PCIE2_SLAVE>; + reset-names =3D "dbi", + "mstr", + "slv"; + spacemit,apmu =3D <&syscon_apmu 0x3dc>; + status =3D "disabled"; + + pcie2_port: pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; }; =20 storage-bus { --=20 2.48.1