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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Or Har-Toov , "Maher Sanalla" Subject: [PATCH mlx5-next 01/10] net/mlx5: Add max_tx_speed and its CAP bit to IFC Date: Thu, 18 Dec 2025 17:57:58 +0200 Message-ID: <20251218-vf-bw-lag-mode-v1-1-7d8ed4368bea@nvidia.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> References: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766069544; l=1802; i=edwards@nvidia.com; s=20251029; h=from:subject:message-id; bh=iH5nuDomUtx+sOM/Yu+qaoqkSr0LjVit6hNEIXO0yVI=; b=DZaNilmLJ8CwUNA9a65h8Rm2hpGsmG+Sv7Bc7wWR3gdXZ1dDWbN/9GJgfocW6aSZSrnApfxBE Ih4oYBv1FH+AHmOSAPJa6Z5Kdt1f5BT4DXHg8sHelQ1+AKeT1YZTRpq X-Developer-Key: i=edwards@nvidia.com; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 15:58:29.2015 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 24ffac22-64c0-477e-210a-08de3e4e496f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5923 From: Or Har-Toov Introduce the max_tx_speed field to the query and modify_vport_state structures. Add the esw_vport_state_max_tx_speed capability bit, indicating the firmware support modifying the max_tx_speed field via the MODIFY_VPORT_STATE command. Signed-off-by: Or Har-Toov Reviewed-by: Maher Sanalla Reviewed-by: Mark Bloch Signed-off-by: Edward Srouji --- include/linux/mlx5/mlx5_ifc.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index e9dcd4bf355d..e844cfa4fe0a 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1071,7 +1071,9 @@ struct mlx5_ifc_e_switch_cap_bits { u8 esw_shared_ingress_acl[0x1]; u8 esw_uplink_ingress_acl[0x1]; u8 root_ft_on_other_esw[0x1]; - u8 reserved_at_a[0xf]; + u8 reserved_at_a[0x1]; + u8 esw_vport_state_max_tx_speed[0x1]; + u8 reserved_at_c[0xd]; u8 esw_functions_changed[0x1]; u8 reserved_at_1a[0x1]; u8 ecpf_vport_exists[0x1]; @@ -5445,7 +5447,8 @@ struct mlx5_ifc_query_vport_state_out_bits { =20 u8 reserved_at_40[0x20]; =20 - u8 reserved_at_60[0x18]; + u8 max_tx_speed[0x10]; + u8 reserved_at_70[0x8]; u8 admin_state[0x4]; u8 state[0x4]; }; @@ -7778,7 +7781,7 @@ struct mlx5_ifc_modify_vport_state_in_bits { u8 reserved_at_41[0xf]; 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Thu, 18 Dec 2025 07:58:06 -0800 From: Edward Srouji To: , Leon Romanovsky , Saeed Mahameed , Tariq Toukan , Mark Bloch , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Or Har-Toov , "Maher Sanalla" Subject: [PATCH mlx5-next 02/10] net/mlx5: Propagate LAG effective max_tx_speed to vports Date: Thu, 18 Dec 2025 17:58:05 +0200 Message-ID: <20251218-vf-bw-lag-mode-v1-2-7d8ed4368bea@nvidia.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> References: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766069544; l=12727; i=edwards@nvidia.com; s=20251029; h=from:subject:message-id; bh=Awua+wWYDe386DrscYUnPCv6WF2teNaNDM2UWKYe7VM=; b=CEOVh9ELN31riAsdjOu98m3WYy4j6fN0ygCVYiBQ5FkK4su+SlowVQduADRf/ABVqxkEq0JHL kJEIye4Y4PLDbFv0HM4WAYZJ7njuehBx4U648T7+eQhXRmP8j7j/9gc X-Developer-Key: i=edwards@nvidia.com; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 15:58:29.3222 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b127398a-ef91-42e6-5fc3-08de3e4e4978 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE32.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9176 From: Or Har-Toov Currently, vports report only their parent's uplink speed, which in LAG setups does not reflect the true aggregated bandwidth. This makes it hard for upper-layer software to optimize load balancing decisions based on accurate bandwidth information. Fix the issue by calculating the possible maximum speed of a LAG as the sum of speeds of all active uplinks that are part of the LAG. Propagate this effective max speed to vports associated with the LAG whenever a relevant event occurs, such as physical port link state changes or LAG creation/modification. With this change, upper-layer components receive accurate bandwidth information corresponding to the active members of the LAG and can make better load balancing decisions. Signed-off-by: Or Har-Toov Reviewed-by: Maher Sanalla Reviewed-by: Mark Bloch Signed-off-by: Edward Srouji --- drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c | 158 +++++++++++++++++= ++++ drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h | 9 ++ .../net/ethernet/mellanox/mlx5/core/mlx5_core.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/port.c | 24 ++++ drivers/net/ethernet/mellanox/mlx5/core/vport.c | 45 ++++++ include/linux/mlx5/vport.h | 4 + 6 files changed, 241 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index 1ac933cd8f02..a042612dcde6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -996,6 +996,126 @@ static bool mlx5_lag_should_disable_lag(struct mlx5_l= ag *ldev, bool do_bond) ldev->mode !=3D MLX5_LAG_MODE_MPESW; } =20 +#ifdef CONFIG_MLX5_ESWITCH +static int +mlx5_lag_sum_devices_speed(struct mlx5_lag *ldev, u32 *sum_speed, + int (*get_speed)(struct mlx5_core_dev *, u32 *)) +{ + struct mlx5_core_dev *pf_mdev; + int pf_idx; + u32 speed; + int ret; + + *sum_speed =3D 0; + mlx5_ldev_for_each(pf_idx, 0, ldev) { + pf_mdev =3D ldev->pf[pf_idx].dev; + if (!pf_mdev) + continue; + + ret =3D get_speed(pf_mdev, &speed); + if (ret) { + mlx5_core_dbg(pf_mdev, + "Failed to get device speed using %ps. Device %s speed is not av= ailable (err=3D%d)\n", + get_speed, dev_name(pf_mdev->device), + ret); + return ret; + } + + *sum_speed +=3D speed; + } + + return 0; +} + +static int mlx5_lag_sum_devices_max_speed(struct mlx5_lag *ldev, u32 *max_= speed) +{ + return mlx5_lag_sum_devices_speed(ldev, max_speed, + mlx5_port_max_linkspeed); +} + +static void mlx5_lag_modify_device_vports_speed(struct mlx5_core_dev *mdev, + u32 speed) +{ + u16 op_mod =3D MLX5_VPORT_STATE_OP_MOD_ESW_VPORT; + struct mlx5_eswitch *esw =3D mdev->priv.eswitch; + struct mlx5_vport *vport; + unsigned long i; + int ret; + + if (!esw) + return; + + if (!MLX5_CAP_ESW(mdev, esw_vport_state_max_tx_speed)) + return; + + mlx5_esw_for_each_vport(esw, i, vport) { + if (!vport) + continue; + + if (vport->vport =3D=3D MLX5_VPORT_UPLINK) + continue; + + ret =3D mlx5_modify_vport_max_tx_speed(mdev, op_mod, + vport->vport, true, speed); + if (ret) + mlx5_core_dbg(mdev, + "Failed to set vport %d speed %d, err=3D%d\n", + vport->vport, speed, ret); + } +} + +void mlx5_lag_set_vports_agg_speed(struct mlx5_lag *ldev) +{ + struct mlx5_core_dev *mdev; + u32 speed; + int pf_idx; + + speed =3D ldev->tracker.bond_speed_mbps; + + if (speed =3D=3D SPEED_UNKNOWN) + return; + + /* If speed is not set, use the sum of max speeds of all PFs */ + if (!speed && mlx5_lag_sum_devices_max_speed(ldev, &speed)) + return; + + speed =3D speed / MLX5_MAX_TX_SPEED_UNIT; + + mlx5_ldev_for_each(pf_idx, 0, ldev) { + mdev =3D ldev->pf[pf_idx].dev; + if (!mdev) + continue; + + mlx5_lag_modify_device_vports_speed(mdev, speed); + } +} + +void mlx5_lag_reset_vports_speed(struct mlx5_lag *ldev) +{ + struct mlx5_core_dev *mdev; + u32 speed; + int pf_idx; + int ret; + + mlx5_ldev_for_each(pf_idx, 0, ldev) { + mdev =3D ldev->pf[pf_idx].dev; + if (!mdev) + continue; + + ret =3D mlx5_port_oper_linkspeed(mdev, &speed); + if (ret) { + mlx5_core_dbg(mdev, + "Failed to reset vports speed for device %s. Oper speed is not a= vailable (err=3D%d)\n", + dev_name(mdev->device), ret); + continue; + } + + speed =3D speed / MLX5_MAX_TX_SPEED_UNIT; + mlx5_lag_modify_device_vports_speed(mdev, speed); + } +} +#endif + static void mlx5_do_bond(struct mlx5_lag *ldev) { int idx =3D mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); @@ -1083,9 +1203,12 @@ static void mlx5_do_bond(struct mlx5_lag *ldev) ndev); dev_put(ndev); } + mlx5_lag_set_vports_agg_speed(ldev); } else if (mlx5_lag_should_modify_lag(ldev, do_bond)) { mlx5_modify_lag(ldev, &tracker); + mlx5_lag_set_vports_agg_speed(ldev); } else if (mlx5_lag_should_disable_lag(ldev, do_bond)) { + mlx5_lag_reset_vports_speed(ldev); mlx5_disable_lag(ldev); } } @@ -1286,6 +1409,38 @@ static int mlx5_handle_changeinfodata_event(struct m= lx5_lag *ldev, return 1; } =20 +static void mlx5_lag_update_tracker_speed(struct lag_tracker *tracker, + struct net_device *ndev) +{ + struct ethtool_link_ksettings lksettings; + struct net_device *bond_dev; + int err; + + if (netif_is_lag_master(ndev)) + bond_dev =3D ndev; + else + bond_dev =3D netdev_master_upper_dev_get(ndev); + + if (!bond_dev) { + tracker->bond_speed_mbps =3D SPEED_UNKNOWN; + return; + } + + err =3D __ethtool_get_link_ksettings(bond_dev, &lksettings); + if (err) { + netdev_dbg(bond_dev, + "Failed to get speed for bond dev %s, err=3D%d\n", + bond_dev->name, err); + tracker->bond_speed_mbps =3D SPEED_UNKNOWN; + return; + } + + if (lksettings.base.speed =3D=3D SPEED_UNKNOWN) + tracker->bond_speed_mbps =3D 0; + else + tracker->bond_speed_mbps =3D lksettings.base.speed; +} + /* this handler is always registered to netdev events */ static int mlx5_lag_netdev_event(struct notifier_block *this, unsigned long event, void *ptr) @@ -1317,6 +1472,9 @@ static int mlx5_lag_netdev_event(struct notifier_bloc= k *this, break; } =20 + if (changed) + mlx5_lag_update_tracker_speed(&tracker, ndev); + ldev->tracker =3D tracker; =20 if (changed) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.h index 4918eee2b3da..8de5640a0161 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h @@ -48,6 +48,7 @@ struct lag_tracker { unsigned int is_bonded:1; unsigned int has_inactive:1; enum netdev_lag_hash hash_type; + u32 bond_speed_mbps; }; =20 /* LAG data of a ConnectX card. @@ -116,6 +117,14 @@ int mlx5_deactivate_lag(struct mlx5_lag *ldev); void mlx5_lag_add_devices(struct mlx5_lag *ldev); struct mlx5_devcom_comp_dev *mlx5_lag_get_devcom_comp(struct mlx5_lag *lde= v); =20 +#ifdef CONFIG_MLX5_ESWITCH +void mlx5_lag_set_vports_agg_speed(struct mlx5_lag *ldev); +void mlx5_lag_reset_vports_speed(struct mlx5_lag *ldev); +#else +static inline void mlx5_lag_set_vports_agg_speed(struct mlx5_lag *ldev) {} +static inline void mlx5_lag_reset_vports_speed(struct mlx5_lag *ldev) {} +#endif + static inline bool mlx5_lag_is_supported(struct mlx5_core_dev *dev) { if (!MLX5_CAP_GEN(dev, vport_group_manager) || diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/= net/ethernet/mellanox/mlx5/core/mlx5_core.h index cfebc110c02f..9fdb9a543cf1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -381,6 +381,7 @@ const struct mlx5_link_info *mlx5_port_ptys2info(struct= mlx5_core_dev *mdev, u32 mlx5_port_info2linkmodes(struct mlx5_core_dev *mdev, struct mlx5_link_info *info, bool force_legacy); +int mlx5_port_oper_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); int mlx5_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); =20 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/e= thernet/mellanox/mlx5/core/port.c index 85a9e534f442..83044c9b6b41 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c @@ -1200,6 +1200,30 @@ u32 mlx5_port_info2linkmodes(struct mlx5_core_dev *m= dev, return link_modes; } =20 +int mlx5_port_oper_linkspeed(struct mlx5_core_dev *mdev, u32 *speed) +{ + const struct mlx5_link_info *table; + struct mlx5_port_eth_proto eproto; + u32 oper_speed =3D 0; + u32 max_size; + bool ext; + int err; + int i; + + ext =3D mlx5_ptys_ext_supported(mdev); + err =3D mlx5_port_query_eth_proto(mdev, 1, ext, &eproto); + if (err) + return err; + + mlx5e_port_get_link_mode_info_arr(mdev, &table, &max_size, false); + for (i =3D 0; i < max_size; ++i) + if (eproto.oper & MLX5E_PROT_MASK(i)) + oper_speed =3D max(oper_speed, table[i].speed); + + *speed =3D oper_speed; + return 0; +} + int mlx5_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed) { const struct mlx5_link_info *table; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/vport.c b/drivers/net/= ethernet/mellanox/mlx5/core/vport.c index 306affbcfd3b..78b1b291cfa4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/vport.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/vport.c @@ -62,6 +62,28 @@ u8 mlx5_query_vport_state(struct mlx5_core_dev *mdev, u8= opmod, u16 vport) return MLX5_GET(query_vport_state_out, out, state); } =20 +static int mlx5_query_vport_admin_state(struct mlx5_core_dev *mdev, u8 opm= od, + u16 vport, u8 other_vport, + u8 *admin_state) +{ + u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] =3D {}; + u32 in[MLX5_ST_SZ_DW(query_vport_state_in)] =3D {}; + int err; + + MLX5_SET(query_vport_state_in, in, opcode, + MLX5_CMD_OP_QUERY_VPORT_STATE); + MLX5_SET(query_vport_state_in, in, op_mod, opmod); + MLX5_SET(query_vport_state_in, in, vport_number, vport); + MLX5_SET(query_vport_state_in, in, other_vport, other_vport); + + err =3D mlx5_cmd_exec_inout(mdev, query_vport_state, in, out); + if (err) + return err; + + *admin_state =3D MLX5_GET(query_vport_state_out, out, admin_state); + return 0; +} + int mlx5_modify_vport_admin_state(struct mlx5_core_dev *mdev, u8 opmod, u16 vport, u8 other_vport, u8 state) { @@ -77,6 +99,29 @@ int mlx5_modify_vport_admin_state(struct mlx5_core_dev *= mdev, u8 opmod, return mlx5_cmd_exec_in(mdev, modify_vport_state, in); } =20 +int mlx5_modify_vport_max_tx_speed(struct mlx5_core_dev *mdev, u8 opmod, + u16 vport, u8 other_vport, u16 max_tx_speed) +{ + u32 in[MLX5_ST_SZ_DW(modify_vport_state_in)] =3D {}; + u8 admin_state; + int err; + + err =3D mlx5_query_vport_admin_state(mdev, opmod, vport, other_vport, + &admin_state); + if (err) + return err; + + MLX5_SET(modify_vport_state_in, in, opcode, + MLX5_CMD_OP_MODIFY_VPORT_STATE); + MLX5_SET(modify_vport_state_in, in, op_mod, opmod); + MLX5_SET(modify_vport_state_in, in, vport_number, vport); + MLX5_SET(modify_vport_state_in, in, other_vport, other_vport); + MLX5_SET(modify_vport_state_in, in, admin_state, admin_state); + MLX5_SET(modify_vport_state_in, in, max_tx_speed, max_tx_speed); + + return mlx5_cmd_exec_in(mdev, modify_vport_state, in); +} + static int mlx5_query_nic_vport_context(struct mlx5_core_dev *mdev, u16 vp= ort, bool other_vport, u32 *out) { diff --git a/include/linux/mlx5/vport.h b/include/linux/mlx5/vport.h index f876bfc0669c..2acf10e9f60a 100644 --- a/include/linux/mlx5/vport.h +++ b/include/linux/mlx5/vport.h @@ -41,6 +41,8 @@ (MLX5_CAP_GEN(mdev, port_type) =3D=3D MLX5_CAP_PORT_TYPE_ETH) && \ mlx5_core_is_pf(mdev)) =20 +#define MLX5_MAX_TX_SPEED_UNIT 100 + enum { MLX5_CAP_INLINE_MODE_L2, MLX5_CAP_INLINE_MODE_VPORT_CONTEXT, @@ -58,6 +60,8 @@ enum { u8 mlx5_query_vport_state(struct mlx5_core_dev *mdev, u8 opmod, u16 vport); int mlx5_modify_vport_admin_state(struct mlx5_core_dev *mdev, u8 opmod, u16 vport, u8 other_vport, u8 state); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Or Har-Toov , "Maher Sanalla" Subject: [PATCH mlx5-next 03/10] net/mlx5: Handle port and vport speed change events in MPESW Date: Thu, 18 Dec 2025 17:58:13 +0200 Message-ID: <20251218-vf-bw-lag-mode-v1-3-7d8ed4368bea@nvidia.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> References: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766069544; l=10422; i=edwards@nvidia.com; s=20251029; h=from:subject:message-id; bh=+3/LGyzysM6EiOwyN7R1W30WCeCKs2Ca44dFQbjCSZo=; b=L3NWf5NDHnEv3Xk4/kM3xJSVTxWyAKoOuNfrW84jAXmVqRMK6YP34WA1BD7O50mb8yV2ob7T6 wU7F1GwhEzCAOWGT/5txXhQCJ1vQI4RC2l7ptUDeo+8+n5AoNmQ6kM4 X-Developer-Key: i=edwards@nvidia.com; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 15:58:43.6044 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c589191c-f1e4-4483-e953-08de3e4e51fe X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD77.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9341 From: Or Har-Toov Add port change event handling logic for MPESW LAG mode, ensuring VFs are updated when the speed of LAG physical ports changes. This triggers a speed update workflow when relevant port state changes occur, enabling consistent and accurate reporting of VF bandwidth. Signed-off-by: Or Har-Toov Reviewed-by: Maher Sanalla Reviewed-by: Mark Bloch Signed-off-by: Edward Srouji --- drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c | 38 ++++++++++++++++++= --- drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h | 2 ++ .../net/ethernet/mellanox/mlx5/core/lag/mpesw.c | 39 ++++++++++++++++++= ++++ .../net/ethernet/mellanox/mlx5/core/lag/mpesw.h | 14 ++++++++ drivers/net/ethernet/mellanox/mlx5/core/vport.c | 29 ++++++++++++++++ include/linux/mlx5/driver.h | 1 + include/linux/mlx5/vport.h | 2 ++ 7 files changed, 121 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index a042612dcde6..0b931aaecef8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -233,14 +233,25 @@ static void mlx5_ldev_free(struct kref *ref) { struct mlx5_lag *ldev =3D container_of(ref, struct mlx5_lag, ref); struct net *net; + int i; =20 if (ldev->nb.notifier_call) { net =3D read_pnet(&ldev->net); unregister_netdevice_notifier_net(net, &ldev->nb); } =20 + mlx5_ldev_for_each(i, 0, ldev) { + if (ldev->pf[i].dev && + ldev->pf[i].port_change_nb.nb.notifier_call) { + struct mlx5_nb *nb =3D &ldev->pf[i].port_change_nb; + + mlx5_eq_notifier_unregister(ldev->pf[i].dev, nb); + } + } + mlx5_lag_mp_cleanup(ldev); cancel_delayed_work_sync(&ldev->bond_work); + cancel_work_sync(&ldev->speed_update_work); destroy_workqueue(ldev->wq); mutex_destroy(&ldev->lock); kfree(ldev); @@ -274,6 +285,7 @@ static struct mlx5_lag *mlx5_lag_dev_alloc(struct mlx5_= core_dev *dev) kref_init(&ldev->ref); mutex_init(&ldev->lock); INIT_DELAYED_WORK(&ldev->bond_work, mlx5_do_bond_work); + INIT_WORK(&ldev->speed_update_work, mlx5_mpesw_speed_update_work); =20 ldev->nb.notifier_call =3D mlx5_lag_netdev_event; write_pnet(&ldev->net, mlx5_core_net(dev)); @@ -1033,6 +1045,13 @@ static int mlx5_lag_sum_devices_max_speed(struct mlx= 5_lag *ldev, u32 *max_speed) mlx5_port_max_linkspeed); } =20 +static int mlx5_lag_sum_devices_oper_speed(struct mlx5_lag *ldev, + u32 *oper_speed) +{ + return mlx5_lag_sum_devices_speed(ldev, oper_speed, + mlx5_port_oper_linkspeed); +} + static void mlx5_lag_modify_device_vports_speed(struct mlx5_core_dev *mdev, u32 speed) { @@ -1070,10 +1089,14 @@ void mlx5_lag_set_vports_agg_speed(struct mlx5_lag = *ldev) u32 speed; int pf_idx; =20 - speed =3D ldev->tracker.bond_speed_mbps; - - if (speed =3D=3D SPEED_UNKNOWN) - return; + if (ldev->mode =3D=3D MLX5_LAG_MODE_MPESW) { + if (mlx5_lag_sum_devices_oper_speed(ldev, &speed)) + return; + } else { + speed =3D ldev->tracker.bond_speed_mbps; + if (speed =3D=3D SPEED_UNKNOWN) + return; + } =20 /* If speed is not set, use the sum of max speeds of all PFs */ if (!speed && mlx5_lag_sum_devices_max_speed(ldev, &speed)) @@ -1520,6 +1543,10 @@ static void mlx5_ldev_add_mdev(struct mlx5_lag *ldev, =20 ldev->pf[fn].dev =3D dev; dev->priv.lag =3D ldev; + + MLX5_NB_INIT(&ldev->pf[fn].port_change_nb, + mlx5_lag_mpesw_port_change_event, PORT_CHANGE); + mlx5_eq_notifier_register(dev, &ldev->pf[fn].port_change_nb); } =20 static void mlx5_ldev_remove_mdev(struct mlx5_lag *ldev, @@ -1531,6 +1558,9 @@ static void mlx5_ldev_remove_mdev(struct mlx5_lag *ld= ev, if (ldev->pf[fn].dev !=3D dev) return; =20 + if (ldev->pf[fn].port_change_nb.nb.notifier_call) + mlx5_eq_notifier_unregister(dev, &ldev->pf[fn].port_change_nb); + ldev->pf[fn].dev =3D NULL; dev->priv.lag =3D NULL; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.h index 8de5640a0161..be1afece5fdc 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h @@ -39,6 +39,7 @@ struct lag_func { struct mlx5_core_dev *dev; struct net_device *netdev; bool has_drop; + struct mlx5_nb port_change_nb; }; =20 /* Used for collection of netdev event info. */ @@ -67,6 +68,7 @@ struct mlx5_lag { struct lag_tracker tracker; struct workqueue_struct *wq; struct delayed_work bond_work; + struct work_struct speed_update_work; struct notifier_block nb; possible_net_t net; struct lag_mp lag_mp; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c b/drivers/= net/ethernet/mellanox/mlx5/core/lag/mpesw.c index aad52d3a90e6..31464343f642 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c @@ -103,6 +103,8 @@ static int enable_mpesw(struct mlx5_lag *ldev) goto err_rescan_drivers; } =20 + mlx5_lag_set_vports_agg_speed(ldev); + return 0; =20 err_rescan_drivers: @@ -216,3 +218,40 @@ bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev) return ldev && ldev->mode =3D=3D MLX5_LAG_MODE_MPESW; } EXPORT_SYMBOL(mlx5_lag_is_mpesw); + +void mlx5_mpesw_speed_update_work(struct work_struct *work) +{ + struct mlx5_lag *ldev =3D container_of(work, struct mlx5_lag, + speed_update_work); + + mutex_lock(&ldev->lock); + if (ldev->mode =3D=3D MLX5_LAG_MODE_MPESW) { + if (ldev->mode_changes_in_progress) + queue_work(ldev->wq, &ldev->speed_update_work); + else + mlx5_lag_set_vports_agg_speed(ldev); + } + + mutex_unlock(&ldev->lock); +} + +int mlx5_lag_mpesw_port_change_event(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct mlx5_nb *mlx5_nb =3D container_of(nb, struct mlx5_nb, nb); + struct lag_func *lag_func =3D container_of(mlx5_nb, + struct lag_func, + port_change_nb); + struct mlx5_core_dev *dev =3D lag_func->dev; + struct mlx5_lag *ldev =3D dev->priv.lag; + struct mlx5_eqe *eqe =3D data; + + if (!ldev) + return NOTIFY_DONE; + + if (eqe->sub_type =3D=3D MLX5_PORT_CHANGE_SUBTYPE_DOWN || + eqe->sub_type =3D=3D MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) + queue_work(ldev->wq, &ldev->speed_update_work); + + return NOTIFY_OK; +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h b/drivers/= net/ethernet/mellanox/mlx5/core/lag/mpesw.h index 02520f27a033..f5d9b5c97b0d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.h @@ -32,4 +32,18 @@ bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev); void mlx5_lag_mpesw_disable(struct mlx5_core_dev *dev); int mlx5_lag_mpesw_enable(struct mlx5_core_dev *dev); =20 +#ifdef CONFIG_MLX5_ESWITCH +void mlx5_mpesw_speed_update_work(struct work_struct *work); +int mlx5_lag_mpesw_port_change_event(struct notifier_block *nb, + unsigned long event, void *data); +#else +static inline void mlx5_mpesw_speed_update_work(struct work_struct *work) = {} +static inline int mlx5_lag_mpesw_port_change_event(struct notifier_block *= nb, + unsigned long event, + void *data) +{ + return NOTIFY_DONE; +} +#endif /* CONFIG_MLX5_ESWITCH */ + #endif /* __MLX5_LAG_MPESW_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/vport.c b/drivers/net/= ethernet/mellanox/mlx5/core/vport.c index 78b1b291cfa4..cb098d3eb2fa 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/vport.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/vport.c @@ -122,6 +122,35 @@ int mlx5_modify_vport_max_tx_speed(struct mlx5_core_de= v *mdev, u8 opmod, return mlx5_cmd_exec_in(mdev, modify_vport_state, in); } =20 +int mlx5_query_vport_max_tx_speed(struct mlx5_core_dev *mdev, u8 op_mod, + u16 vport, u8 other_vport, u32 *max_tx_speed) +{ + u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] =3D {}; + u32 in[MLX5_ST_SZ_DW(query_vport_state_in)] =3D {}; + u32 state; + int err; + + MLX5_SET(query_vport_state_in, in, opcode, + MLX5_CMD_OP_QUERY_VPORT_STATE); + MLX5_SET(query_vport_state_in, in, op_mod, op_mod); + MLX5_SET(query_vport_state_in, in, vport_number, vport); + MLX5_SET(query_vport_state_in, in, other_vport, other_vport); + + err =3D mlx5_cmd_exec_inout(mdev, query_vport_state, in, out); + if (err) + return err; + + state =3D MLX5_GET(query_vport_state_out, out, state); + if (state =3D=3D VPORT_STATE_DOWN) { + *max_tx_speed =3D 0; + return 0; + } + + *max_tx_speed =3D MLX5_GET(query_vport_state_out, out, max_tx_speed); + return 0; +} +EXPORT_SYMBOL_GPL(mlx5_query_vport_max_tx_speed); + static int mlx5_query_nic_vport_context(struct mlx5_core_dev *mdev, u16 vp= ort, bool other_vport, u32 *out) { diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 1c54aa6f74fb..9e0ab3cfab73 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -1149,6 +1149,7 @@ int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *= dev); bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); bool mlx5_lag_is_active(struct mlx5_core_dev *dev); +int mlx5_lag_query_bond_speed(struct net_device *bond_dev, u32 *speed); bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev); bool mlx5_lag_is_master(struct mlx5_core_dev *dev); bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev); diff --git a/include/linux/mlx5/vport.h b/include/linux/mlx5/vport.h index 2acf10e9f60a..dfa2fe32217a 100644 --- a/include/linux/mlx5/vport.h +++ b/include/linux/mlx5/vport.h @@ -60,6 +60,8 @@ enum { u8 mlx5_query_vport_state(struct mlx5_core_dev *mdev, u8 opmod, u16 vport); int mlx5_modify_vport_admin_state(struct mlx5_core_dev *mdev, u8 opmod, u16 vport, u8 other_vport, u8 state); +int mlx5_query_vport_max_tx_speed(struct mlx5_core_dev *mdev, u8 op_mod, + u16 vport, u8 other_vport, u32 *max_tx_speed); int mlx5_modify_vport_max_tx_speed(struct mlx5_core_dev *mdev, u8 opmod, u16 vport, u8 other_vport, u16 max_tx_speed); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Or Har-Toov Subject: [PATCH mlx5-next 04/10] net/mlx5: Add support for querying bond speed Date: Thu, 18 Dec 2025 17:58:20 +0200 Message-ID: <20251218-vf-bw-lag-mode-v1-4-7d8ed4368bea@nvidia.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> References: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766069544; l=2387; i=edwards@nvidia.com; s=20251029; h=from:subject:message-id; bh=DYA3j1FbMdWMjw+VR2DyyLdvAFv7QQDyFWSQpq59lhE=; b=9V31cIlnHJMoUT+XFcs9UlYbsU0B9ZtSEoFNLSdQ5EejhW8NVj8GTx7YuIKWtYdFduW3U3YSL af/3hfhiyrDDyieKtyczgU0AtGfUGUdeSepoYROAHd6OQjKgCWdc90C X-Developer-Key: i=edwards@nvidia.com; a=ed25519; pk=VME+d2WbMZT5AY+AolKh2XIdrnXWUwwzz/XLQ3jXgDM= Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD79:EE_|DM4PR12MB6062:EE_ X-MS-Office365-Filtering-Correlation-Id: 9dbbc216-24a6-4f69-7473-08de3e4e5509 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|7416014|36860700013|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 15:58:48.6649 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9dbbc216-24a6-4f69-7473-08de3e4e5509 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD79.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6062 From: Or Har-Toov Add mlx5_lag_query_bond_speed() to query the aggregated speed of lag configurationsi with a bond device. Signed-off-by: Or Har-Toov Reviewed-by: Mark Bloch Signed-off-by: Edward Srouji --- drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c | 27 +++++++++++++++++++= ++++ include/linux/mlx5/driver.h | 2 +- 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/lag/lag.c index 0b931aaecef8..187ea8219ca9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -1464,6 +1464,33 @@ static void mlx5_lag_update_tracker_speed(struct lag= _tracker *tracker, tracker->bond_speed_mbps =3D lksettings.base.speed; } =20 +/* Returns speed in Mbps. */ +int mlx5_lag_query_bond_speed(struct mlx5_core_dev *mdev, u32 *speed) +{ + struct mlx5_lag *ldev; + unsigned long flags; + int ret =3D 0; + + spin_lock_irqsave(&lag_lock, flags); + ldev =3D mlx5_lag_dev(mdev); + if (!ldev) { + ret =3D -ENODEV; + goto unlock; + } + + *speed =3D ldev->tracker.bond_speed_mbps; + + if (*speed =3D=3D SPEED_UNKNOWN) { + mlx5_core_dbg(mdev, "Bond speed is unknown\n"); + ret =3D -EINVAL; + } + +unlock: + spin_unlock_irqrestore(&lag_lock, flags); + return ret; +} +EXPORT_SYMBOL_GPL(mlx5_lag_query_bond_speed); + /* this handler is always registered to netdev events */ static int mlx5_lag_netdev_event(struct notifier_block *this, unsigned long event, void *ptr) diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 9e0ab3cfab73..e2d067b1e67b 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -1149,7 +1149,7 @@ int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *= dev); bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); bool mlx5_lag_is_active(struct mlx5_core_dev *dev); -int mlx5_lag_query_bond_speed(struct net_device *bond_dev, u32 *speed); +int mlx5_lag_query_bond_speed(struct mlx5_core_dev *dev, u32 *speed); bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev); bool mlx5_lag_is_master(struct mlx5_core_dev *dev); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Or Har-Toov Subject: [PATCH rdma-next 05/10] IB/core: Add async event on device speed change Date: Thu, 18 Dec 2025 17:58:26 +0200 Message-ID: <20251218-vf-bw-lag-mode-v1-5-7d8ed4368bea@nvidia.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> References: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766069544; l=1340; i=edwards@nvidia.com; s=20251029; h=from:subject:message-id; bh=vRYdnneA8bd5HUCiwpeL0kp5mDnnbvhnpCSpmUChFUY=; b=YbqUaydBuAKajfjMFLfevCuTLfQ1HI9d/yERmNTsAKuNRKjxXs2xJ1gmbBNp8irLO4d+o23yG +jo+z6fOR76BxL3W9bRL+nvztqRsWpf+Ti3e+zOcQ/taLEIitbRt2rl X-Developer-Key: i=edwards@nvidia.com; a=ed25519; pk=VME+d2WbMZT5AY+AolKh2XIdrnXWUwwzz/XLQ3jXgDM= Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE35:EE_|IA1PR12MB9740:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b299925-beaf-46d0-d6c3-08de3e4e5297 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 15:58:44.6523 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b299925-beaf-46d0-d6c3-08de3e4e5297 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE35.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9740 From: Or Har-Toov Add IB_EVENT_DEVICE_SPEED_CHANGE for notifying user applications on device's ports speed changes. Signed-off-by: Or Har-Toov Reviewed-by: Mark Bloch Signed-off-by: Edward Srouji --- drivers/infiniband/core/verbs.c | 1 + include/rdma/ib_verbs.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/infiniband/core/verbs.c b/drivers/infiniband/core/verb= s.c index 11b1a194de44..f495a2182c84 100644 --- a/drivers/infiniband/core/verbs.c +++ b/drivers/infiniband/core/verbs.c @@ -78,6 +78,7 @@ static const char * const ib_events[] =3D { [IB_EVENT_QP_LAST_WQE_REACHED] =3D "last WQE reached", [IB_EVENT_CLIENT_REREGISTER] =3D "client reregister", [IB_EVENT_GID_CHANGE] =3D "GID changed", + [IB_EVENT_DEVICE_SPEED_CHANGE] =3D "device speed change" }; =20 const char *__attribute_const__ ib_event_msg(enum ib_event_type event) diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h index 6aad66bc5dd7..95f1e557cbb8 100644 --- a/include/rdma/ib_verbs.h +++ b/include/rdma/ib_verbs.h @@ -764,6 +764,7 @@ enum ib_event_type { IB_EVENT_CLIENT_REREGISTER, IB_EVENT_GID_CHANGE, IB_EVENT_WQ_FATAL, + IB_EVENT_DEVICE_SPEED_CHANGE, }; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Or Har-Toov Subject: [PATCH rdma-next 06/10] IB/core: Add helper to convert port attributes to data rate Date: Thu, 18 Dec 2025 17:58:32 +0200 Message-ID: <20251218-vf-bw-lag-mode-v1-6-7d8ed4368bea@nvidia.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> References: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766069544; l=3311; i=edwards@nvidia.com; s=20251029; h=from:subject:message-id; bh=1KbwFRkFYU9DgsLWpVgIh9uLuiiwUdy6L5df/5FOubw=; b=4CRs3w/IVJo48ZV4dhv3+tKwEZqg4sRwepa0iP9u4S/8EXoQ7NZI3kEGuzf1g8VZ5bacLgfyE i2Sku33BNovDSeXbdnGfGOie1G9V8VD6K3s9ZYgcHhV69NI7xM1hDb3 X-Developer-Key: i=edwards@nvidia.com; a=ed25519; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 15:59:01.1899 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 34948929-1e71-4cdb-2c42-08de3e4e5c7f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD74.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7968 From: Or Har-Toov Introduce ib_port_attr_to_rate() to compute the data rate in 100 Mbps units (deci-Gb/sec) from a port's active_speed and active_width attributes. This generic helper removes duplicated speed-to-rate calculations, which are used by sysfs and the upcoming new verb. Signed-off-by: Or Har-Toov Reviewed-by: Mark Bloch Signed-off-by: Edward Srouji --- drivers/infiniband/core/verbs.c | 51 +++++++++++++++++++++++++++++++++++++= ++++ include/rdma/ib_verbs.h | 14 +++++++++++ 2 files changed, 65 insertions(+) diff --git a/drivers/infiniband/core/verbs.c b/drivers/infiniband/core/verb= s.c index f495a2182c84..8b56b6b62352 100644 --- a/drivers/infiniband/core/verbs.c +++ b/drivers/infiniband/core/verbs.c @@ -217,6 +217,57 @@ __attribute_const__ int ib_rate_to_mbps(enum ib_rate r= ate) } EXPORT_SYMBOL(ib_rate_to_mbps); =20 +struct ib_speed_attr { + const char *str; + int speed; +}; + +#define IB_SPEED_ATTR(speed_type, _str, _speed) \ + [speed_type] =3D {.str =3D _str, .speed =3D _speed} + +static const struct ib_speed_attr ib_speed_attrs[] =3D { + IB_SPEED_ATTR(IB_SPEED_SDR, " SDR", 25), + IB_SPEED_ATTR(IB_SPEED_DDR, " DDR", 50), + IB_SPEED_ATTR(IB_SPEED_QDR, " QDR", 100), + IB_SPEED_ATTR(IB_SPEED_FDR10, " FDR10", 100), + IB_SPEED_ATTR(IB_SPEED_FDR, " FDR", 140), + IB_SPEED_ATTR(IB_SPEED_EDR, " EDR", 250), + IB_SPEED_ATTR(IB_SPEED_HDR, " HDR", 500), + IB_SPEED_ATTR(IB_SPEED_NDR, " NDR", 1000), + IB_SPEED_ATTR(IB_SPEED_XDR, " XDR", 2000), +}; + +int ib_port_attr_to_speed_info(struct ib_port_attr *attr, + struct ib_port_speed_info *speed_info) +{ + int speed_idx =3D attr->active_speed; + + switch (attr->active_speed) { + case IB_SPEED_DDR: + case IB_SPEED_QDR: + case IB_SPEED_FDR10: + case IB_SPEED_FDR: + case IB_SPEED_EDR: + case IB_SPEED_HDR: + case IB_SPEED_NDR: + case IB_SPEED_XDR: + case IB_SPEED_SDR: + break; + default: + speed_idx =3D IB_SPEED_SDR; /* Default to SDR for invalid rates */ + break; + } + + speed_info->str =3D ib_speed_attrs[speed_idx].str; + speed_info->rate =3D ib_speed_attrs[speed_idx].speed; + speed_info->rate *=3D ib_width_enum_to_int(attr->active_width); + if (speed_info->rate < 0) + return -EINVAL; + + return 0; +} +EXPORT_SYMBOL(ib_port_attr_to_speed_info); + __attribute_const__ enum rdma_transport_type rdma_node_get_transport(unsigned int node_type) { diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h index 95f1e557cbb8..b984f9581a73 100644 --- a/include/rdma/ib_verbs.h +++ b/include/rdma/ib_verbs.h @@ -878,6 +878,20 @@ __attribute_const__ int ib_rate_to_mult(enum ib_rate r= ate); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 15:59:01.9357 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e72a5f4d-d642-4408-e5e7-08de3e4e5cdd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6389 From: Or Har-Toov Update sysfs rate_show() to rely on ib_port_attr_to_speed_info() for converting IB port speed and width attributes to data rate and speed string. Signed-off-by: Or Har-Toov Reviewed-by: Maher Sanalla Reviewed-by: Mark Bloch Signed-off-by: Edward Srouji --- drivers/infiniband/core/sysfs.c | 56 ++++++-------------------------------= ---- 1 file changed, 8 insertions(+), 48 deletions(-) diff --git a/drivers/infiniband/core/sysfs.c b/drivers/infiniband/core/sysf= s.c index 0ed862b38b44..bfaca07933d8 100644 --- a/drivers/infiniband/core/sysfs.c +++ b/drivers/infiniband/core/sysfs.c @@ -292,62 +292,22 @@ static ssize_t cap_mask_show(struct ib_device *ibdev,= u32 port_num, static ssize_t rate_show(struct ib_device *ibdev, u32 port_num, struct ib_port_attribute *unused, char *buf) { + struct ib_port_speed_info speed_info; struct ib_port_attr attr; - char *speed =3D ""; - int rate; /* in deci-Gb/sec */ ssize_t ret; =20 ret =3D ib_query_port(ibdev, port_num, &attr); if (ret) return ret; =20 - switch (attr.active_speed) { - case IB_SPEED_DDR: - speed =3D " DDR"; - rate =3D 50; - break; - case IB_SPEED_QDR: - speed =3D " QDR"; - rate =3D 100; - break; - case IB_SPEED_FDR10: - speed =3D " FDR10"; - rate =3D 100; - break; - case IB_SPEED_FDR: - speed =3D " FDR"; - rate =3D 140; - break; - case IB_SPEED_EDR: - speed =3D " EDR"; - rate =3D 250; - break; - case IB_SPEED_HDR: - speed =3D " HDR"; - rate =3D 500; - break; - case IB_SPEED_NDR: - speed =3D " NDR"; - rate =3D 1000; - break; - case IB_SPEED_XDR: - speed =3D " XDR"; - rate =3D 2000; - break; - case IB_SPEED_SDR: - default: /* default to SDR for invalid rates */ - speed =3D " SDR"; - rate =3D 25; - break; - } - - rate *=3D ib_width_enum_to_int(attr.active_width); - if (rate < 0) - return -EINVAL; + ret =3D ib_port_attr_to_speed_info(&attr, &speed_info); + if (ret) + return ret; =20 - return sysfs_emit(buf, "%d%s Gb/sec (%dX%s)\n", rate / 10, - rate % 10 ? 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Thu, 18 Dec 2025 07:58:47 -0800 From: Edward Srouji To: , Leon Romanovsky , Saeed Mahameed , Tariq Toukan , Mark Bloch , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Or Har-Toov Subject: [PATCH rdma-next 08/10] IB/core: Add query_port_speed verb Date: Thu, 18 Dec 2025 17:58:46 +0200 Message-ID: <20251218-vf-bw-lag-mode-v1-8-7d8ed4368bea@nvidia.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> References: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766069544; l=4955; i=edwards@nvidia.com; s=20251029; h=from:subject:message-id; bh=Kt/KrEayBQDIibnIQzfDvSmj/uPFgDGcYeFaXYm4DcY=; b=k5SswPW8VG3L88Q1SGQiD2TdsAWhpyscwEW0TuEN5nuolrw6sq6Np8NVa1B9Hic82SmerSnuH +v10OUZhjpTC54lKTF/vVA9ESwd4oDZt0F3+kVdwEIM4iNRjAWg6VOq X-Developer-Key: i=edwards@nvidia.com; a=ed25519; pk=VME+d2WbMZT5AY+AolKh2XIdrnXWUwwzz/XLQ3jXgDM= Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD78:EE_|SN7PR12MB8101:EE_ X-MS-Office365-Filtering-Correlation-Id: 1760ba4f-a343-48c4-1276-08de3e4e6333 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 15:59:12.4392 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1760ba4f-a343-48c4-1276-08de3e4e6333 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD78.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8101 From: Or Har-Toov Add new ibv_query_port_speed() verb to enable applications to query the effective bandwidth of a port. This verb is particularly useful when the speed is not a multiplication of IB speed and width where width is 2^n. Signed-off-by: Or Har-Toov Reviewed-by: Mark Bloch Signed-off-by: Edward Srouji --- drivers/infiniband/core/device.c | 1 + drivers/infiniband/core/uverbs_std_types_device.c | 42 +++++++++++++++++++= ++++ include/rdma/ib_verbs.h | 2 ++ include/uapi/rdma/ib_user_ioctl_cmds.h | 6 ++++ 4 files changed, 51 insertions(+) diff --git a/drivers/infiniband/core/device.c b/drivers/infiniband/core/dev= ice.c index 13e8a1714bbd..04edc57592aa 100644 --- a/drivers/infiniband/core/device.c +++ b/drivers/infiniband/core/device.c @@ -2816,6 +2816,7 @@ void ib_set_device_ops(struct ib_device *dev, const s= truct ib_device_ops *ops) SET_DEVICE_OP(dev_ops, query_gid); SET_DEVICE_OP(dev_ops, query_pkey); SET_DEVICE_OP(dev_ops, query_port); + SET_DEVICE_OP(dev_ops, query_port_speed); SET_DEVICE_OP(dev_ops, query_qp); SET_DEVICE_OP(dev_ops, query_srq); SET_DEVICE_OP(dev_ops, query_ucontext); diff --git a/drivers/infiniband/core/uverbs_std_types_device.c b/drivers/in= finiband/core/uverbs_std_types_device.c index c0fd283d9d6c..a28f9f21bed8 100644 --- a/drivers/infiniband/core/uverbs_std_types_device.c +++ b/drivers/infiniband/core/uverbs_std_types_device.c @@ -209,6 +209,39 @@ static int UVERBS_HANDLER(UVERBS_METHOD_QUERY_PORT)( &resp, sizeof(resp)); } =20 +static int UVERBS_HANDLER(UVERBS_METHOD_QUERY_PORT_SPEED)( + struct uverbs_attr_bundle *attrs) +{ + struct ib_ucontext *ucontext; + struct ib_device *ib_dev; + u32 port_num; + u64 speed; + int ret; + + ucontext =3D ib_uverbs_get_ucontext(attrs); + if (IS_ERR(ucontext)) + return PTR_ERR(ucontext); + ib_dev =3D ucontext->device; + + if (!ib_dev->ops.query_port_speed) + return -EOPNOTSUPP; + + ret =3D uverbs_get_const(&port_num, attrs, + UVERBS_ATTR_QUERY_PORT_SPEED_PORT_NUM); + if (ret) + return ret; + + if (!rdma_is_port_valid(ib_dev, port_num)) + return -EINVAL; + + ret =3D ib_dev->ops.query_port_speed(ib_dev, port_num, &speed); + if (ret) + return ret; + + return uverbs_copy_to(attrs, UVERBS_ATTR_QUERY_PORT_SPEED_RESP, + &speed, sizeof(speed)); +} + static int UVERBS_HANDLER(UVERBS_METHOD_GET_CONTEXT)( struct uverbs_attr_bundle *attrs) { @@ -469,6 +502,14 @@ DECLARE_UVERBS_NAMED_METHOD( active_speed_ex), UA_MANDATORY)); =20 +DECLARE_UVERBS_NAMED_METHOD( + UVERBS_METHOD_QUERY_PORT_SPEED, + UVERBS_ATTR_CONST_IN(UVERBS_ATTR_QUERY_PORT_SPEED_PORT_NUM, u32, + UA_MANDATORY), + UVERBS_ATTR_PTR_OUT(UVERBS_ATTR_QUERY_PORT_SPEED_RESP, + UVERBS_ATTR_TYPE(u64), + UA_MANDATORY)); + DECLARE_UVERBS_NAMED_METHOD( UVERBS_METHOD_QUERY_GID_TABLE, UVERBS_ATTR_CONST_IN(UVERBS_ATTR_QUERY_GID_TABLE_ENTRY_SIZE, u64, @@ -498,6 +539,7 @@ DECLARE_UVERBS_GLOBAL_METHODS(UVERBS_OBJECT_DEVICE, &UVERBS_METHOD(UVERBS_METHOD_INVOKE_WRITE), &UVERBS_METHOD(UVERBS_METHOD_INFO_HANDLES), &UVERBS_METHOD(UVERBS_METHOD_QUERY_PORT), + &UVERBS_METHOD(UVERBS_METHOD_QUERY_PORT_SPEED), &UVERBS_METHOD(UVERBS_METHOD_QUERY_CONTEXT), &UVERBS_METHOD(UVERBS_METHOD_QUERY_GID_TABLE), &UVERBS_METHOD(UVERBS_METHOD_QUERY_GID_ENTRY)); diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h index b984f9581a73..a4786395328a 100644 --- a/include/rdma/ib_verbs.h +++ b/include/rdma/ib_verbs.h @@ -2418,6 +2418,8 @@ struct ib_device_ops { int comp_vector); int (*query_port)(struct ib_device *device, u32 port_num, struct ib_port_attr *port_attr); + int (*query_port_speed)(struct ib_device *device, u32 port_num, + u64 *speed); int (*modify_port)(struct ib_device *device, u32 port_num, int port_modify_mask, struct ib_port_modify *port_modify); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Or Har-Toov Subject: [PATCH rdma-next 09/10] RDMA/mlx5: Raise async event on device speed change Date: Thu, 18 Dec 2025 17:58:53 +0200 Message-ID: <20251218-vf-bw-lag-mode-v1-9-7d8ed4368bea@nvidia.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> References: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766069544; l=1432; i=edwards@nvidia.com; s=20251029; h=from:subject:message-id; bh=h5wZW1LI1kWmTGlwtXPO+VEysmFaSQ5nBUeqft/eCio=; b=BSSxujtTgcHm+t59ewdX32GQaVWakv6mtB5FTnbdx5v8Kn3t04uu9SCK0TEaOrIj+P0CQ6mux ljOCMXa63eLDhGV58+Z+5BHoXNcVVGO80WwfUSKVT5fxkwFmAk6Cbrq X-Developer-Key: i=edwards@nvidia.com; a=ed25519; pk=VME+d2WbMZT5AY+AolKh2XIdrnXWUwwzz/XLQ3jXgDM= Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F2:EE_|SJ1PR12MB6169:EE_ X-MS-Office365-Filtering-Correlation-Id: d2fb7987-3717-4bf6-13a4-08de3e4e63b6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|82310400026|376014|1800799024|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 15:59:13.4162 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d2fb7987-3717-4bf6-13a4-08de3e4e63b6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6169 From: Or Har-Toov Raise IB_EVENT_DEVICE_SPEED_CHANGE whenever the speed of one of the device's ports changes. Usually all ports of the device changes together. This ensures user applications and upper-layer software are immediately notified when bandwidth changes, improving traffic management in dynamic environments. This is especially useful for vports which are part of a LAG configuration, to know if the effective speed of the LAG was changed. Signed-off-by: Or Har-Toov Reviewed-by: Mark Bloch Signed-off-by: Edward Srouji --- drivers/infiniband/hw/mlx5/main.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5= /main.c index 40284bbb45d6..bea42acbeaad 100644 --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c @@ -2838,6 +2838,14 @@ static int handle_port_change(struct mlx5_ib_dev *ib= dev, struct mlx5_eqe *eqe, case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: case MLX5_PORT_CHANGE_SUBTYPE_DOWN: case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: + if (ibdev->ib_active) { + struct ib_event speed_event =3D {}; + + speed_event.device =3D &ibdev->ib_dev; + speed_event.event =3D IB_EVENT_DEVICE_SPEED_CHANGE; + ib_dispatch_event(&speed_event); + } + /* In RoCE, port up/down events are handled in * mlx5_netdev_event(). */ --=20 2.47.1 From nobody Sun Feb 8 18:44:16 2026 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011041.outbound.protection.outlook.com [52.101.52.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B7D436A01B; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe CC: , , , Or Har-Toov Subject: [PATCH rdma-next 10/10] RDMA/mlx5: Implement query_port_speed callback Date: Thu, 18 Dec 2025 17:59:00 +0200 Message-ID: <20251218-vf-bw-lag-mode-v1-10-7d8ed4368bea@nvidia.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> References: <20251218-vf-bw-lag-mode-v1-0-7d8ed4368bea@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766069544; l=5304; i=edwards@nvidia.com; s=20251029; h=from:subject:message-id; bh=/2jKTjIK0B9x/5XD4kSB6Q2ua3AVH4sYJDVpEnBfGAg=; b=pWXaHqsEmknMl55d289fPrNL7Y/w0/cQlclEhIHO+htqxN0oubX6GTtvkpWOszZmPFoXxCPAV FLfOvDqwGRbCp6374jbhOSIgXB9bmZL8ct0R7Khy6S5zc2AabfZ5TWz X-Developer-Key: i=edwards@nvidia.com; a=ed25519; pk=VME+d2WbMZT5AY+AolKh2XIdrnXWUwwzz/XLQ3jXgDM= Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F2:EE_|SA5PPF8ECEC29A9:EE_ X-MS-Office365-Filtering-Correlation-Id: 2351f487-860a-45c6-face-08de3e4e6aa6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026|7416014|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 15:59:25.0725 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2351f487-860a-45c6-face-08de3e4e6aa6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPF8ECEC29A9 From: Or Har-Toov Implement the query_port_speed callback for mlx5 driver to support querying effective port bandwidth. For LAG configurations, query the aggregated speed from the LAG layer or from the modified vport max_tx_speed. Signed-off-by: Or Har-Toov Reviewed-by: Mark Bloch Signed-off-by: Edward Srouji --- drivers/infiniband/hw/mlx5/main.c | 124 +++++++++++++++++++++++++++++++= ++++ drivers/infiniband/hw/mlx5/mlx5_ib.h | 2 + 2 files changed, 126 insertions(+) diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5= /main.c index bea42acbeaad..47c19d527fa2 100644 --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c @@ -1581,6 +1581,129 @@ static int mlx5_ib_rep_query_pkey(struct ib_device = *ibdev, u32 port, u16 index, return 0; } =20 +static int mlx5_ib_query_port_speed_from_port(struct mlx5_ib_dev *dev, + u32 port_num, u64 *speed) +{ + struct ib_port_speed_info speed_info; + struct ib_port_attr attr =3D {}; + int err; + + err =3D mlx5_ib_query_port(&dev->ib_dev, port_num, &attr); + if (err) + return err; + + if (attr.state =3D=3D IB_PORT_DOWN) { + *speed =3D 0; + return 0; + } + + err =3D ib_port_attr_to_speed_info(&attr, &speed_info); + if (err) + return err; + + *speed =3D speed_info.rate; + return 0; +} + +static int mlx5_ib_query_port_speed_from_vport(struct mlx5_core_dev *mdev, + u8 op_mod, u16 vport, + u8 other_vport, u64 *speed, + struct mlx5_ib_dev *dev, + u32 port_num) +{ + u32 max_tx_speed; + int err; + + err =3D mlx5_query_vport_max_tx_speed(mdev, op_mod, vport, other_vport, + &max_tx_speed); + if (err) + return err; + + if (max_tx_speed =3D=3D 0) + /* Value 0 indicates field not supported, fallback */ + return mlx5_ib_query_port_speed_from_port(dev, port_num, + speed); + + *speed =3D max_tx_speed; + return 0; +} + +static int mlx5_ib_query_port_speed_from_bond(struct mlx5_ib_dev *dev, + u32 port_num, u64 *speed) +{ + struct mlx5_core_dev *mdev =3D dev->mdev; + u32 bond_speed; + int err; + + err =3D mlx5_lag_query_bond_speed(mdev, &bond_speed); + if (err) + return err; + + *speed =3D bond_speed / MLX5_MAX_TX_SPEED_UNIT; + + return 0; +} + +static int mlx5_ib_query_port_speed_non_rep(struct mlx5_ib_dev *dev, + u32 port_num, u64 *speed) +{ + u16 op_mod =3D MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT; + + if (mlx5_lag_is_roce(dev->mdev)) + return mlx5_ib_query_port_speed_from_bond(dev, port_num, + speed); + + return mlx5_ib_query_port_speed_from_vport(dev->mdev, op_mod, 0, false, + speed, dev, port_num); +} + +static int mlx5_ib_query_port_speed_rep(struct mlx5_ib_dev *dev, u32 port_= num, + u64 *speed) +{ + struct mlx5_eswitch_rep *rep; + struct mlx5_core_dev *mdev; + u16 op_mod; + + if (!dev->port[port_num - 1].rep) { + mlx5_ib_warn(dev, "Representor doesn't exist for port %u\n", + port_num); + return -EINVAL; + } + + rep =3D dev->port[port_num - 1].rep; + mdev =3D mlx5_eswitch_get_core_dev(rep->esw); + if (!mdev) + return -ENODEV; + + if (rep->vport =3D=3D MLX5_VPORT_UPLINK) { + if (mlx5_lag_is_sriov(mdev)) + return mlx5_ib_query_port_speed_from_bond(dev, + port_num, + speed); + + return mlx5_ib_query_port_speed_from_port(dev, port_num, + speed); + } + + op_mod =3D MLX5_VPORT_STATE_OP_MOD_ESW_VPORT; + return mlx5_ib_query_port_speed_from_vport(dev->mdev, op_mod, + rep->vport, true, speed, dev, + port_num); +} + +int mlx5_ib_query_port_speed(struct ib_device *ibdev, u32 port_num, u64 *s= peed) +{ + struct mlx5_ib_dev *dev =3D to_mdev(ibdev); + + if (mlx5_ib_port_link_layer(ibdev, port_num) =3D=3D + IB_LINK_LAYER_INFINIBAND || mlx5_core_mp_enabled(dev->mdev)) + return mlx5_ib_query_port_speed_from_port(dev, port_num, speed); + else if (!dev->is_rep) + return mlx5_ib_query_port_speed_non_rep(dev, port_num, speed); + else + return mlx5_ib_query_port_speed_rep(dev, port_num, speed); +} + static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, union ib_gid *gid) { @@ -4305,6 +4428,7 @@ static const struct ib_device_ops mlx5_ib_dev_ops =3D= { .query_device =3D mlx5_ib_query_device, .query_gid =3D mlx5_ib_query_gid, .query_pkey =3D mlx5_ib_query_pkey, + .query_port_speed =3D mlx5_ib_query_port_speed, .query_qp =3D mlx5_ib_query_qp, .query_srq =3D mlx5_ib_query_srq, .query_ucontext =3D mlx5_ib_query_ucontext, diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/m= lx5/mlx5_ib.h index 09d82d5f95e3..cc6b3b6c713c 100644 --- a/drivers/infiniband/hw/mlx5/mlx5_ib.h +++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h @@ -1435,6 +1435,8 @@ int mlx5_query_mad_ifc_port(struct ib_device *ibdev, = u32 port, struct ib_port_attr *props); int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, struct ib_port_attr *props); +int mlx5_ib_query_port_speed(struct ib_device *ibdev, u32 port_num, + u64 *speed); void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *= pas, u64 access_flags); int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); --=20 2.47.1