From nobody Wed Feb 11 00:36:45 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 160CC2D5C92 for ; Thu, 18 Dec 2025 15:04:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766070275; cv=none; b=EAVvnm+c5HMfzbGPXjbUjJPLnke6DnrUyQyR0fN1UV593kpWZVIIZbSVDJaqKTJGSXvfrbvRaIEee78ijmN6WUeJ1jWZEYla05vi3nOTJrCElwXZNnZcvBQvo33ca8ZZDGRO4lWp7uP0i/dIholNpUnzAGs4c3NrEsLZzsIoxBA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766070275; c=relaxed/simple; bh=uI48RSG+a+nSuEyywiQ6swM+axk120OhOUA8CnTh+yk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gmNQk7ekSh3FSsLs6Z071oeYWMhy7SjH0dAcMMbXu2nPzCVLbYWg7pR9F2CVEi7YC9NhwutX/xsNDq3BnJhjpPVKY4Xy//Tc/Be3NsXW73ubVNy3ZicWV4wC7c1Dsh+QuPMvcNTgT899L8F1mOrjd3nCSpZKt03FOicg3gp+etE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1vWFY4-0007j2-Oa; Thu, 18 Dec 2025 16:04:12 +0100 Received: from dude02.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::28]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1vWFY1-006IfH-1p; Thu, 18 Dec 2025 16:04:09 +0100 Received: from localhost ([::1] helo=dude02.red.stw.pengutronix.de) by dude02.red.stw.pengutronix.de with esmtp (Exim 4.98.2) (envelope-from ) id 1vWFY1-00000002kPh-1nOx; Thu, 18 Dec 2025 16:04:09 +0100 From: Sascha Hauer Date: Thu, 18 Dec 2025 16:04:07 +0100 Subject: [PATCH v2 01/10] ASoC: tlv320adcx140: invert DRE_ENABLE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-sound-soc-codecs-tvl320adcx140-v2-1-3c2270c34bac@pengutronix.de> References: <20251218-sound-soc-codecs-tvl320adcx140-v2-0-3c2270c34bac@pengutronix.de> In-Reply-To: <20251218-sound-soc-codecs-tvl320adcx140-v2-0-3c2270c34bac@pengutronix.de> To: Shenghao Ding , Kevin Lu , Baojun Xu , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Davis , Dan Murphy Cc: linux-sound@vger.kernel.org, linux-kernel@vger.kernel.org, Kevin Lu , linux-rt-devel@lists.linux.dev, devicetree@vger.kernel.org, Sascha Hauer , Emil Svendsen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766070249; l=1278; i=s.hauer@pengutronix.de; s=20230412; h=from:subject:message-id; bh=WfOW2anrTgz/4XEyF51/kruoQkV8SVMulwmjlAzpc1c=; b=KZwIJgesMBd2J6tlmJpgQ5foIXa4107d+o+0giboc5aT1Axyfd5+f0ZihcbZfHKAOXNvFHwYR y7n3RCZNtytBacLBW4Jql74pzrXKyc3K2ncwqxxfWSUHNsi3Wb8i2Jb X-Developer-Key: i=s.hauer@pengutronix.de; a=ed25519; pk=4kuc9ocmECiBJKWxYgqyhtZOHj5AWi7+d0n/UjhkwTg= X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: s.hauer@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org From: Emil Svendsen Looking at section 8.6.1.1.69 in datasheets for both 5140 and 6140 (3140 doesn't support DRE). REG ADCX140_DSP_CFG1 BIT 3 field "DRE_AGC_SEL" it select either DRE or AGC. It states: * 0 =3D DRE * 1 =3D AGC The control is called "DRE_ENABLE" and for it to be true it has to be active low. This commit will invert the control so "DRE_ENABLE" is active low. Signed-off-by: Emil Svendsen Signed-off-by: Sascha Hauer --- sound/soc/codecs/tlv320adcx140.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/tlv320adcx140.c b/sound/soc/codecs/tlv320adcx= 140.c index 443cf59cb71ab3e70f47c4395159752a0331b1ef..75e1007012a48a569586bc28964= 00e79ddce1c71 100644 --- a/sound/soc/codecs/tlv320adcx140.c +++ b/sound/soc/codecs/tlv320adcx140.c @@ -338,7 +338,7 @@ static const struct snd_kcontrol_new adcx140_dapm_ch4_d= re_en_switch =3D SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0); =20 static const struct snd_kcontrol_new adcx140_dapm_dre_en_switch =3D - SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 0); + SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 1); =20 /* Output Mixer */ static const struct snd_kcontrol_new adcx140_output_mixer_controls[] =3D { --=20 2.47.3