From nobody Sun Feb 8 05:06:45 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD57A33508E; Thu, 18 Dec 2025 12:56:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062604; cv=pass; b=tVBBt+tiXmFp57pp3FhtfiSFc7TVspf5VpEZiW0evvVMlL42QrO5DlRBGtuEYW8UTGRrNg3oSjYenPp7VoqF+asJyPmVcJfUkc9r7zLK/RiaKiWOWvbntAz+pBj3LcaCWSP7KxRfwjZxHWle+mIwMTWofo3zo8bI3+E2w2HatDI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062604; c=relaxed/simple; bh=s4gWqn6AVICq0UMOP4oXABfrBXQ1mTOvQL8K5njXSlQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nQoHff2CluYcyFqKpDYQWN9BdXYbxXsnyLg67VO5MW/a9Ftj1V+9EegjlcjHL66AuVxGabt+eqDlmrj6BT/oOLsu9tX0TB+ZBLihwcmiBb3YJLdxEsKkDQ9Zcj+r9V28tIz7jAWC6grFOAeg0Q4ELDRRRGPM9rIN0NrFVdhbth4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=X7B+Ngts; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="X7B+Ngts" ARC-Seal: i=1; a=rsa-sha256; t=1766062550; cv=none; d=zohomail.com; s=zohoarc; b=B8vnSIVKVSZPXJ8U4+CaiqhGWT2VkqJe3XSJZalf6If7XtyBw1/KqjtYMf4huFZAdZdLHNUJxLHsMVD9bdP6TDk6w/ncC4YjiO7m928/fYLVMFILVIgfEg0C4YDuAzDM+xCdYnfsy9h1vyOod32z2alczRuK96SJmReQuIAYI8Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766062550; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=L4FVB0oYChYLlDwfcvsV37MKzm2n6cyg4ekMnI4E9H4=; b=T3+dsyHqClZXVjRTsk+4R/5copT6bf7ZdIEODPQngvBXAytF3OUHC0pdivgGHhwg7hvLkZ688cqrG6ZjimBeIrJytxvD8JGO1dmBUWxFJYKfDr2tzC6FPPJ8o82eo7Gl7jn+VXRvzN72R/FS3ujamA3qO3OK50GKGHTEH994MiI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1766062550; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=L4FVB0oYChYLlDwfcvsV37MKzm2n6cyg4ekMnI4E9H4=; b=X7B+NgtsDYUJXhsRkrfcx6IlgF7hJT32lNTB5JA5wD+v7z5X5rjrACkwgYZ3uhXL yqTuR9RNZTaox9LRNKlca3fIgi/ZiUBOJNgX+VyQz6rB0b+SYxGqcPyJoSd6rt5GzAN Qv95fiHq+yyxbuDXrvr3V2i3RdyrVs2swtdWTnMM= Received: by mx.zohomail.com with SMTPS id 1766062549961270.54454758878353; Thu, 18 Dec 2025 04:55:49 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:54:53 +0100 Subject: [PATCH v4 03/25] dt-bindings: ufs: mediatek,ufs: Add mt8196 variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-3-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 The MediaTek MT8196 SoC's UFS controller uses three additional clocks compared to the MT8195, and a different set of supplies. It is therefore not compatible with the MT8195. While it does have a AVDD09_UFS_1 pin in addition to the AVDD09_UFS pin, it appears that these two pins are commoned together, as the board schematic I have access to uses the same supply for both, and the downstream driver does not distinguish between the two supplies either. Add a compatible for it, and modify the binding correspondingly. Signed-off-by: Nicolas Frattaroli Acked-by: Conor Dooley Acked-by: Vinod Koul --- .../devicetree/bindings/ufs/mediatek,ufs.yaml | 58 ++++++++++++++++++= +++- 1 file changed, 57 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml b/Docu= mentation/devicetree/bindings/ufs/mediatek,ufs.yaml index e0aef3e5f56b..a82119ecbfe8 100644 --- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml @@ -16,10 +16,11 @@ properties: - mediatek,mt8183-ufshci - mediatek,mt8192-ufshci - mediatek,mt8195-ufshci + - mediatek,mt8196-ufshci =20 clocks: minItems: 1 - maxItems: 13 + maxItems: 16 =20 clock-names: minItems: 1 @@ -37,6 +38,9 @@ properties: - const: crypt_perf - const: ufs_rx_symbol0 - const: ufs_rx_symbol1 + - const: ufs_sel + - const: ufs_sel_min_src + - const: ufs_sel_max_src =20 operating-points-v2: true =20 @@ -131,9 +135,27 @@ allOf: properties: clocks: minItems: 13 + maxItems: 13 clock-names: minItems: 13 + maxItems: 13 avdd09-supply: false + - if: + properties: + compatible: + contains: + const: mediatek,mt8196-ufshci + then: + properties: + clocks: + minItems: 16 + maxItems: 16 + clock-names: + minItems: 16 + maxItems: 16 + avdd18-supply: false + required: + - operating-points-v2 =20 examples: - | @@ -183,3 +205,37 @@ examples: =20 mediatek,ufs-disable-mcq; }; + - | + #include + #include + + ufshci@16810000 { + compatible =3D "mediatek,mt8196-ufshci"; + reg =3D <0x16810000 0x2a00>; + interrupts =3D ; + + clocks =3D <&ufs_ao_clk 6>, <&ufs_ao_clk 7>, <&clk26m>, <&ufs_ao_c= lk 3>, + <&clk26m>, <&ufs_ao_clk 4>, <&ufs_ao_clk 0>, + <&topckgen 7>, <&topckgen 41>, <&topckgen 105>, <&topckge= n 83>, + <&ufs_ao_clk 1>, <&ufs_ao_clk 2>, <&topckgen 42>, + <&topckgen 84>, <&topckgen 102>; + clock-names =3D "ufs", "ufs_aes", "ufs_tick", "unipro_sysclk", + "unipro_tick", "unipro_mp_bclk", "ufs_tx_symbol", + "ufs_mem_sub", "crypt_mux", "crypt_lp", "crypt_perf", + "ufs_rx_symbol0", "ufs_rx_symbol1", "ufs_sel", + "ufs_sel_min_src", "ufs_sel_max_src"; + + operating-points-v2 =3D <&ufs_opp_table>; + + phys =3D <&ufsphy>; + + avdd09-supply =3D <&mt6363_vsram_modem>; + vcc-supply =3D <&mt6363_vemc>; + vccq-supply =3D <&mt6363_vufs12>; + + resets =3D <&ufs_ao_clk MT8196_UFSAO_RST1_UFS_UNIPRO>, + <&ufs_ao_clk MT8196_UFSAO_RST1_UFS_CRYPTO>, + <&ufs_ao_clk MT8196_UFSAO_RST1_UFSHCI>; + reset-names =3D "unipro", "crypto", "hci"; + mediatek,ufs-disable-mcq; + }; --=20 2.52.0