From nobody Mon Feb 9 16:08:20 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C1B033D6FE; Thu, 18 Dec 2025 12:58:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062697; cv=pass; b=sw5Zvm5wYDUYk7JvgQXWfMZoLuaReniRsb7MDIbYlLWk3f+mLZKmVrfJLP6q1/AXnwQrFfwuUe/CSIfFUyYcjElk21JrLfH0fKKK6XmK8AmsoDib+nUtI714Hh0DhQSvztIYLRkVHZO6Tx6uoWxrmJRFb66W12y1DR6mOMMJ9nA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062697; c=relaxed/simple; bh=hgHuv2VHrzANfpWGvJBTw/HX4ZeeOq9SNa/Kd+m35hs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V3ua+gxkEE4Bvj1YsbSCjetQC3uAkIefJ5ahllLJBr1/WPOXnO/F9pbQmJbX7IPfiOPULowrKr6DRWN96/r4lYdmhVraoMvY1U0AL0uWKH7PQrMsWjS9k/EcZYjz579lPud/3kTWmmbiK23oTrhpwpWiUzl4eS24yT51OfwH7lM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=Shw6aL9Z; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="Shw6aL9Z" ARC-Seal: i=1; a=rsa-sha256; t=1766062660; cv=none; d=zohomail.com; s=zohoarc; b=DJbWeAaUj9WSEIKeD+7z4xIEIwg1WHGw5sl87rt+imjJ+11WPTcI+ZwXE4Oi20mA5JaVzuKxmeeOQsOsBtm/xmHQl4vmDVfQ0fzTO6W4XigbeGCIVzB4fawq35qTehlj9fV5sQ9FBUV39OpvwgWf70nM5qPm2D+ZZZO+RtZQ7kA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766062660; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=kP6+tesLXT6b6oe8yL/PwiMt0IZtyIkk3FBpDPLGZwE=; b=A2W+zgXR8I4PP03V8yIbBaXtScXvvpC/IE004EChGUZ9WnGcjFl1mT3k9kp5fx4fGjTfvGqDf+5NO92SBud0/Lujdt3oZp2+BePUmA7Vm8oXkt6fCBl7mW8qI6/XcNSWh7LSwhPTIiWZqUq6SA7UAMHU70+gBq8zWbLzXteK1xk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1766062660; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=kP6+tesLXT6b6oe8yL/PwiMt0IZtyIkk3FBpDPLGZwE=; b=Shw6aL9ZZYU8f2qw1TB1B0HThItIk2Wqv0gB9mvnvQuDBb1TBjEgQmN5P31LB0ah X8s+4XJkjGtAZPrs/0Skb5sKU/NGpdTL/Y9GjgaItHNpMdRTsrTUgcnsyTIYnagfb5e 2X2u/QqKkLrY8+qEidHbcb9yyumaENk0ZSQVr3yo= Received: by mx.zohomail.com with SMTPS id 1766062658889766.5723795494483; Thu, 18 Dec 2025 04:57:38 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:55:10 +0100 Subject: [PATCH v4 20/25] scsi: ufs: mediatek: Don't acquire dvfsrc-vcore twice Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-20-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 As part of its featureset, the ufs-mediatek driver needs to play with an optional dvfsrc-vcore regulator for some of them. However, it currently does this by acquiring two different references to it in two different places, needlessly duplicating logic. Move reg_vcore to the host struct, acquire it in the same function as avdd09 is acquired, and rework the users of reg_vcore. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 73 +++++++++++++++++++------------------= ---- drivers/ufs/host/ufs-mediatek.h | 3 +- 2 files changed, 34 insertions(+), 42 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index b07776f45acb..a54c3aeb7bab 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -519,15 +519,13 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, = bool boost) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); struct ufs_mtk_crypt_cfg *cfg; - struct regulator *reg; int volt, ret; =20 - if (!ufs_mtk_is_boost_crypt_enabled(hba)) + if (!ufs_mtk_is_boost_crypt_enabled(hba) || !host->reg_vcore) return; =20 cfg =3D host->crypt; volt =3D cfg->vcore_volt; - reg =3D cfg->reg_vcore; =20 ret =3D clk_prepare_enable(cfg->clk_crypt_mux); if (ret) { @@ -537,7 +535,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bo= ol boost) } =20 if (boost) { - ret =3D regulator_set_voltage(reg, volt, INT_MAX); + ret =3D regulator_set_voltage(host->reg_vcore, volt, INT_MAX); if (ret) { dev_err(hba->dev, "%s: Failed to set vcore to %d: %pe\n", __func__, volt, ERR_PTR(ret)); @@ -548,7 +546,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bo= ol boost) if (ret) { dev_err(hba->dev, "%s: Failed to reparent clk_crypt_perf: %pe\n", __func__, ERR_PTR(ret)); - regulator_set_voltage(reg, 0, INT_MAX); + regulator_set_voltage(host->reg_vcore, 0, INT_MAX); goto out; } } else { @@ -559,7 +557,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bo= ol boost) goto out; } =20 - ret =3D regulator_set_voltage(reg, 0, INT_MAX); + ret =3D regulator_set_voltage(host->reg_vcore, 0, INT_MAX); if (ret) { dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n", __func__, ERR_PTR(ret)); @@ -576,16 +574,13 @@ static int ufs_mtk_init_boost_crypt(struct ufs_hba *h= ba) struct device *dev =3D hba->dev; int ret; =20 + if (!host->reg_vcore) + return 0; + cfg =3D devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL); if (!cfg) return -ENOMEM; =20 - cfg->reg_vcore =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); - if (IS_ERR(cfg->reg_vcore)) { - dev_err(dev, "Failed to get dvfsrc-vcore: %pe", cfg->reg_vcore); - return PTR_ERR(cfg->reg_vcore); - } - ret =3D of_property_read_u32(dev->of_node, "mediatek,boost-crypt-vcore-mi= n", &cfg->vcore_volt); if (ret) { @@ -891,7 +886,6 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) struct list_head *head =3D &hba->clk_list_head; struct ufs_clk_info *clki, *clki_tmp; struct device *dev =3D hba->dev; - struct regulator *reg; u32 volt; =20 /* @@ -932,16 +926,8 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) return; } =20 - /* - * Default get vcore if dts have these settings. - * No matter clock scaling support or not. (may disable by customer) - */ - reg =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); - if (IS_ERR(reg)) { - if (PTR_ERR(reg) !=3D -ENODEV) - dev_err(dev, "Failed to get dvfsrc-vcore: %pe\n", reg); + if (!host->reg_vcore) return; - } =20 if (of_property_read_u32(dev->of_node, "mediatek,clk-scale-up-vcore-min", &volt)) { @@ -949,12 +935,11 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) return; } =20 - host->mclk.reg_vcore =3D reg; host->mclk.vcore_volt =3D volt; =20 /* If default boot is max gear, request vcore */ - if (reg && volt && host->clk_scale_up) - if (regulator_set_voltage(reg, volt, INT_MAX)) + if (volt && host->clk_scale_up) + if (regulator_set_voltage(host->reg_vcore, volt, INT_MAX)) dev_err(hba->dev, "Failed to set vcore to %d\n", volt); } =20 @@ -1066,6 +1051,17 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host = *host) const struct ufs_mtk_soc_data *data =3D of_device_get_match_data(dev); int ret; =20 + host->reg_vcore =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); + if (IS_ERR(host->reg_vcore)) { + if (PTR_ERR(host->reg_vcore) !=3D -ENODEV) { + dev_err(dev, "Failed to get dvfsrc-vcore supply: %pe\n", + host->reg_vcore); + return PTR_ERR(host->reg_vcore); + } + + host->reg_vcore =3D NULL; + } + if (!data) return 0; =20 @@ -1099,14 +1095,13 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host= *host) =20 host->reg_avdd09 =3D devm_regulator_get_optional(dev, "avdd09"); if (IS_ERR(host->reg_avdd09)) { - if (PTR_ERR(host->reg_avdd09) =3D=3D -ENODEV) { - host->reg_avdd09 =3D NULL; - return 0; + if (PTR_ERR(host->reg_avdd09) !=3D -ENODEV) { + dev_err(dev, "Failed to get avdd09 regulator: %pe\n", + host->reg_avdd09); + return PTR_ERR(host->reg_avdd09); } =20 - dev_err(dev, "Failed to get avdd09 regulator: %pe\n", - host->reg_avdd09); - return PTR_ERR(host->reg_avdd09); + host->reg_avdd09 =3D NULL; } =20 return 0; @@ -1137,6 +1132,10 @@ static int ufs_mtk_init(struct ufs_hba *hba) host->hba =3D hba; ufshcd_set_variant(hba, host); =20 + err =3D ufs_mtk_get_supplies(host); + if (err) + goto out_variant_clear; + /* Initialize host capability */ ufs_mtk_init_host_caps(hba); =20 @@ -1191,10 +1190,6 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 ufs_mtk_init_clocks(hba); =20 - err =3D ufs_mtk_get_supplies(host); - if (err) - goto out_phy_exit; - /* * ufshcd_vops_init() is invoked after * ufshcd_setup_clock(true) in ufshcd_hba_init() thus @@ -1940,7 +1935,6 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, b= ool scale_up) struct ufs_mtk_clk *mclk =3D &host->mclk; struct ufs_clk_info *clki =3D mclk->ufs_sel_clki; struct ufs_clk_info *fde_clki =3D mclk->ufs_fde_clki; - struct regulator *reg; int volt, ret =3D 0; bool clk_bind_vcore =3D false; bool clk_fde_scale =3D false; @@ -1951,9 +1945,8 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, b= ool scale_up) if (!clki || !fde_clki) return; =20 - reg =3D host->mclk.reg_vcore; volt =3D host->mclk.vcore_volt; - if (reg && volt !=3D 0) + if (host->reg_vcore && volt) clk_bind_vcore =3D true; =20 if (mclk->ufs_fde_max_clki && mclk->ufs_fde_min_clki) @@ -1977,7 +1970,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, b= ool scale_up) =20 if (scale_up) { if (clk_bind_vcore) { - ret =3D regulator_set_voltage(reg, volt, INT_MAX); + ret =3D regulator_set_voltage(host->reg_vcore, volt, INT_MAX); if (ret) { dev_err(hba->dev, "Failed to set vcore to %d\n", volt); goto out; @@ -2017,7 +2010,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, b= ool scale_up) } =20 if (clk_bind_vcore) { - ret =3D regulator_set_voltage(reg, 0, INT_MAX); + ret =3D regulator_set_voltage(host->reg_vcore, 0, INT_MAX); if (ret) { dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n", __func__, ERR_PTR(ret)); diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index 5f096ed3f850..9586fe9c0441 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -141,7 +141,6 @@ enum ufs_mtk_host_caps { }; =20 struct ufs_mtk_crypt_cfg { - struct regulator *reg_vcore; struct clk *clk_crypt_perf; struct clk *clk_crypt_mux; struct clk *clk_crypt_lp; @@ -155,7 +154,6 @@ struct ufs_mtk_clk { struct ufs_clk_info *ufs_fde_clki; /* Mux */ struct ufs_clk_info *ufs_fde_max_clki; /* Max src */ struct ufs_clk_info *ufs_fde_min_clki; /* Min src */ - struct regulator *reg_vcore; int vcore_volt; }; =20 @@ -174,6 +172,7 @@ struct ufs_mtk_mcq_intr_info { struct ufs_mtk_host { struct phy *mphy; struct regulator *reg_avdd09; + struct regulator *reg_vcore; struct regulator_bulk_data *reg_misc; u8 num_reg_misc; struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS]; --=20 2.52.0