From nobody Mon Feb 9 04:42:19 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 442B3334C05; Thu, 18 Dec 2025 12:56:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062569; cv=pass; b=DOOKKKa/1jAziVBBh7C4KlmfQBwPr1zPJxPqmDUJWHc7qniMBd36LcZKLUwljGD2h2l/nmEGU37dFKxXc0u8OcZgpTmfIw9/4ltO/vKBKw/Vj3Mf0NfCe4Rv0GBcdnUJrYsMb2v7aswInJTOvCmlqTrktPVlTZPdIWkhQv8uynY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062569; c=relaxed/simple; bh=6NCLt1CkDaVVzz36N3PGq1kZUWkoy/C3UaYJFP8nz5U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BZafABNvl/ptl6feXu9t/wSu1lZRG66nuSqIjoeUShRwhSuUCfCgBzVDj2xGCCnK1xOpA9R9z3tOjJIhsmnK7pigCwYRCbyGSgASx963w2BB94JQ1mzW4o08VUr2ZAdAkPaWe4+WthHrzlkuBIX//ANspzyJK663s2KnyswI+UM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=Tfa5p2/V; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="Tfa5p2/V" ARC-Seal: i=1; a=rsa-sha256; t=1766062544; cv=none; d=zohomail.com; s=zohoarc; b=EJc1zmuzyelcc6GiVPmYsyzeENAV/u2zP67XPLwRzxQiy0hwW4cWggsmHaASsa3TY7EAF0ntvwQMxgyzGIxuIIwWpHSkh732AgO4DsZRUc7mvMe4Bw2vkVlpmVM/xs8K1VrAJS99ZJdHpLQqo0rai7sarNdk7YY9BD7NwQSwdhI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766062544; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=cyIuwDWXNEOeb22XF+MzmGV8Uy378L9Dzlhhn/BXHQY=; b=hFGwaoTe89ZqbijZiPxgwvUZX9/CDAlacd0xeOWSx5tSrHhuyjJ/rSirqcAWjB3INwF5/2jBxuO8HWZBKJbJjC5EhK5OJuvkYwWeIDXf0GT3wrx8toYpc60ZBX/ceCGXf+Nlrp2mhbyHeLM/WxF28RG3+DXGJI5Pvlo3PzhzFH4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1766062544; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=cyIuwDWXNEOeb22XF+MzmGV8Uy378L9Dzlhhn/BXHQY=; b=Tfa5p2/VCao6Gn2gCedJh7xRveTYJuaysaxZfe2Boax/WEcgrw6UI5UOA2u7wo8T xiVk+mu4bEwpGAwBvgm7jqaKM+9mCXlb4r14Hc9tFrbFxb8onWV+aXFXTvECpONLbHj AHqWmhpI4B8oEB+L3xDVv1oYku7Ww8fkEIK9jzpg= Received: by mx.zohomail.com with SMTPS id 1766062543544710.8872489757659; Thu, 18 Dec 2025 04:55:43 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:54:52 +0100 Subject: [PATCH v4 02/25] dt-bindings: ufs: mediatek,ufs: Complete the binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-2-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 As it stands, the mediatek,ufs.yaml binding is startlingly incomplete. Its one example, which is the only real "user" of this binding in mainline, uses the deprecated freq-table-hz property. The resets, of which there are three optional ones, are completely absent. The clock description for MT8195 is incomplete, as is the one for MT8192. It's not known if the one clock binding for MT8183 is even correct, but I do not have access to the necessary code and documentation to find this out myself. The power supply situation is not much better; the binding describes one required power supply, but it's the UFS card supply, not any of the supplies feeding the controller silicon. No second example is present in the binding, making verification difficult. Disallow freq-table-hz and move to operating-points-v2. It's fine to break compatibility here, as the binding is currently unused and would be impossible to correctly use in its current state. Add the three resets and the corresponding reset-names property. These resets appear to be optional, i.e. not required for the functioning of the device. Move the list of clock names out of the if condition, and expand it for the confirmed clocks I could find by cross-referencing several clock drivers. For MT8195, increase the minimum number of clocks to include the crypt and rx_symbol ones, as they're internal to the SoC and should always be present, and should therefore not be omitted. MT8192 gets to have at least 3 clocks, as these were the ones I could quickly confirm from a glance at various trees. I can't say this was an exhaustive search though, but it's better than the current situation. Properly document all supplies, with which pin name on the SoCs they supply. Complete the example with them. Also add a MT8195 example to the binding, using supply labels that I am pretty sure would be the right ones for e.g. the Radxa NIO 12L. Signed-off-by: Nicolas Frattaroli Acked-by: Vinod Koul Reviewed-by: Conor Dooley --- .../devicetree/bindings/ufs/mediatek,ufs.yaml | 117 +++++++++++++++++= +--- 1 file changed, 100 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml b/Docu= mentation/devicetree/bindings/ufs/mediatek,ufs.yaml index 15c347f5e660..e0aef3e5f56b 100644 --- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml @@ -19,11 +19,28 @@ properties: =20 clocks: minItems: 1 - maxItems: 8 + maxItems: 13 =20 clock-names: minItems: 1 - maxItems: 8 + items: + - const: ufs + - const: ufs_aes + - const: ufs_tick + - const: unipro_sysclk + - const: unipro_tick + - const: unipro_mp_bclk + - const: ufs_tx_symbol + - const: ufs_mem_sub + - const: crypt_mux + - const: crypt_lp + - const: crypt_perf + - const: ufs_rx_symbol0 + - const: ufs_rx_symbol1 + + operating-points-v2: true + + freq-table-hz: false =20 phys: maxItems: 1 @@ -31,8 +48,36 @@ properties: reg: maxItems: 1 =20 + resets: + items: + - description: reset for the UniPro layer + - description: reset for the cryptography engine + - description: reset for the host controller + + reset-names: + items: + - const: unipro + - const: crypto + - const: hci + + avdd09-supply: + description: Phandle to the 0.9V supply powering the AVDD09_UFS pin + + avdd12-supply: + description: Phandle to the 1.2V supply powering the AVDD12_UFS pin + + avdd12-ckbuf-supply: + description: Phandle to the 1.2V supply powering the AVDD12_CKBUF_UFS = pin + + avdd18-supply: + description: Phandle to the 1.8V supply powering the AVDD18_UFS pin + vcc-supply: true =20 + vccq-supply: true + + vccq2-supply: true + mediatek,ufs-disable-mcq: $ref: /schemas/types.yaml#/definitions/flag description: The mask to disable MCQ (Multi-Circular Queue) for UFS ho= st. @@ -54,29 +99,41 @@ allOf: properties: compatible: contains: - enum: - - mediatek,mt8195-ufshci + const: mediatek,mt8183-ufshci then: properties: clocks: - minItems: 8 + maxItems: 1 clock-names: items: - const: ufs - - const: ufs_aes - - const: ufs_tick - - const: unipro_sysclk - - const: unipro_tick - - const: unipro_mp_bclk - - const: ufs_tx_symbol - - const: ufs_mem_sub - else: + avdd12-ckbuf-supply: false + - if: + properties: + compatible: + contains: + const: mediatek,mt8192-ufshci + then: properties: clocks: - maxItems: 1 + minItems: 3 + maxItems: 3 + clocks-names: + minItems: 3 + maxItems: 3 + avdd09-supply: false + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-ufshci + then: + properties: + clocks: + minItems: 13 clock-names: - items: - - const: ufs + minItems: 13 + avdd09-supply: false =20 examples: - | @@ -95,8 +152,34 @@ examples: =20 clocks =3D <&infracfg_ao CLK_INFRA_UFS>; clock-names =3D "ufs"; - freq-table-hz =3D <0 0>; =20 vcc-supply =3D <&mt_pmic_vemc_ldo_reg>; }; }; + - | + ufshci@11270000 { + compatible =3D "mediatek,mt8195-ufshci"; + reg =3D <0x11270000 0x2300>; + interrupts =3D ; + phys =3D <&ufsphy>; + clocks =3D <&infracfg_ao 63>, <&infracfg_ao 64>, <&infracfg_ao 65>, + <&infracfg_ao 54>, <&infracfg_ao 55>, + <&infracfg_ao 56>, <&infracfg_ao 90>, + <&infracfg_ao 93>, <&topckgen 60>, <&topckgen 152>, + <&topckgen 125>, <&topckgen 212>, <&topckgen 215>; + clock-names =3D "ufs", "ufs_aes", "ufs_tick", + "unipro_sysclk", "unipro_tick", + "unipro_mp_bclk", "ufs_tx_symbol", + "ufs_mem_sub", "crypt_mux", "crypt_lp", + "crypt_perf", "ufs_rx_symbol0", "ufs_rx_symbol1"; + + operating-points-v2 =3D <&ufs_opp_table>; + + avdd12-supply =3D <&mt6359_vrf12_ldo_reg>; + avdd12-ckbuf-supply =3D <&mt6359_vbbck_ldo_reg>; + avdd18-supply =3D <&mt6359_vio18_ldo_reg>; + vcc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vccq2-supply =3D <&mt6359_vufs_ldo_reg>; + + mediatek,ufs-disable-mcq; + }; --=20 2.52.0