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Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 The MediaTek MT8196 SoC includes an M-PHY compatible with the already existing mt8183 binding. However, one omission from the original binding was that all of these variants may have an optional reset. Add the new compatible, and also the resets property, with an example. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli Acked-by: Conor Dooley --- .../devicetree/bindings/phy/mediatek,ufs-phy.yaml | 16 ++++++++++++= ++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml b/= Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml index 6e2edd43fc2a..ee71dfa4e0c0 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: - mediatek,mt8195-ufsphy + - mediatek,mt8196-ufsphy - const: mediatek,mt8183-ufsphy - const: mediatek,mt8183-ufsphy =20 @@ -43,6 +44,10 @@ properties: - const: unipro - const: mp =20 + resets: + items: + - description: Optional UFS M-PHY reset. + "#phy-cells": const: 0 =20 @@ -66,5 +71,16 @@ examples: clock-names =3D "unipro", "mp"; #phy-cells =3D <0>; }; + - | + #include + ufs-phy@16800000 { + compatible =3D "mediatek,mt8196-ufsphy", "mediatek,mt8183-ufsphy"; + reg =3D <0x16800000 0x10000>; + clocks =3D <&ufs_ao_clk 3>, + <&ufs_ao_clk 5>; + clock-names =3D "unipro", "mp"; + resets =3D <&ufs_ao_clk MT8196_UFSAO_RST0_UFS_MPHY>; + #phy-cells =3D <0>; + }; =20 ... --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 442B3334C05; Thu, 18 Dec 2025 12:56:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062569; cv=pass; b=DOOKKKa/1jAziVBBh7C4KlmfQBwPr1zPJxPqmDUJWHc7qniMBd36LcZKLUwljGD2h2l/nmEGU37dFKxXc0u8OcZgpTmfIw9/4ltO/vKBKw/Vj3Mf0NfCe4Rv0GBcdnUJrYsMb2v7aswInJTOvCmlqTrktPVlTZPdIWkhQv8uynY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062569; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=cyIuwDWXNEOeb22XF+MzmGV8Uy378L9Dzlhhn/BXHQY=; b=Tfa5p2/VCao6Gn2gCedJh7xRveTYJuaysaxZfe2Boax/WEcgrw6UI5UOA2u7wo8T xiVk+mu4bEwpGAwBvgm7jqaKM+9mCXlb4r14Hc9tFrbFxb8onWV+aXFXTvECpONLbHj AHqWmhpI4B8oEB+L3xDVv1oYku7Ww8fkEIK9jzpg= Received: by mx.zohomail.com with SMTPS id 1766062543544710.8872489757659; Thu, 18 Dec 2025 04:55:43 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:54:52 +0100 Subject: [PATCH v4 02/25] dt-bindings: ufs: mediatek,ufs: Complete the binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-2-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 As it stands, the mediatek,ufs.yaml binding is startlingly incomplete. Its one example, which is the only real "user" of this binding in mainline, uses the deprecated freq-table-hz property. The resets, of which there are three optional ones, are completely absent. The clock description for MT8195 is incomplete, as is the one for MT8192. It's not known if the one clock binding for MT8183 is even correct, but I do not have access to the necessary code and documentation to find this out myself. The power supply situation is not much better; the binding describes one required power supply, but it's the UFS card supply, not any of the supplies feeding the controller silicon. No second example is present in the binding, making verification difficult. Disallow freq-table-hz and move to operating-points-v2. It's fine to break compatibility here, as the binding is currently unused and would be impossible to correctly use in its current state. Add the three resets and the corresponding reset-names property. These resets appear to be optional, i.e. not required for the functioning of the device. Move the list of clock names out of the if condition, and expand it for the confirmed clocks I could find by cross-referencing several clock drivers. For MT8195, increase the minimum number of clocks to include the crypt and rx_symbol ones, as they're internal to the SoC and should always be present, and should therefore not be omitted. MT8192 gets to have at least 3 clocks, as these were the ones I could quickly confirm from a glance at various trees. I can't say this was an exhaustive search though, but it's better than the current situation. Properly document all supplies, with which pin name on the SoCs they supply. Complete the example with them. Also add a MT8195 example to the binding, using supply labels that I am pretty sure would be the right ones for e.g. the Radxa NIO 12L. Signed-off-by: Nicolas Frattaroli Reviewed-by: Conor Dooley --- .../devicetree/bindings/ufs/mediatek,ufs.yaml | 117 +++++++++++++++++= +--- 1 file changed, 100 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml b/Docu= mentation/devicetree/bindings/ufs/mediatek,ufs.yaml index 15c347f5e660..e0aef3e5f56b 100644 --- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml @@ -19,11 +19,28 @@ properties: =20 clocks: minItems: 1 - maxItems: 8 + maxItems: 13 =20 clock-names: minItems: 1 - maxItems: 8 + items: + - const: ufs + - const: ufs_aes + - const: ufs_tick + - const: unipro_sysclk + - const: unipro_tick + - const: unipro_mp_bclk + - const: ufs_tx_symbol + - const: ufs_mem_sub + - const: crypt_mux + - const: crypt_lp + - const: crypt_perf + - const: ufs_rx_symbol0 + - const: ufs_rx_symbol1 + + operating-points-v2: true + + freq-table-hz: false =20 phys: maxItems: 1 @@ -31,8 +48,36 @@ properties: reg: maxItems: 1 =20 + resets: + items: + - description: reset for the UniPro layer + - description: reset for the cryptography engine + - description: reset for the host controller + + reset-names: + items: + - const: unipro + - const: crypto + - const: hci + + avdd09-supply: + description: Phandle to the 0.9V supply powering the AVDD09_UFS pin + + avdd12-supply: + description: Phandle to the 1.2V supply powering the AVDD12_UFS pin + + avdd12-ckbuf-supply: + description: Phandle to the 1.2V supply powering the AVDD12_CKBUF_UFS = pin + + avdd18-supply: + description: Phandle to the 1.8V supply powering the AVDD18_UFS pin + vcc-supply: true =20 + vccq-supply: true + + vccq2-supply: true + mediatek,ufs-disable-mcq: $ref: /schemas/types.yaml#/definitions/flag description: The mask to disable MCQ (Multi-Circular Queue) for UFS ho= st. @@ -54,29 +99,41 @@ allOf: properties: compatible: contains: - enum: - - mediatek,mt8195-ufshci + const: mediatek,mt8183-ufshci then: properties: clocks: - minItems: 8 + maxItems: 1 clock-names: items: - const: ufs - - const: ufs_aes - - const: ufs_tick - - const: unipro_sysclk - - const: unipro_tick - - const: unipro_mp_bclk - - const: ufs_tx_symbol - - const: ufs_mem_sub - else: + avdd12-ckbuf-supply: false + - if: + properties: + compatible: + contains: + const: mediatek,mt8192-ufshci + then: properties: clocks: - maxItems: 1 + minItems: 3 + maxItems: 3 + clocks-names: + minItems: 3 + maxItems: 3 + avdd09-supply: false + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-ufshci + then: + properties: + clocks: + minItems: 13 clock-names: - items: - - const: ufs + minItems: 13 + avdd09-supply: false =20 examples: - | @@ -95,8 +152,34 @@ examples: =20 clocks =3D <&infracfg_ao CLK_INFRA_UFS>; clock-names =3D "ufs"; - freq-table-hz =3D <0 0>; =20 vcc-supply =3D <&mt_pmic_vemc_ldo_reg>; }; }; + - | + ufshci@11270000 { + compatible =3D "mediatek,mt8195-ufshci"; + reg =3D <0x11270000 0x2300>; + interrupts =3D ; + phys =3D <&ufsphy>; + clocks =3D <&infracfg_ao 63>, <&infracfg_ao 64>, <&infracfg_ao 65>, + <&infracfg_ao 54>, <&infracfg_ao 55>, + <&infracfg_ao 56>, <&infracfg_ao 90>, + <&infracfg_ao 93>, <&topckgen 60>, <&topckgen 152>, + <&topckgen 125>, <&topckgen 212>, <&topckgen 215>; + clock-names =3D "ufs", "ufs_aes", "ufs_tick", + "unipro_sysclk", "unipro_tick", + "unipro_mp_bclk", "ufs_tx_symbol", + "ufs_mem_sub", "crypt_mux", "crypt_lp", + "crypt_perf", "ufs_rx_symbol0", "ufs_rx_symbol1"; + + operating-points-v2 =3D <&ufs_opp_table>; + + avdd12-supply =3D <&mt6359_vrf12_ldo_reg>; + avdd12-ckbuf-supply =3D <&mt6359_vbbck_ldo_reg>; + avdd18-supply =3D <&mt6359_vio18_ldo_reg>; + vcc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vccq2-supply =3D <&mt6359_vufs_ldo_reg>; + + mediatek,ufs-disable-mcq; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-3-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 The MediaTek MT8196 SoC's UFS controller uses three additional clocks compared to the MT8195, and a different set of supplies. It is therefore not compatible with the MT8195. While it does have a AVDD09_UFS_1 pin in addition to the AVDD09_UFS pin, it appears that these two pins are commoned together, as the board schematic I have access to uses the same supply for both, and the downstream driver does not distinguish between the two supplies either. Add a compatible for it, and modify the binding correspondingly. Signed-off-by: Nicolas Frattaroli Acked-by: Conor Dooley --- .../devicetree/bindings/ufs/mediatek,ufs.yaml | 58 ++++++++++++++++++= +++- 1 file changed, 57 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml b/Docu= mentation/devicetree/bindings/ufs/mediatek,ufs.yaml index e0aef3e5f56b..a82119ecbfe8 100644 --- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml @@ -16,10 +16,11 @@ properties: - mediatek,mt8183-ufshci - mediatek,mt8192-ufshci - mediatek,mt8195-ufshci + - mediatek,mt8196-ufshci =20 clocks: minItems: 1 - maxItems: 13 + maxItems: 16 =20 clock-names: minItems: 1 @@ -37,6 +38,9 @@ properties: - const: crypt_perf - const: ufs_rx_symbol0 - const: ufs_rx_symbol1 + - const: ufs_sel + - const: ufs_sel_min_src + - const: ufs_sel_max_src =20 operating-points-v2: true =20 @@ -131,9 +135,27 @@ allOf: properties: clocks: minItems: 13 + maxItems: 13 clock-names: minItems: 13 + maxItems: 13 avdd09-supply: false + - if: + properties: + compatible: + contains: + const: mediatek,mt8196-ufshci + then: + properties: + clocks: + minItems: 16 + maxItems: 16 + clock-names: + minItems: 16 + maxItems: 16 + avdd18-supply: false + required: + - operating-points-v2 =20 examples: - | @@ -183,3 +205,37 @@ examples: =20 mediatek,ufs-disable-mcq; }; + - | + #include + #include + + ufshci@16810000 { + compatible =3D "mediatek,mt8196-ufshci"; + reg =3D <0x16810000 0x2a00>; + interrupts =3D ; + + clocks =3D <&ufs_ao_clk 6>, <&ufs_ao_clk 7>, <&clk26m>, <&ufs_ao_c= lk 3>, + <&clk26m>, <&ufs_ao_clk 4>, <&ufs_ao_clk 0>, + <&topckgen 7>, <&topckgen 41>, <&topckgen 105>, <&topckge= n 83>, + <&ufs_ao_clk 1>, <&ufs_ao_clk 2>, <&topckgen 42>, + <&topckgen 84>, <&topckgen 102>; + clock-names =3D "ufs", "ufs_aes", "ufs_tick", "unipro_sysclk", + "unipro_tick", "unipro_mp_bclk", "ufs_tx_symbol", + "ufs_mem_sub", "crypt_mux", "crypt_lp", "crypt_perf", + "ufs_rx_symbol0", "ufs_rx_symbol1", "ufs_sel", + "ufs_sel_min_src", "ufs_sel_max_src"; + + operating-points-v2 =3D <&ufs_opp_table>; + + phys =3D <&ufsphy>; + + avdd09-supply =3D <&mt6363_vsram_modem>; + vcc-supply =3D <&mt6363_vemc>; + vccq-supply =3D <&mt6363_vufs12>; + + resets =3D <&ufs_ao_clk MT8196_UFSAO_RST1_UFS_UNIPRO>, + <&ufs_ao_clk MT8196_UFSAO_RST1_UFS_CRYPTO>, + <&ufs_ao_clk MT8196_UFSAO_RST1_UFSHCI>; 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Thu, 18 Dec 2025 04:55:56 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:54:54 +0100 Subject: [PATCH v4 04/25] scsi: ufs: mediatek: Move MTK_SIP_UFS_CONTROL to mtk_sip_svc.h Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-4-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 SMC commands used by multiple drivers need to live in a shared header file somewhere to avoid code duplication. In order to rework the MPHY reset control to be in the phy-mtk-ufs.c driver, both ufs-mediatek and the phy driver need access to this command. Move it to mtk_sip_svc.h, where other such command definitions already live. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek-sip.h | 1 - include/linux/soc/mediatek/mtk_sip_svc.h | 3 +++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-med= iatek-sip.h index 7d17aedf6fb8..d627dfb4a766 100644 --- a/drivers/ufs/host/ufs-mediatek-sip.h +++ b/drivers/ufs/host/ufs-mediatek-sip.h @@ -11,7 +11,6 @@ /* * SiP (Slicon Partner) commands */ -#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) #define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0) #define UFS_MTK_SIP_DEVICE_RESET BIT(1) #define UFS_MTK_SIP_CRYPTO_CTRL BIT(2) diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/m= ediatek/mtk_sip_svc.h index abe24a73ee19..7265ff2a6e2a 100644 --- a/include/linux/soc/mediatek/mtk_sip_svc.h +++ b/include/linux/soc/mediatek/mtk_sip_svc.h @@ -22,6 +22,9 @@ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \ ARM_SMCCC_OWNER_SIP, fn_id) =20 +/* UFS related SMC call */ +#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) + /* DVFSRC SMC calls */ #define MTK_SIP_DVFSRC_VCOREFS_CONTROL MTK_SIP_SMC_CMD(0x506) =20 --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A00723358B5; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-5-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 The MediaTek UFS PHY supports PHY resets. Until now, they've been implemented in the UFS host driver. Since they were never documented in the UFS HCI node's DT bindings, and no mainline DT uses it, it's fine if it's moved to the correct location, which is the PHY driver. Implement the MPHY reset logic in this driver and expose it through the phy subsystem's reset op. The reset itself is optional, as judging by other mainline devices that use this hardware, it's not required for the device to function. If no reset is present, the reset op returns -EOPNOTSUPP, which means that the ufshci driver can detect it's present and not double sleep in its own reset function, where it will call the phy reset. Reviewed-by: Philipp Zabel Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli --- drivers/phy/mediatek/phy-mtk-ufs.c | 71 ++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 71 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-ufs.c b/drivers/phy/mediatek/phy-= mtk-ufs.c index 0cb5a25b1b7a..48f8e4dbf928 100644 --- a/drivers/phy/mediatek/phy-mtk-ufs.c +++ b/drivers/phy/mediatek/phy-mtk-ufs.c @@ -4,6 +4,7 @@ * Author: Stanley Chu */ =20 +#include #include #include #include @@ -11,6 +12,8 @@ #include #include #include +#include +#include =20 #include "phy-mtk-io.h" =20 @@ -36,9 +39,17 @@ =20 #define UFSPHY_CLKS_CNT 2 =20 +#define UFS_MTK_SIP_MPHY_CTRL BIT(8) + +enum ufs_mtk_mphy_op { + UFS_MPHY_BACKUP =3D 0, + UFS_MPHY_RESTORE +}; + struct ufs_mtk_phy { struct device *dev; void __iomem *mmio; + struct reset_control *reset; struct clk_bulk_data clks[UFSPHY_CLKS_CNT]; }; =20 @@ -141,9 +152,59 @@ static int ufs_mtk_phy_power_off(struct phy *generic_p= hy) return 0; } =20 +static int ufs_mtk_phy_ctrl(struct ufs_mtk_phy *phy, enum ufs_mtk_mphy_op = op) +{ + struct arm_smccc_res res; + + arm_smccc_smc(MTK_SIP_UFS_CONTROL, UFS_MTK_SIP_MPHY_CTRL, op, + 0, 0, 0, 0, 0, &res); + + switch (res.a0) { + case SMCCC_RET_NOT_SUPPORTED: + return -EOPNOTSUPP; + case SMCCC_RET_INVALID_PARAMETER: + return -EINVAL; + default: + return 0; + } +} + +static int ufs_mtk_phy_reset(struct phy *generic_phy) +{ + struct ufs_mtk_phy *phy =3D get_ufs_mtk_phy(generic_phy); + int ret; + + if (!phy->reset) + return -EOPNOTSUPP; + + ret =3D reset_control_assert(phy->reset); + if (ret) + return ret; + + usleep_range(100, 110); + + ret =3D reset_control_deassert(phy->reset); + if (ret) + return ret; + + /* + * To avoid double-sleep and other unintended side-effects in the ufshci + * driver, don't return the phy_ctrl retval here, but just return -EPROTO. + */ + ret =3D ufs_mtk_phy_ctrl(phy, UFS_MPHY_RESTORE); + if (ret) { + dev_err(phy->dev, "UFS_MPHY_RESTORE SMC command failed: %pe\n", + ERR_PTR(ret)); + return -EPROTO; + } + + return 0; +} + static const struct phy_ops ufs_mtk_phy_ops =3D { .power_on =3D ufs_mtk_phy_power_on, .power_off =3D ufs_mtk_phy_power_off, + .reset =3D ufs_mtk_phy_reset, .owner =3D THIS_MODULE, }; =20 @@ -163,8 +224,18 @@ static int ufs_mtk_phy_probe(struct platform_device *p= dev) if (IS_ERR(phy->mmio)) return PTR_ERR(phy->mmio); =20 + phy->reset =3D devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(phy->reset)) + return dev_err_probe(dev, PTR_ERR(phy->reset), "Failed to get reset\n"); + phy->dev =3D dev; =20 + if (phy->reset) { + ret =3D ufs_mtk_phy_ctrl(phy, UFS_MPHY_BACKUP); + if (ret) + return dev_err_probe(dev, ret, "Failed to back up MPHY\n"); + } + ret =3D ufs_mtk_phy_clk_init(phy); if (ret) return ret; --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1388D334C05; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-6-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Rework the reset control getting in the driver's probe function to use the bulk reset APIs. Use the optional variant instead of defaulting to NULL if the resets fail, so that absent resets can be distinguished from erroneous resets. Also remove all remnants of the MPHY reset ever having lived in this driver. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Reviewed-by: Philipp Zabel Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek-sip.h | 8 ---- drivers/ufs/host/ufs-mediatek.c | 78 ++++++++++++++++++---------------= ---- drivers/ufs/host/ufs-mediatek.h | 7 ++-- 3 files changed, 42 insertions(+), 51 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-med= iatek-sip.h index d627dfb4a766..256598cc3b5b 100644 --- a/drivers/ufs/host/ufs-mediatek-sip.h +++ b/drivers/ufs/host/ufs-mediatek-sip.h @@ -31,11 +31,6 @@ enum ufs_mtk_vcc_num { UFS_VCC_MAX }; =20 -enum ufs_mtk_mphy_op { - UFS_MPHY_BACKUP =3D 0, - UFS_MPHY_RESTORE -}; - /* * SMC call wrapper function */ @@ -84,9 +79,6 @@ static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s) #define ufs_mtk_device_pwr_ctrl(on, ufs_version, res) \ ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_version) =20 -#define ufs_mtk_mphy_ctrl(op, res) \ - ufs_mtk_smc(UFS_MTK_SIP_MPHY_CTRL, &(res), op) - #define ufs_mtk_mtcmos_ctrl(op, res) \ ufs_mtk_smc(UFS_MTK_SIP_MTCMOS_CTRL, &(res), op) =20 diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index ecbbf52bf734..d1554701793e 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -93,6 +93,12 @@ static const char *const ufs_uic_dl_err_str[] =3D { "PA_INIT" }; =20 +static const char *const ufs_reset_names[] =3D { + "unipro", + "crypto", + "hci", +}; + static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); @@ -203,49 +209,45 @@ static void ufs_mtk_crypto_enable(struct ufs_hba *hba) static void ufs_mtk_host_reset(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); - struct arm_smccc_res res; - - reset_control_assert(host->hci_reset); - reset_control_assert(host->crypto_reset); - reset_control_assert(host->unipro_reset); - reset_control_assert(host->mphy_reset); - - usleep_range(100, 110); + int ret; =20 - reset_control_deassert(host->unipro_reset); - reset_control_deassert(host->crypto_reset); - reset_control_deassert(host->hci_reset); - reset_control_deassert(host->mphy_reset); + ret =3D reset_control_bulk_assert(MTK_UFS_NUM_RESETS, host->resets); + if (ret) + dev_warn(hba->dev, "Host reset assert failed: %pe\n", ERR_PTR(ret)); =20 - /* restore mphy setting aftre mphy reset */ - if (host->mphy_reset) - ufs_mtk_mphy_ctrl(UFS_MPHY_RESTORE, res); -} + ret =3D phy_reset(host->mphy); =20 -static void ufs_mtk_init_reset_control(struct ufs_hba *hba, - struct reset_control **rc, - char *str) -{ - *rc =3D devm_reset_control_get(hba->dev, str); - if (IS_ERR(*rc)) { - dev_info(hba->dev, "Failed to get reset control %s: %ld\n", - str, PTR_ERR(*rc)); - *rc =3D NULL; + /* + * Only sleep if MPHY doesn't have a reset implemented (which already + * sleeps) or the PHY reset function failed somehow, just to be safe + */ + if (ret) { + usleep_range(100, 110); + if (ret !=3D -EOPNOTSUPP) + dev_warn(hba->dev, "PHY reset failed: %pe\n", ERR_PTR(ret)); } + + ret =3D reset_control_bulk_deassert(MTK_UFS_NUM_RESETS, host->resets); + if (ret) + dev_warn(hba->dev, "Host reset deassert failed: %pe\n", ERR_PTR(ret)); } =20 -static void ufs_mtk_init_reset(struct ufs_hba *hba) +static int ufs_mtk_init_reset(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); + int ret, i; + + for (i =3D 0; i < MTK_UFS_NUM_RESETS; i++) + host->resets[i].id =3D ufs_reset_names[i]; =20 - ufs_mtk_init_reset_control(hba, &host->hci_reset, - "hci_rst"); - ufs_mtk_init_reset_control(hba, &host->unipro_reset, - "unipro_rst"); - ufs_mtk_init_reset_control(hba, &host->crypto_reset, - "crypto_rst"); - ufs_mtk_init_reset_control(hba, &host->mphy_reset, - "mphy_rst"); + ret =3D devm_reset_control_bulk_get_optional_exclusive(hba->dev, MTK_UFS_= NUM_RESETS, + host->resets); + if (ret) { + dev_err(hba->dev, "Failed to get resets: %pe\n", ERR_PTR(ret)); + return ret; + } + + return 0; } =20 static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba, @@ -1247,11 +1249,9 @@ static int ufs_mtk_init(struct ufs_hba *hba) if (err) goto out_variant_clear; =20 - ufs_mtk_init_reset(hba); - - /* backup mphy setting if mphy can reset */ - if (host->mphy_reset) - ufs_mtk_mphy_ctrl(UFS_MPHY_BACKUP, res); + err =3D ufs_mtk_init_reset(hba); + if (err) + goto out_variant_clear; =20 /* Enable runtime autosuspend */ hba->caps |=3D UFSHCD_CAP_RPM_AUTOSUSPEND; diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index 9747277f11e8..4fce29d131d1 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -7,12 +7,14 @@ #define _UFS_MEDIATEK_H =20 #include +#include =20 /* * MCQ define and struct */ #define UFSHCD_MAX_Q_NR 8 #define MTK_MCQ_INVALID_IRQ 0xFFFF +#define MTK_UFS_NUM_RESETS 3 =20 /* REG_UFS_MMIO_OPT_CTRL_0 160h */ #define EHS_EN BIT(0) @@ -175,10 +177,7 @@ struct ufs_mtk_mcq_intr_info { struct ufs_mtk_host { struct phy *mphy; struct regulator *reg_va09; - struct reset_control *hci_reset; - struct reset_control *unipro_reset; - struct reset_control *crypto_reset; - struct reset_control *mphy_reset; + struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS]; struct ufs_hba *hba; struct ufs_mtk_crypt_cfg *crypt; struct ufs_mtk_clk mclk; --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5410D335070; Thu, 18 Dec 2025 12:57:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062630; cv=pass; b=nI0qUZuvV+YcVPUmaK5u+npG1z2bxjY9HT84zHJJtGkbNrpSrHkKDDuDzRXDV34qpz0BM2DLmDdMcFKFpvP3bfNSRWatCfuwOLPeIvBvLYhFv5Yjkr1Bpx/4MDVL8gsttsG65SbM63iBmrcoOnJ39ZjQfP8VztrfyzsL8LOU8l4= ARC-Message-Signature: i=2; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=63TKGqL6C4TGtRj92HHlbCGShqRReqCKXYiYAqxc0lU=; b=gYQHeghrxl4Lz8tY63nEAdzdYiaE8eK1e6MNnlcN6lxW67SEjSo/fczo/qZeywqQ TiWSHexuFE66pJmCxxVUMc0IUka6ZjjFIPc+5FevegNywhSrZJbIyTiS8gn2p3yPemd 2YDMp2ZIlz70PT2DvI2TOe58Nt5Rczn2GIllLO/g= Received: by mx.zohomail.com with SMTPS id 1766062575671860.20272978435; Thu, 18 Dec 2025 04:56:15 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:54:57 +0100 Subject: [PATCH v4 07/25] scsi: ufs: mediatek: Rework 0.9V regulator Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-7-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 The mediatek UFS host driver does some pretty bad stuff with regards to the 0.9V regulator. Instead of just checking for the presence of the regulator, it adds a cap if it's there, and then checks for the cap. It also sleeps to stabilise the supply after enabling the regulator, which is something that should be done by the regulator framework with the appropriate delay properties in the DTS instead of random sleeps in the driver code. Rework this code and rename it to the avdd09 name I've chosen in the binding for this supply name, instead of the downstream "va09" name that isn't used by the datasheets for any of these chips. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 153 ++++++++++++++++++++++++++----------= ---- drivers/ufs/host/ufs-mediatek.h | 3 +- 2 files changed, 101 insertions(+), 55 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index d1554701793e..a7aab2332ef2 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -38,6 +38,10 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool= scale_up); #define MAX_SUPP_MAC 64 #define MCQ_QUEUE_OFFSET(c) ((((c) >> 16) & 0xFF) * 0x200) =20 +struct ufs_mtk_soc_data { + bool has_avdd09; +}; + static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] =3D { { .wmanufacturerid =3D UFS_ANY_VENDOR, .model =3D UFS_ANY_MODEL, @@ -48,13 +52,6 @@ static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = =3D { {} }; =20 -static const struct of_device_id ufs_mtk_of_match[] =3D { - { .compatible =3D "mediatek,mt8183-ufshci" }, - { .compatible =3D "mediatek,mt8195-ufshci" }, - {}, -}; -MODULE_DEVICE_TABLE(of, ufs_mtk_of_match); - /* * Details of UIC Errors */ @@ -106,13 +103,6 @@ static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_= hba *hba) return host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE; } =20 -static bool ufs_mtk_is_va09_supported(struct ufs_hba *hba) -{ - struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); - - return host->caps & UFS_MTK_CAP_VA09_PWR_CTRL; -} - static bool ufs_mtk_is_broken_vcc(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); @@ -506,44 +496,70 @@ static int ufs_mtk_wait_link_state(struct ufs_hba *hb= a, u32 state, return -ETIMEDOUT; } =20 +static int ufs_mtk_09v_off(struct ufs_mtk_host *host) +{ + struct arm_smccc_res res; + int ret; + + if (!host->reg_avdd09) + return 0; + + ufs_mtk_va09_pwr_ctrl(res, 0); + ret =3D regulator_disable(host->reg_avdd09); + if (ret) { + dev_err(host->hba->dev, "Failed to disable avdd09-supply: %pe\n", + ERR_PTR(ret)); + ufs_mtk_va09_pwr_ctrl(res, 1); + return ret; + } + + return 0; +} + +static int ufs_mtk_09v_on(struct ufs_mtk_host *host) +{ + struct arm_smccc_res res; + int ret; + + if (!host->reg_avdd09) + return 0; + + ret =3D regulator_enable(host->reg_avdd09); + if (ret) { + dev_err(host->hba->dev, "Failed to enable avdd09-supply: %pe\n", + ERR_PTR(ret)); + return ret; + } + + ufs_mtk_va09_pwr_ctrl(res, 1); + + return 0; +} + static int ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); struct phy *mphy =3D host->mphy; - struct arm_smccc_res res; - int ret =3D 0; + int ret; =20 - if (!mphy || !(on ^ host->mphy_powered_on)) + if (!mphy || on =3D=3D host->mphy_powered_on) return 0; =20 if (on) { - if (ufs_mtk_is_va09_supported(hba)) { - ret =3D regulator_enable(host->reg_va09); - if (ret < 0) - goto out; - /* wait 200 us to stablize VA09 */ - usleep_range(200, 210); - ufs_mtk_va09_pwr_ctrl(res, 1); - } + ret =3D ufs_mtk_09v_on(host); + if (ret) + return ret; phy_power_on(mphy); } else { phy_power_off(mphy); - if (ufs_mtk_is_va09_supported(hba)) { - ufs_mtk_va09_pwr_ctrl(res, 0); - ret =3D regulator_disable(host->reg_va09); - } - } -out: - if (ret) { - dev_info(hba->dev, - "failed to %s va09: %d\n", - on ? "enable" : "disable", - ret); - } else { - host->mphy_powered_on =3D on; + ret =3D ufs_mtk_09v_off(host); + if (ret) + return ret; } =20 - return ret; + host->mphy_powered_on =3D on; + + return 0; } =20 static int ufs_mtk_get_host_clk(struct device *dev, const char *name, @@ -678,17 +694,6 @@ static void ufs_mtk_init_boost_crypt(struct ufs_hba *h= ba) return; } =20 -static void ufs_mtk_init_va09_pwr_ctrl(struct ufs_hba *hba) -{ - struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); - - host->reg_va09 =3D regulator_get(hba->dev, "va09"); - if (IS_ERR(host->reg_va09)) - dev_info(hba->dev, "failed to get va09"); - else - host->caps |=3D UFS_MTK_CAP_VA09_PWR_CTRL; -} - static void ufs_mtk_init_host_caps(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); @@ -697,9 +702,6 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba) if (of_property_read_bool(np, "mediatek,ufs-boost-crypt")) ufs_mtk_init_boost_crypt(hba); =20 - if (of_property_read_bool(np, "mediatek,ufs-support-va09")) - ufs_mtk_init_va09_pwr_ctrl(hba); - if (of_property_read_bool(np, "mediatek,ufs-disable-ah8")) host->caps |=3D UFS_MTK_CAP_DISABLE_AH8; =20 @@ -1205,6 +1207,35 @@ static void ufs_mtk_init_mcq_irq(struct ufs_hba *hba) host->mcq_nr_intr =3D 0; } =20 +/** + * ufs_mtk_get_supplies - acquire variant-specific supplies + * @host: pointer to driver's private &struct ufs_mtk_host instance + * + * Returns 0 on success, negative errno on error. + */ +static int ufs_mtk_get_supplies(struct ufs_mtk_host *host) +{ + struct device *dev =3D host->hba->dev; + const struct ufs_mtk_soc_data *data =3D of_device_get_match_data(dev); + + if (!data || !data->has_avdd09) + return 0; + + host->reg_avdd09 =3D devm_regulator_get_optional(dev, "avdd09"); + if (IS_ERR(host->reg_avdd09)) { + if (PTR_ERR(host->reg_avdd09) =3D=3D -ENODEV) { + host->reg_avdd09 =3D NULL; + return 0; + } + + dev_err(dev, "Failed to get avdd09 regulator: %pe\n", + host->reg_avdd09); + return PTR_ERR(host->reg_avdd09); + } + + return 0; +} + /** * ufs_mtk_init - find other essential mmio bases * @hba: host controller instance @@ -1288,6 +1319,10 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 ufs_mtk_init_clocks(hba); =20 + err =3D ufs_mtk_get_supplies(host); + if (err) + goto out_variant_clear; + /* * ufshcd_vops_init() is invoked after * ufshcd_setup_clock(true) in ufshcd_hba_init() thus @@ -2336,6 +2371,18 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_= vops =3D { .config_scsi_dev =3D ufs_mtk_config_scsi_dev, }; =20 +static const struct ufs_mtk_soc_data mt8183_data =3D { + .has_avdd09 =3D true, +}; + +static const struct of_device_id ufs_mtk_of_match[] =3D { + { .compatible =3D "mediatek,mt8183-ufshci", .data =3D &mt8183_data }, + { .compatible =3D "mediatek,mt8192-ufshci" }, + { .compatible =3D "mediatek,mt8195-ufshci" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ufs_mtk_of_match); + /** * ufs_mtk_probe - probe routine of the driver * @pdev: pointer to Platform device handle diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index 4fce29d131d1..24c8941f6b86 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -125,7 +125,6 @@ enum { */ enum ufs_mtk_host_caps { UFS_MTK_CAP_BOOST_CRYPT_ENGINE =3D 1 << 0, - UFS_MTK_CAP_VA09_PWR_CTRL =3D 1 << 1, UFS_MTK_CAP_DISABLE_AH8 =3D 1 << 2, UFS_MTK_CAP_BROKEN_VCC =3D 1 << 3, =20 @@ -176,7 +175,7 @@ struct ufs_mtk_mcq_intr_info { =20 struct ufs_mtk_host { struct phy *mphy; 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Thu, 18 Dec 2025 04:56:22 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:54:58 +0100 Subject: [PATCH v4 08/25] scsi: ufs: mediatek: Rework init function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-8-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Printing an error message on ENOMEM is pointless. The print will not work because there is no memory. Adding an of_match_device to the init function is pointless. Why would a different device with a different probe function ever use the same init function? Get rid of it. zero-initialising an error variable just so you can then goto a bare return statement with that error variable to signal success is also pointless, just return directly, there's no unwind being done. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index a7aab2332ef2..131f71145a12 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1248,29 +1248,19 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host= *host) */ static int ufs_mtk_init(struct ufs_hba *hba) { - const struct of_device_id *id; struct device *dev =3D hba->dev; struct ufs_mtk_host *host; struct Scsi_Host *shost =3D hba->host; - int err =3D 0; + int err; struct arm_smccc_res res; =20 host =3D devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); - if (!host) { - err =3D -ENOMEM; - dev_info(dev, "%s: no memory for mtk ufs host\n", __func__); - goto out; - } + if (!host) + return -ENOMEM; =20 host->hba =3D hba; ufshcd_set_variant(hba, host); =20 - id =3D of_match_device(ufs_mtk_of_match, dev); - if (!id) { - err =3D -EINVAL; - goto out; - } - /* Initialize host capability */ ufs_mtk_init_host_caps(hba); =20 @@ -1344,11 +1334,10 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 ufs_mtk_get_hw_ip_version(hba); =20 - goto out; + return 0; =20 out_variant_clear: ufshcd_set_variant(hba, NULL); -out: return err; } =20 --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33D89334372; Thu, 18 Dec 2025 12:56:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062616; cv=pass; b=SHm/6z+8BZSsXJUdxnNCVR25QyLMm1DDcctRUuzd3kHN1xo0Lg7TELD+b/PNLwAueXmAuyqfd2Moc4dzeYPpcrjRabyOQmF8bGIQohYqeeKg2HIjv3o9ECJ8A98ZLbR7WRu5LgxSJe9AHhq3dbY97C1zmyeDij8tLjNY5D8XhDs= ARC-Message-Signature: i=2; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=DCodZ65ripcarw6609Dpnt3dZb7SVi5h2TJ87Z7JA4M=; b=BgIq1IV+0jku6sdH/hbA6ptzf6ygSImZhdhGoGb2j/mcDXtz8HWuCT4Pq9t+Aqeb 8ZYbaM4seb2YAnuXzE669LvsRuGPzBZfn06t8/fDKmoN/a6uoWpiUiHieReK2X8XUw4 lLCiHn/1vZX9sZlmSsiXiyV3O2kTfuYCOcbvzlE4= Received: by mx.zohomail.com with SMTPS id 1766062588541902.244686873399; Thu, 18 Dec 2025 04:56:28 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:54:59 +0100 Subject: [PATCH v4 09/25] scsi: ufs: mediatek: Rework the crypt-boost stuff Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-9-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 I don't know whether the crypt-boost functionality as it is currently implemented is even appropriate for mainline. It might be better done in some generic way. But what I do know is that I can rework the code to make it less obtuse. Prefix the boost stuff with the appropriate vendor prefix, remove the pointless clock wrappers, and rework the function. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 91 +++++++++++++++----------------------= ---- 1 file changed, 32 insertions(+), 59 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 131f71145a12..9c0ac72d6e43 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -562,21 +562,6 @@ static int ufs_mtk_mphy_power_on(struct ufs_hba *hba, = bool on) return 0; } =20 -static int ufs_mtk_get_host_clk(struct device *dev, const char *name, - struct clk **clk_out) -{ - struct clk *clk; - int err =3D 0; - - clk =3D devm_clk_get(dev, name); - if (IS_ERR(clk)) - err =3D PTR_ERR(clk); - else - *clk_out =3D clk; - - return err; -} - static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); @@ -633,65 +618,53 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, = bool boost) clk_disable_unprepare(cfg->clk_crypt_mux); } =20 -static int ufs_mtk_init_host_clk(struct ufs_hba *hba, const char *name, - struct clk **clk) -{ - int ret; - - ret =3D ufs_mtk_get_host_clk(hba->dev, name, clk); - if (ret) { - dev_info(hba->dev, "%s: failed to get %s: %d", __func__, - name, ret); - } - - return ret; -} - -static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba) +static int ufs_mtk_init_boost_crypt(struct ufs_hba *hba) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); struct ufs_mtk_crypt_cfg *cfg; struct device *dev =3D hba->dev; - struct regulator *reg; - u32 volt; + int ret; =20 - host->crypt =3D devm_kzalloc(dev, sizeof(*(host->crypt)), - GFP_KERNEL); - if (!host->crypt) - goto disable_caps; + cfg =3D devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL); + if (!cfg) + return -ENOMEM; =20 - reg =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); - if (IS_ERR(reg)) { - dev_info(dev, "failed to get dvfsrc-vcore: %ld", - PTR_ERR(reg)); - goto disable_caps; + cfg->reg_vcore =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); + if (IS_ERR(cfg->reg_vcore)) { + dev_err(dev, "Failed to get dvfsrc-vcore: %pe", cfg->reg_vcore); + return PTR_ERR(cfg->reg_vcore); } =20 - if (of_property_read_u32(dev->of_node, "boost-crypt-vcore-min", - &volt)) { - dev_info(dev, "failed to get boost-crypt-vcore-min"); - goto disable_caps; + ret =3D of_property_read_u32(dev->of_node, "mediatek,boost-crypt-vcore-mi= n", + &cfg->vcore_volt); + if (ret) { + dev_err(dev, "Failed to get mediatek,boost-crypt-vcore-min: %pe\n", + ERR_PTR(ret)); + return ret; } =20 - cfg =3D host->crypt; - if (ufs_mtk_init_host_clk(hba, "crypt_mux", - &cfg->clk_crypt_mux)) - goto disable_caps; + cfg->clk_crypt_mux =3D devm_clk_get(dev, "crypt_mux"); + if (IS_ERR(cfg->clk_crypt_mux)) { + dev_err(dev, "Failed to get clock crypt_mux: %pe\n", cfg->clk_crypt_mux); + return PTR_ERR(cfg->clk_crypt_mux); + } =20 - if (ufs_mtk_init_host_clk(hba, "crypt_lp", - &cfg->clk_crypt_lp)) - goto disable_caps; + cfg->clk_crypt_lp =3D devm_clk_get(dev, "crypt_lp"); + if (IS_ERR(cfg->clk_crypt_lp)) { + dev_err(dev, "Failed to get clock crypt_lp: %pe\n", cfg->clk_crypt_lp); + return PTR_ERR(cfg->clk_crypt_lp); + } =20 - if (ufs_mtk_init_host_clk(hba, "crypt_perf", - &cfg->clk_crypt_perf)) - goto disable_caps; + cfg->clk_crypt_perf =3D devm_clk_get(dev, "crypt_perf"); + if (IS_ERR(cfg->clk_crypt_perf)) { + dev_err(dev, "Failed to get clock crypt_perf: %pe\n", cfg->clk_crypt_per= f); + return PTR_ERR(cfg->clk_crypt_perf); + } =20 - cfg->reg_vcore =3D reg; - cfg->vcore_volt =3D volt; + host->crypt =3D cfg; host->caps |=3D UFS_MTK_CAP_BOOST_CRYPT_ENGINE; =20 -disable_caps: - return; + return 0; } =20 static void ufs_mtk_init_host_caps(struct ufs_hba *hba) --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5418C335072; Thu, 18 Dec 2025 12:57:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-10-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 MediaTek SoCs handled by this driver contain a per-SoC specific set of miscellaneous supplies. These feed parts of the UFS controller silicon inside the SoC, as opposed to the UFS card. Add the necessary driver code to acquire these supplies using the regulator bulk API, and disable/enable them during suspend/resume. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 61 +++++++++++++++++++++++++++++++++++++= +--- drivers/ufs/host/ufs-mediatek.h | 2 ++ 2 files changed, 59 insertions(+), 4 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 9c0ac72d6e43..10d6b69e91a5 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -40,6 +40,8 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool = scale_up); =20 struct ufs_mtk_soc_data { bool has_avdd09; + u8 num_reg_names; + const char *const *reg_names; }; =20 static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] =3D { @@ -1190,8 +1192,37 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host = *host) { struct device *dev =3D host->hba->dev; const struct ufs_mtk_soc_data *data =3D of_device_get_match_data(dev); + int ret; =20 - if (!data || !data->has_avdd09) + if (!data) + return 0; + + if (data->num_reg_names) { + host->reg_misc =3D devm_kcalloc(dev, data->num_reg_names, + sizeof(*host->reg_misc), GFP_KERNEL); + if (!host->reg_misc) + return -ENOMEM; + + regulator_bulk_set_supply_names(host->reg_misc, data->reg_names, + data->num_reg_names); + + ret =3D devm_regulator_bulk_get(dev, data->num_reg_names, host->reg_misc= ); + if (ret) { + dev_err(dev, "Failed to get misc regulators: %pe\n", ERR_PTR(ret)); + return ret; + } + + host->num_reg_misc =3D data->num_reg_names; + + ret =3D regulator_bulk_enable(host->num_reg_misc, host->reg_misc); + if (ret) { + dev_err(dev, "Failed to turn on misc regulators: %pe\n", + ERR_PTR(ret)); + return ret; + } + } + + if (!data->has_avdd09) return 0; =20 host->reg_avdd09 =3D devm_regulator_get_optional(dev, "avdd09"); @@ -1833,7 +1864,9 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum = ufs_pm_op pm_op, _ufs_mtk_clk_scale(hba, false); } =20 - return 0; + err =3D regulator_bulk_disable(host->num_reg_misc, host->reg_misc); + + return err; fail: /* * Set link as off state enforcedly to trigger @@ -1850,6 +1883,10 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum = ufs_pm_op pm_op) struct arm_smccc_res res; struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); =20 + err =3D regulator_bulk_enable(host->num_reg_misc, host->reg_misc); + if (err) + return err; + if (hba->ufshcd_state !=3D UFSHCD_STATE_OPERATIONAL) ufs_mtk_dev_vreg_set_lpm(hba, false); =20 @@ -2333,14 +2370,30 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk= _vops =3D { .config_scsi_dev =3D ufs_mtk_config_scsi_dev, }; =20 +static const char *const ufs_mtk_regs_avdd12_avdd18[] =3D { + "avdd12", "avdd18" +}; + +static const char *const ufs_mtk_regs_avdd12_ckbuf_avdd18[] =3D { + "avdd12", "avdd12-ckbuf", "avdd18" +}; + static const struct ufs_mtk_soc_data mt8183_data =3D { .has_avdd09 =3D true, + .reg_names =3D ufs_mtk_regs_avdd12_avdd18, + .num_reg_names =3D ARRAY_SIZE(ufs_mtk_regs_avdd12_avdd18), +}; + +static const struct ufs_mtk_soc_data mt8192_8195_data =3D { + .has_avdd09 =3D false, + .reg_names =3D ufs_mtk_regs_avdd12_ckbuf_avdd18, + .num_reg_names =3D ARRAY_SIZE(ufs_mtk_regs_avdd12_ckbuf_avdd18), }; =20 static const struct of_device_id ufs_mtk_of_match[] =3D { { .compatible =3D "mediatek,mt8183-ufshci", .data =3D &mt8183_data }, - { .compatible =3D "mediatek,mt8192-ufshci" }, - { .compatible =3D "mediatek,mt8195-ufshci" }, + { .compatible =3D "mediatek,mt8192-ufshci", .data =3D &mt8192_8195_data }, + { .compatible =3D "mediatek,mt8195-ufshci", .data =3D &mt8192_8195_data }, {}, }; MODULE_DEVICE_TABLE(of, ufs_mtk_of_match); diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index 24c8941f6b86..cb32fc987864 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -176,6 +176,8 @@ struct ufs_mtk_mcq_intr_info { struct ufs_mtk_host { struct phy *mphy; struct regulator *reg_avdd09; + struct regulator_bulk_data *reg_misc; + u8 num_reg_misc; struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS]; struct ufs_hba *hba; struct ufs_mtk_crypt_cfg *crypt; --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3321333A030; Thu, 18 Dec 2025 12:57:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; 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spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1766062602; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=6XOCA2Fip916bzcuN3Z/+09ZGEdeJC+mwMclvW4uRfs=; b=ewml0xW1YctPdGEdbSSxUAw0FheoKoxAwkcbJt6U89TgIeJ0xZR5bHl8nnynCeNT Kl16X3E5x26VoEWp/l+4TPznhodb0PL8HJORHdHt82JunguP+hfa6BCzQOUe6dGP7UR 6wsg8wGEnPF7li+Avq/2KDYbm+UzEiB49SE81GJ0= Received: by mx.zohomail.com with SMTPS id 1766062601306820.1593929255353; Thu, 18 Dec 2025 04:56:41 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:55:01 +0100 Subject: [PATCH v4 11/25] scsi: ufs: mediatek: Rework probe function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-11-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Remove the ti,syscon-reset cruft. Make PHY mandatory. All the compatibles supported by the binding make it mandatory. Entertain this driver's insistence on playing with the PHY's RPM, but at least fix the part where it doesn't increase the reference count, which would lead to use-after-free. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 87 +++++++++++++++----------------------= ---- 1 file changed, 32 insertions(+), 55 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 10d6b69e91a5..cc6a3a4c9704 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -2406,74 +2406,49 @@ MODULE_DEVICE_TABLE(of, ufs_mtk_of_match); */ static int ufs_mtk_probe(struct platform_device *pdev) { - int err; - struct device *dev =3D &pdev->dev, *phy_dev =3D NULL; - struct device_node *reset_node, *phy_node =3D NULL; - struct platform_device *reset_pdev, *phy_pdev =3D NULL; - struct device_link *link; - struct ufs_hba *hba; + struct platform_device *phy_pdev; + struct device *dev =3D &pdev->dev; + struct device_node *phy_node; struct ufs_mtk_host *host; + struct device *phy_dev; + struct ufs_hba *hba; + int err; =20 - reset_node =3D of_find_compatible_node(NULL, NULL, - "ti,syscon-reset"); - if (!reset_node) { - dev_notice(dev, "find ti,syscon-reset fail\n"); - goto skip_reset; - } - reset_pdev =3D of_find_device_by_node(reset_node); - if (!reset_pdev) { - dev_notice(dev, "find reset_pdev fail\n"); - goto skip_reset; - } - link =3D device_link_add(dev, &reset_pdev->dev, - DL_FLAG_AUTOPROBE_CONSUMER); - put_device(&reset_pdev->dev); - if (!link) { - dev_notice(dev, "add reset device_link fail\n"); - goto skip_reset; - } - /* supplier is not probed */ - if (link->status =3D=3D DL_STATE_DORMANT) { - err =3D -EPROBE_DEFER; - goto out; - } - -skip_reset: /* find phy node */ phy_node =3D of_parse_phandle(dev->of_node, "phys", 0); + if (!phy_node) + return dev_err_probe(dev, -ENOENT, "No PHY node found\n"); =20 - if (phy_node) { - phy_pdev =3D of_find_device_by_node(phy_node); - if (!phy_pdev) - goto skip_phy; - phy_dev =3D &phy_pdev->dev; + phy_pdev =3D of_find_device_by_node(phy_node); + of_node_put(phy_node); + if (!phy_pdev) + return dev_err_probe(dev, -ENODEV, "No PHY device found\n"); =20 - pm_runtime_set_active(phy_dev); - pm_runtime_enable(phy_dev); - pm_runtime_get_sync(phy_dev); + phy_dev =3D &phy_pdev->dev; =20 - put_device(phy_dev); - dev_info(dev, "phys node found\n"); - } else { - dev_notice(dev, "phys node not found\n"); + err =3D pm_runtime_set_active(phy_dev); + if (err) { + dev_err_probe(dev, err, "Failed to activate PHY RPM\n"); + goto err_put_phy; + } + pm_runtime_enable(phy_dev); + err =3D pm_runtime_get_sync(phy_dev); + if (err) { + dev_err_probe(dev, err, "Failed to power on PHY\n"); + goto err_put_phy; } =20 -skip_phy: /* perform generic probe */ err =3D ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops); if (err) { - dev_err(dev, "probe failed %d\n", err); - goto out; + dev_err_probe(dev, err, "Generic platform probe failed\n"); + goto err_put_phy; } =20 hba =3D platform_get_drvdata(pdev); - if (!hba) - goto out; =20 - if (phy_node && phy_dev) { - host =3D ufshcd_get_variant(hba); - host->phy_dev =3D phy_dev; - } + host =3D ufshcd_get_variant(hba); + host->phy_dev =3D phy_dev; =20 /* * Because the default power setting of VSx (the upper layer of @@ -2482,9 +2457,11 @@ static int ufs_mtk_probe(struct platform_device *pde= v) */ ufs_mtk_dev_vreg_set_lpm(hba, false); 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Thu, 18 Dec 2025 04:56:47 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:55:02 +0100 Subject: [PATCH v4 12/25] scsi: ufs: mediatek: Remove vendor kernel quirks cruft Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-12-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Both ufs_mtk_vreg_fix_vcc and ufs_mtk_vreg_fix_vccqx look like they are vendor kernel hacks to work around existing downstream device trees. Mainline does not need or want them, so remove them. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 69 -------------------------------------= ---- 1 file changed, 69 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index cc6a3a4c9704..6385ebcc9142 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1019,73 +1019,6 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) } } =20 -#define MAX_VCC_NAME 30 -static int ufs_mtk_vreg_fix_vcc(struct ufs_hba *hba) -{ - struct ufs_vreg_info *info =3D &hba->vreg_info; - struct device_node *np =3D hba->dev->of_node; - struct device *dev =3D hba->dev; - char vcc_name[MAX_VCC_NAME]; - struct arm_smccc_res res; - int err, ver; - - if (info->vcc) - return 0; - - if (of_property_read_bool(np, "mediatek,ufs-vcc-by-num")) { - ufs_mtk_get_vcc_num(res); - if (res.a1 > UFS_VCC_NONE && res.a1 < UFS_VCC_MAX) - snprintf(vcc_name, MAX_VCC_NAME, "vcc-opt%lu", res.a1); - else - return -ENODEV; - } else if (of_property_read_bool(np, "mediatek,ufs-vcc-by-ver")) { - ver =3D (hba->dev_info.wspecversion & 0xF00) >> 8; - snprintf(vcc_name, MAX_VCC_NAME, "vcc-ufs%u", ver); - } else { - return 0; - } - - err =3D ufshcd_populate_vreg(dev, vcc_name, &info->vcc, false); - if (err) - return err; - - err =3D ufshcd_get_vreg(dev, info->vcc); - if (err) - return err; - - err =3D regulator_enable(info->vcc->reg); - if (!err) { - info->vcc->enabled =3D true; - dev_info(dev, "%s: %s enabled\n", __func__, vcc_name); - } - - return err; -} - -static void ufs_mtk_vreg_fix_vccqx(struct ufs_hba *hba) -{ - struct ufs_vreg_info *info =3D &hba->vreg_info; - struct ufs_vreg **vreg_on, **vreg_off; - - if (hba->dev_info.wspecversion >=3D 0x0300) { - vreg_on =3D &info->vccq; - vreg_off =3D &info->vccq2; - } else { - vreg_on =3D &info->vccq2; - vreg_off =3D &info->vccq; - } - - if (*vreg_on) - (*vreg_on)->always_on =3D true; - - if (*vreg_off) { - regulator_disable((*vreg_off)->reg); - devm_kfree(hba->dev, (*vreg_off)->name); - devm_kfree(hba->dev, *vreg_off); - *vreg_off =3D NULL; - } -} - static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba) { unsigned long flags; @@ -2005,8 +1938,6 @@ static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *= hba) hba->dev_quirks &=3D ~UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM; } =20 - ufs_mtk_vreg_fix_vcc(hba); - ufs_mtk_vreg_fix_vccqx(hba); ufs_mtk_fix_ahit(hba); ufs_mtk_fix_clock_scaling(hba); } --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E377339860; Thu, 18 Dec 2025 12:57:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062647; cv=pass; b=gIb6Od0RK+UTmJrK6C9L5ircI1zdscU5P2HTImOwXAVNKSZgv+D/YGlcL4tyPfY0EIAxJZImr7MnhB3FL8rTBLC+JrvpkhbF+epVBVFVDkEHBYwVKKJEE+Nn4H0aEfMHlpZW4FM6uGUkQEI50DTv+jnsiwK61izX7yLpfYU8TmA= ARC-Message-Signature: i=2; a=rsa-sha256; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=lIRA5jBmzjNM1Jhu5oCUpBq81ZSbzIvIV0wFiZyrEjY=; b=bL0j2K5kZgXBQTF4qaC6akzmQmGfzwfjuP2qPUiM8JB3nYNAvwvZ/oG7aLvUkkvR G40wxQhmtdABp7+52RhucmM8PyNy+SMzdcnFyXAdIt3l15WQLVY6nLkKg+DzImCOqxr YnXpmPdFEZGLw6Z9v0XFqwBt4+SFAsywpggXFDyg= Received: by mx.zohomail.com with SMTPS id 1766062614054781.808413243351; Thu, 18 Dec 2025 04:56:54 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:55:03 +0100 Subject: [PATCH v4 13/25] scsi: ufs: mediatek: Use the common PHY framework Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-13-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 There is no need to reinvent the PHY framework, especially not its OF parsing. Change the code to simply use the PHY framework to acquire the device's PHY in the ufshcd init, so that it's device linked to the right device. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 133 ++++++++++++------------------------= ---- drivers/ufs/host/ufs-mediatek.h | 1 - 2 files changed, 40 insertions(+), 94 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 6385ebcc9142..b3fb87bd1c75 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -293,44 +293,6 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *h= ba, return 0; } =20 -static int ufs_mtk_bind_mphy(struct ufs_hba *hba) -{ - struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); - struct device *dev =3D hba->dev; - struct device_node *np =3D dev->of_node; - int err =3D 0; - - host->mphy =3D devm_of_phy_get_by_index(dev, np, 0); - - if (host->mphy =3D=3D ERR_PTR(-EPROBE_DEFER)) { - /* - * UFS driver might be probed before the phy driver does. - * In that case we would like to return EPROBE_DEFER code. - */ - err =3D -EPROBE_DEFER; - dev_info(dev, - "%s: required phy hasn't probed yet. err =3D %d\n", - __func__, err); - } else if (IS_ERR(host->mphy)) { - err =3D PTR_ERR(host->mphy); - if (err !=3D -ENODEV) { - dev_info(dev, "%s: PHY get failed %d\n", __func__, - err); - } - } - - if (err) - host->mphy =3D NULL; - /* - * Allow unbound mphy because not every platform needs specific - * mphy control. - */ - if (err =3D=3D -ENODEV) - err =3D 0; - - return err; -} - static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); @@ -1203,13 +1165,21 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 ufs_mtk_init_mcq_irq(hba); =20 - err =3D ufs_mtk_bind_mphy(hba); - if (err) + host->mphy =3D devm_phy_get(dev, NULL); + if (IS_ERR(host->mphy)) { + err =3D dev_err_probe(dev, PTR_ERR(host->mphy), "Failed to get PHY\n"); + goto out_variant_clear; + } + + err =3D phy_init(host->mphy); + if (err) { + dev_err_probe(dev, err, "Failed to initialize PHY\n"); goto out_variant_clear; + } =20 err =3D ufs_mtk_init_reset(hba); if (err) - goto out_variant_clear; + goto out_phy_exit; =20 /* Enable runtime autosuspend */ hba->caps |=3D UFSHCD_CAP_RPM_AUTOSUSPEND; @@ -1248,7 +1218,7 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 err =3D ufs_mtk_get_supplies(host); if (err) - goto out_variant_clear; + goto out_phy_exit; =20 /* * ufshcd_vops_init() is invoked after @@ -1273,11 +1243,22 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 return 0; =20 +out_phy_exit: + phy_exit(host->mphy); out_variant_clear: ufshcd_set_variant(hba, NULL); return err; } =20 +static void ufs_mtk_exit(struct ufs_hba *hba) +{ + struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); + + ufs_mtk_mphy_power_on(hba, false); + + phy_exit(host->mphy); +} + static bool ufs_mtk_pmc_via_fastauto(struct ufs_hba *hba, struct ufs_pa_layer_attr *dev_req_params) { @@ -2279,6 +2260,7 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_v= ops =3D { .name =3D "mediatek.ufshci", .max_num_rtt =3D MTK_MAX_NUM_RTT, .init =3D ufs_mtk_init, + .exit =3D ufs_mtk_exit, .get_ufs_hci_version =3D ufs_mtk_get_ufs_hci_version, .setup_clocks =3D ufs_mtk_setup_clocks, .hce_enable_notify =3D ufs_mtk_hce_enable_notify, @@ -2337,50 +2319,17 @@ MODULE_DEVICE_TABLE(of, ufs_mtk_of_match); */ static int ufs_mtk_probe(struct platform_device *pdev) { - struct platform_device *phy_pdev; struct device *dev =3D &pdev->dev; - struct device_node *phy_node; - struct ufs_mtk_host *host; - struct device *phy_dev; struct ufs_hba *hba; - int err; - - /* find phy node */ - phy_node =3D of_parse_phandle(dev->of_node, "phys", 0); - if (!phy_node) - return dev_err_probe(dev, -ENOENT, "No PHY node found\n"); - - phy_pdev =3D of_find_device_by_node(phy_node); - of_node_put(phy_node); - if (!phy_pdev) - return dev_err_probe(dev, -ENODEV, "No PHY device found\n"); - - phy_dev =3D &phy_pdev->dev; - - err =3D pm_runtime_set_active(phy_dev); - if (err) { - dev_err_probe(dev, err, "Failed to activate PHY RPM\n"); - goto err_put_phy; - } - pm_runtime_enable(phy_dev); - err =3D pm_runtime_get_sync(phy_dev); - if (err) { - dev_err_probe(dev, err, "Failed to power on PHY\n"); - goto err_put_phy; - } + int ret; =20 /* perform generic probe */ - err =3D ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops); - if (err) { - dev_err_probe(dev, err, "Generic platform probe failed\n"); - goto err_put_phy; - } + ret =3D ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops); + if (ret) + return dev_err_probe(dev, ret, "Generic platform probe failed\n"); =20 hba =3D platform_get_drvdata(pdev); =20 - host =3D ufshcd_get_variant(hba); - host->phy_dev =3D phy_dev; - /* * Because the default power setting of VSx (the upper layer of * VCCQ/VCCQ2) is HWLP, we need to prevent VCCQ/VCCQ2 from @@ -2389,18 +2338,11 @@ static int ufs_mtk_probe(struct platform_device *pd= ev) ufs_mtk_dev_vreg_set_lpm(hba, false); =20 return 0; - -err_put_phy: - put_device(phy_dev); - - return err; } =20 /** * ufs_mtk_remove - set driver_data of the device to NULL * @pdev: pointer to platform device handle - * - * Always return 0 */ static void ufs_mtk_remove(struct platform_device *pdev) { @@ -2460,9 +2402,8 @@ static int ufs_mtk_system_resume(struct device *dev) static int ufs_mtk_runtime_suspend(struct device *dev) { struct ufs_hba *hba =3D dev_get_drvdata(dev); - struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); struct arm_smccc_res res; - int ret =3D 0; + int ret; =20 ret =3D ufshcd_runtime_suspend(dev); if (ret) @@ -2473,8 +2414,11 @@ static int ufs_mtk_runtime_suspend(struct device *de= v) if (ufs_mtk_is_rtff_mtcmos(hba)) ufs_mtk_mtcmos_ctrl(false, res); =20 - if (host->phy_dev) - pm_runtime_put_sync(host->phy_dev); + ret =3D ufs_mtk_mphy_power_on(hba, false); + if (ret) { + dev_err(dev, "Failed to power off PHY: %pe\n", ERR_PTR(ret)); + return ret; + } =20 return 0; } @@ -2482,14 +2426,17 @@ static int ufs_mtk_runtime_suspend(struct device *d= ev) static int ufs_mtk_runtime_resume(struct device *dev) { struct ufs_hba *hba =3D dev_get_drvdata(dev); - struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); struct arm_smccc_res res; + int ret; =20 if (ufs_mtk_is_rtff_mtcmos(hba)) ufs_mtk_mtcmos_ctrl(true, res); =20 - if (host->phy_dev) - pm_runtime_get_sync(host->phy_dev); + ret =3D ufs_mtk_mphy_power_on(hba, true); + if (ret) { + dev_err(dev, "Failed to power on PHY: %pe\n", ERR_PTR(ret)); + return ret; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=60JlsHuRXLbXd5Pexm7Q9dFe3pq5uxcyNe5DGlL9XFE=; b=AitEfXcuM7OO9SCx0cok6nieLMV/ptKscnMiXFPdP2jXdLgZYEZEZ+UPSUfGCtHn Jd0aboy/v619/6JkNPmglrcryoZp2GMWsIrS1wgSSmC+vVQweh5iP3cccLd26lzkjl4 gXaJ1kOqRrGaZpFZ5/xZDUhpjOPedETAa4q0XolE= Received: by mx.zohomail.com with SMTPS id 176606262047881.2669190579021; Thu, 18 Dec 2025 04:57:00 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:55:04 +0100 Subject: [PATCH v4 14/25] scsi: ufs: mediatek: Switch to newer PM ops helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-14-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 SET_SYSTEM_SLEEP_PM_OPS and SET_RUNTIME_PM_OPS are deprecated. Switch to the non-deprecated variants, and pm_ptr, removing the ifdeffery in the process. This allows the compiler visibility into those functions. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index b3fb87bd1c75..89e3fa5d7d10 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -2349,7 +2349,6 @@ static void ufs_mtk_remove(struct platform_device *pd= ev) ufshcd_pltfrm_remove(pdev); } =20 -#ifdef CONFIG_PM_SLEEP static int ufs_mtk_system_suspend(struct device *dev) { struct ufs_hba *hba =3D dev_get_drvdata(dev); @@ -2396,9 +2395,7 @@ static int ufs_mtk_system_resume(struct device *dev) =20 return ret; } -#endif =20 -#ifdef CONFIG_PM static int ufs_mtk_runtime_suspend(struct device *dev) { struct ufs_hba *hba =3D dev_get_drvdata(dev); @@ -2442,13 +2439,10 @@ static int ufs_mtk_runtime_resume(struct device *de= v) =20 return ufshcd_runtime_resume(dev); } -#endif =20 static const struct dev_pm_ops ufs_mtk_pm_ops =3D { - SET_SYSTEM_SLEEP_PM_OPS(ufs_mtk_system_suspend, - ufs_mtk_system_resume) - SET_RUNTIME_PM_OPS(ufs_mtk_runtime_suspend, - ufs_mtk_runtime_resume, NULL) + SYSTEM_SLEEP_PM_OPS(ufs_mtk_system_suspend, ufs_mtk_system_resume) + RUNTIME_PM_OPS(ufs_mtk_runtime_suspend, ufs_mtk_runtime_resume, NULL) .prepare =3D ufshcd_suspend_prepare, .complete =3D ufshcd_resume_complete, }; @@ -2458,7 +2452,7 @@ static struct platform_driver ufs_mtk_pltform =3D { .remove =3D ufs_mtk_remove, .driver =3D { .name =3D "ufshcd-mtk", - .pm =3D &ufs_mtk_pm_ops, + .pm =3D pm_ptr(&ufs_mtk_pm_ops), .of_match_table =3D ufs_mtk_of_match, }, }; --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D58653370EA; Thu, 18 Dec 2025 12:57:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062659; cv=pass; b=qyuIx+0MCla5wrwYQ1AY2FnVN3KTwAa0wqGwAcTFDQuu6h8rRTxH2XtGflmGfmsGimCPBTAseLWVT/54U+n7t9sarBXeHevoMdyZQspHhsZwUXJXcayvXKcqjRxCJSBBVBGJ5HR+dU3iuURqrLEIbAd3NGnbxFzo2gLVKLoYrvU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=tBDcvlSJdqaE/FhBeajz0HQZsvPrdYdKBwg6m1HcfQ0=; b=TXrbXtvn4RVxLZPS40ooO+3NTCHPKCUHj0XQ/fixHp9L/9PfpLUsuFxOKCF+Gcer iN7DXc1baXOuGZCpHpHEdW0Wyfin8iwY0sAxlok+lBjyWXJGbDc7KLUOPVjxD9ghX/Z hun4PI8LAciEyqaZDXG3/13iiRuAJc3K2efPgjsk= Received: by mx.zohomail.com with SMTPS id 176606262695595.52766682896265; Thu, 18 Dec 2025 04:57:06 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:55:05 +0100 Subject: [PATCH v4 15/25] scsi: ufs: mediatek: Remove mediatek,ufs-broken-rtc property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-15-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 This flag property was never described in the binding, and its capability wrapper seems pointless. If one of the MediaTek SoCs needs the ufshcd quirk applied, then this can be done per-compatible, without needing to give the device tree author the option to forget to set it. Remove it and the associated capability flag wrapping code. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 5 ----- drivers/ufs/host/ufs-mediatek.h | 2 -- 2 files changed, 7 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 89e3fa5d7d10..ffd52b8c295a 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -657,9 +657,6 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba) if (of_property_read_bool(np, "mediatek,ufs-rtff-mtcmos")) host->caps |=3D UFS_MTK_CAP_RTFF_MTCMOS; =20 - if (of_property_read_bool(np, "mediatek,ufs-broken-rtc")) - host->caps |=3D UFS_MTK_CAP_MCQ_BROKEN_RTC; - dev_info(hba->dev, "caps: 0x%x", host->caps); } =20 @@ -1203,8 +1200,6 @@ static int ufs_mtk_init(struct ufs_hba *hba) hba->quirks |=3D UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL; =20 hba->quirks |=3D UFSHCD_QUIRK_MCQ_BROKEN_INTR; - if (host->caps & UFS_MTK_CAP_MCQ_BROKEN_RTC) - hba->quirks |=3D UFSHCD_QUIRK_MCQ_BROKEN_RTC; =20 hba->vps->wb_flush_threshold =3D UFS_WB_BUF_REMAIN_PERCENT(80); =20 diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index bf8122af69f0..5f096ed3f850 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -138,8 +138,6 @@ enum ufs_mtk_host_caps { UFS_MTK_CAP_DISABLE_MCQ =3D 1 << 8, /* Control MTCMOS with RTFF */ UFS_MTK_CAP_RTFF_MTCMOS =3D 1 << 9, - - UFS_MTK_CAP_MCQ_BROKEN_RTC =3D 1 << 10, }; =20 struct ufs_mtk_crypt_cfg { --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E615433ADBA; Thu, 18 Dec 2025 12:57:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062665; cv=pass; b=Kdhdwkl1w3D3YSeM9gpb8Nm6BFL427UPMR62T35oZbmFtvet1yCWs7UzACYBZsSCnblfu7KEiGDpfH1jF4LIpru6pzYiq9gkwZpyqLftKB3ze7UgfAAvhBcRQPQoB3xqBU9Cig8UHDuB0/4ut1oxQmyOwAQ3P7HXSHH5gmaXlOE= ARC-Message-Signature: i=2; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=TTl4r4f6Il+Hnj8EJO5lgTBBkjOsH1KrF0jWRvAtRn0=; b=k+36rhv7SZ52ojxw1sdywYKG3Tav4dBj7dPGwa+03wnfE1ExKHr58xjupG00EJZe lDnqu6Nwqe8wIzuEyF1F8ks/yiLbdnmiIDFCCkqCcCG7zlqh2C8ED51sTL7rNt7vJQ+ insrddx4neT7KpKWxRMYvumJIfMteVa1mpMk3v/o= Received: by mx.zohomail.com with SMTPS id 1766062633346532.3493326825272; Thu, 18 Dec 2025 04:57:13 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:55:06 +0100 Subject: [PATCH v4 16/25] scsi: ufs: mediatek: Rework _ufs_mtk_clk_scale error paths Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-16-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Errors should be printed at the correct log level. Additionally, it looks like some "goto out"'s were omitted in the scale up case, which looks like a mistake, as the scale down branch of the code does use them. Rework the error messages to make them nicer and at the correct verbosity, and add the missing gotos. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 41 +++++++++++++++++++------------------= ---- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index ffd52b8c295a..d72b6ab05a23 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1985,16 +1985,16 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba,= bool scale_up) =20 ret =3D clk_prepare_enable(clki->clk); if (ret) { - dev_info(hba->dev, - "clk_prepare_enable() fail, ret: %d\n", ret); + dev_err(hba->dev, "%s: Failed to enable clock: %pe\n", __func__, ERR_PTR= (ret)); return; } =20 if (clk_fde_scale) { ret =3D clk_prepare_enable(fde_clki->clk); if (ret) { - dev_info(hba->dev, - "fde clk_prepare_enable() fail, ret: %d\n", ret); + dev_err(hba->dev, "%s: Failed to enable FDE clock: %pe\n", + __func__, ERR_PTR(ret)); + clk_disable_unprepare(clki->clk); return; } } @@ -2003,51 +2003,48 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba,= bool scale_up) if (clk_bind_vcore) { ret =3D regulator_set_voltage(reg, volt, INT_MAX); if (ret) { - dev_info(hba->dev, - "Failed to set vcore to %d\n", volt); + dev_err(hba->dev, "Failed to set vcore to %d\n", volt); goto out; } } =20 ret =3D clk_set_parent(clki->clk, mclk->ufs_sel_max_clki->clk); if (ret) { - dev_info(hba->dev, "Failed to set clk mux, ret =3D %d\n", - ret); + dev_err(hba->dev, "%s: Failed to set clock mux: %pe\n", + __func__, ERR_PTR(ret)); + goto out; } =20 if (clk_fde_scale) { - ret =3D clk_set_parent(fde_clki->clk, - mclk->ufs_fde_max_clki->clk); + ret =3D clk_set_parent(fde_clki->clk, mclk->ufs_fde_max_clki->clk); if (ret) { - dev_info(hba->dev, - "Failed to set fde clk mux, ret =3D %d\n", - ret); + dev_err(hba->dev, "%s: Failed to set fde clock mux: %pe\n", + __func__, ERR_PTR(ret)); + goto out; } } } else { if (clk_fde_scale) { - ret =3D clk_set_parent(fde_clki->clk, - mclk->ufs_fde_min_clki->clk); + ret =3D clk_set_parent(fde_clki->clk, mclk->ufs_fde_min_clki->clk); if (ret) { - dev_info(hba->dev, - "Failed to set fde clk mux, ret =3D %d\n", - ret); + dev_err(hba->dev, "%s: Failed to set fde clock mux: %pe\n", + __func__, ERR_PTR(ret)); goto out; } } =20 ret =3D clk_set_parent(clki->clk, mclk->ufs_sel_min_clki->clk); if (ret) { - dev_info(hba->dev, "Failed to set clk mux, ret =3D %d\n", - ret); + dev_err(hba->dev, "%s: Failed to set clock mux: %pe\n", + __func__, ERR_PTR(ret)); goto out; } =20 if (clk_bind_vcore) { ret =3D regulator_set_voltage(reg, 0, INT_MAX); if (ret) { - dev_info(hba->dev, - "failed to set vcore to MIN\n"); + dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n", + __func__, ERR_PTR(ret)); } } } --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2E8433B6CF; Thu, 18 Dec 2025 12:57:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-17-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Device Tree properties other than the standard properties must be prefixed with the vendor's name. The "clk-scale-up-vcore-min" property, which this driver uses, and the binding did not previously document, lacked a vendor prefix. Add the missing "mediatek," vendor prefix and clean up the error print. No judgements are made regarding the use the property itself, it may turn out to be implementing something that it should do through a different way (e.g. OPPs). Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index d72b6ab05a23..a598019cb9ea 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -960,9 +960,9 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) return; } =20 - if (of_property_read_u32(dev->of_node, "clk-scale-up-vcore-min", + if (of_property_read_u32(dev->of_node, "mediatek,clk-scale-up-vcore-min", &volt)) { - dev_info(dev, "failed to get clk-scale-up-vcore-min"); + dev_err(dev, "Failed to get mediatek,clk-scale-up-vcore-min\n"); return; } =20 --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAC4F33B6E6; Thu, 18 Dec 2025 12:57:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062684; cv=pass; b=KAYmiFtHOAMN9lRBnwYxHyuTEAxke03wu2m7Mp0NM8nM9BXdMgyzDsw76yYC5huu6tzFdPhWDZEO6yapoLSvGtOAD8Ed50ZfAJXt5lx28OK2zYb41yfpyfhul+0OR+BIUzfVufRBZQLUZ41BMbUEowTXG545CEG2HxSki09taCA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062684; c=relaxed/simple; bh=HjOEIQ58hWDYCcq3bts63RHlVksDrppKgk+u217mXk4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V2Ki4TQdMh/jG0UgBe9rt0E2aMkOhuBV/Ui2PGv3+jT3fMwkB9wl/7m06rYTWPm0miimferBSE9N19Qgxk7WT8s7ZTB/I0TBDxgkDsBCtWg/rnnWsBMLJd/pJh8JRr7+b955bkHi+dkoyRA2RM6d8H0evaJL/69WcS3S+YXtt1w= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=c7DlvbQ1; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="c7DlvbQ1" ARC-Seal: i=1; a=rsa-sha256; t=1766062646; cv=none; d=zohomail.com; s=zohoarc; b=hloorC9xLj1YWGiubyRc7mZrYunY76WOj7Gggatk48Owql/DoQ/WVgBLo+CzXWLuMahywx5bfTHmWVLM8xGfcyzZTnpFA+cvVtyh7efjfj3R+AyrhDeIXQjY/uwpvakdjnWbMae1CT26wHv32W7Qq6b2z420tmK4XH1Z9jk1Crk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766062646; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=0u+FEG1ewW5jMo5KdiONlDeszER3qg+eFNJnGUtfuzI=; b=kv/B9AInAvvmpEwcpFr2PFAgQtfXG5S1KUuls4FPmUnlZbStLByhxEUr6BVrXHbrt7JY7Hx1OxmIEgS2B6ozpT3UVxNRaXok01Xe+jkUmGZLkt6g9um7K2819q5OADMApr5bw5XdYpsDl3VsT4mKaF/ZUsO0HuocGDIbHHbiVPg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1766062646; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=0u+FEG1ewW5jMo5KdiONlDeszER3qg+eFNJnGUtfuzI=; b=c7DlvbQ1L5IPWtB9sR3uT5G5cEqwqOmezaF7uWQwFXE5kD9Yoen/U0fwYEox27sC mES39kk4g4qLU9wBhQLfqgMPgnC3yifvRHHYPqeZiUHLFL08ptTT2XvybhHfYfVkTe3 ivLhA8XgoFfuGQJN4JgLbIWhI0rYcDYU+/fLXU/U= Received: by mx.zohomail.com with SMTPS id 1766062646107171.16048124413987; Thu, 18 Dec 2025 04:57:26 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:55:08 +0100 Subject: [PATCH v4 18/25] scsi: ufs: mediatek: Clean up logging prints Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-18-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 The Linux kernel's log buffer provides many levels of verbosity, associated with different semantic meanings. Care should be taken to only log useful information to the info level, and log errors to the error level. The MediaTek UFS driver does not do this. It freely logs verbose debug information to the info level, errors to the info level, and sometimes errors to the warning level. Adjust all the wrapped kprintf invocations to rectify this situation. Use user-friendly %pe format codes for printing errors where possible. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 99 ++++++++++++++++++-------------------= ---- 1 file changed, 43 insertions(+), 56 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index a598019cb9ea..8c9daf005e12 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -192,8 +192,8 @@ static void ufs_mtk_crypto_enable(struct ufs_hba *hba) =20 ufs_mtk_crypto_ctrl(res, 1); if (res.a0) { - dev_info(hba->dev, "%s: crypto enable failed, err: %lu\n", - __func__, res.a0); + dev_err(hba->dev, "%s: crypto enable failed with error %lu, disabling\n", + __func__, res.a0); hba->caps &=3D ~UFSHCD_CAP_CRYPTO; } } @@ -542,40 +542,38 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, = bool boost) =20 ret =3D clk_prepare_enable(cfg->clk_crypt_mux); if (ret) { - dev_info(hba->dev, "clk_prepare_enable(): %d\n", - ret); + dev_err(hba->dev, "%s: Failed to enable clk_crypt_mux: %pe\n", + __func__, ERR_PTR(ret)); return; } =20 if (boost) { ret =3D regulator_set_voltage(reg, volt, INT_MAX); if (ret) { - dev_info(hba->dev, - "failed to set vcore to %d\n", volt); + dev_err(hba->dev, "%s: Failed to set vcore to %d: %pe\n", + __func__, volt, ERR_PTR(ret)); goto out; } =20 - ret =3D clk_set_parent(cfg->clk_crypt_mux, - cfg->clk_crypt_perf); + ret =3D clk_set_parent(cfg->clk_crypt_mux, cfg->clk_crypt_perf); if (ret) { - dev_info(hba->dev, - "failed to set clk_crypt_perf\n"); + dev_err(hba->dev, "%s: Failed to reparent clk_crypt_perf: %pe\n", + __func__, ERR_PTR(ret)); regulator_set_voltage(reg, 0, INT_MAX); goto out; } } else { - ret =3D clk_set_parent(cfg->clk_crypt_mux, - cfg->clk_crypt_lp); + ret =3D clk_set_parent(cfg->clk_crypt_mux, cfg->clk_crypt_lp); if (ret) { - dev_info(hba->dev, - "failed to set clk_crypt_lp\n"); + dev_err(hba->dev, "%s: Failed to reparent clk_crypt_lp: %pe\n", + __func__, ERR_PTR(ret)); goto out; } =20 ret =3D regulator_set_voltage(reg, 0, INT_MAX); if (ret) { - dev_info(hba->dev, - "failed to set vcore to MIN\n"); + dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n", + __func__, ERR_PTR(ret)); } } out: @@ -765,10 +763,8 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, b= ool on, if (clk_pwr_off) { ufs_mtk_pwr_ctrl(hba, false); } else { - dev_warn(hba->dev, "Clock is not turned off, hba->ahit =3D 0x%x, AHIT = =3D 0x%x\n", - hba->ahit, - ufshcd_readl(hba, - REG_AUTO_HIBERNATE_IDLE_TIMER)); + dev_warn(hba->dev, "Clock isn't off, hba->ahit =3D 0x%x, AHIT =3D 0x%x\= n", + hba->ahit, ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER)); } ufs_mtk_mcq_disable_irq(hba); } else if (on && status =3D=3D POST_CHANGE) { @@ -812,11 +808,11 @@ static void ufs_mtk_mcq_set_irq_affinity(struct ufs_h= ba *hba, unsigned int cpu) _cpu =3D (cpu =3D=3D 0) ? 3 : cpu; ret =3D irq_set_affinity(irq, cpumask_of(_cpu)); if (ret) { - dev_err(hba->dev, "set irq %d affinity to CPU %d failed\n", + dev_err(hba->dev, "setting irq %d affinity to CPU %d failed\n", irq, _cpu); return; } - dev_info(hba->dev, "set irq %d affinity to CPU: %d\n", irq, _cpu); + dev_dbg(hba->dev, "set irq %d affinity to CPU %d\n", irq, _cpu); } =20 static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *hba, u32 hw_ip_ver) @@ -832,7 +828,8 @@ static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *h= ba, u32 hw_ip_ver) default: break; } - dev_info(hba->dev, "legacy IP version - 0x%x, is legacy : %d", hw_ip_ver,= is_legacy); + dev_dbg(hba->dev, "IP version 0x%x, legacy =3D %s", hw_ip_ver, + str_true_false(is_legacy)); =20 return is_legacy; } @@ -937,15 +934,12 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) } } =20 - list_for_each_entry(clki, head, list) { - dev_info(hba->dev, "clk \"%s\" present", clki->name); - } + list_for_each_entry(clki, head, list) + dev_dbg(hba->dev, "clk \"%s\" present", clki->name); =20 if (!ufs_mtk_is_clk_scale_ready(hba)) { hba->caps &=3D ~UFSHCD_CAP_CLK_SCALING; - dev_info(hba->dev, - "%s: Clk-scaling not ready. Feature disabled.", - __func__); + dev_info(hba->dev, "%s: Clock scaling unavailable", __func__); return; } =20 @@ -955,8 +949,8 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) */ reg =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); if (IS_ERR(reg)) { - dev_info(dev, "failed to get dvfsrc-vcore: %ld", - PTR_ERR(reg)); + if (PTR_ERR(reg) !=3D -ENODEV) + dev_err(dev, "Failed to get dvfsrc-vcore: %pe\n", reg); return; } =20 @@ -970,12 +964,9 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) host->mclk.vcore_volt =3D volt; =20 /* If default boot is max gear, request vcore */ - if (reg && volt && host->clk_scale_up) { - if (regulator_set_voltage(reg, volt, INT_MAX)) { - dev_info(hba->dev, - "Failed to set vcore to %d\n", volt); - } - } + if (reg && volt && host->clk_scale_up) + if (regulator_set_voltage(reg, volt, INT_MAX)) + dev_err(hba->dev, "Failed to set vcore to %d\n", volt); } =20 static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba) @@ -1062,7 +1053,7 @@ static void ufs_mtk_init_mcq_irq(struct ufs_hba *hba) } host->mcq_intr_info[i].hba =3D hba; host->mcq_intr_info[i].irq =3D irq; - dev_info(hba->dev, "get platform mcq irq: %d, %d\n", i, irq); + dev_dbg(hba->dev, "get platform mcq irq: %d, %d\n", i, irq); } =20 return; @@ -1325,10 +1316,8 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hb= a, host_params.desired_working_mode =3D UFS_PWM_MODE; =20 ret =3D ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req= _params); - if (ret) { - pr_info("%s: failed to determine capabilities\n", - __func__); - } + if (ret) + dev_warn(hba->dev, "%s: failed to determine capabilities\n", __func__); =20 if (ufs_mtk_pmc_via_fastauto(hba, dev_req_params)) { ufs_mtk_adjust_sync_length(hba); @@ -1374,10 +1363,9 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hb= a, ret =3D ufshcd_uic_change_pwr_mode(hba, FASTAUTO_MODE << 4 | FASTAUTO_MODE); =20 - if (ret) { - dev_err(hba->dev, "%s: HSG1B FASTAUTO failed ret=3D%d\n", - __func__, ret); - } + if (ret) + dev_err(hba->dev, "%s: HSG1B FASTAUTO failed: %pe\n", + __func__, ERR_PTR(ret)); } =20 /* if already configured to the requested pwr_mode, skip adapt */ @@ -1427,7 +1415,7 @@ static int ufs_mtk_auto_hibern8_disable(struct ufs_hb= a *hba) =20 out: if (ret) { - dev_warn(hba->dev, "exit h8 state fail, ret=3D%d\n", ret); + dev_err(hba->dev, "Failed to exit h8 state: %pe\n", ERR_PTR(ret)); =20 ufshcd_force_error_recovery(hba); =20 @@ -1589,7 +1577,7 @@ static int ufs_mtk_device_reset(struct ufs_hba *hba) /* Some devices may need time to respond to rst_n */ usleep_range(10000, 15000); =20 - dev_info(hba->dev, "device reset done\n"); + dev_dbg(hba->dev, "device reset done\n"); =20 return 0; } @@ -1625,12 +1613,12 @@ static int ufs_mtk_link_set_hpm(struct ufs_hba *hba) /* Check link state to make sure exit h8 success */ err =3D ufs_mtk_wait_idle_state(hba, 5); if (err) { - dev_warn(hba->dev, "wait idle fail, err=3D%d\n", err); + dev_err(hba->dev, "Failed to wait for idle: %pe\n", ERR_PTR(err)); return err; } err =3D ufs_mtk_wait_link_state(hba, VS_LINK_UP, 100); if (err) { - dev_warn(hba->dev, "exit h8 state fail, err=3D%d\n", err); + dev_err(hba->dev, "Failed to wait for link to be up: %pe\n", ERR_PTR(err= )); return err; } ufshcd_set_link_active(hba); @@ -1929,20 +1917,19 @@ static void ufs_mtk_event_notify(struct ufs_hba *hb= a, =20 /* Print details of UIC Errors */ if (evt <=3D UFS_EVT_DME_ERR) { - dev_info(hba->dev, - "Host UIC Error Code (%s): %08x\n", - ufs_uic_err_str[evt], val); + dev_err(hba->dev, "Host UIC Error Code (%s): %08x\n", + ufs_uic_err_str[evt], val); reg =3D val; } =20 if (evt =3D=3D UFS_EVT_PA_ERR) { for_each_set_bit(bit, ®, ARRAY_SIZE(ufs_uic_pa_err_str)) - dev_info(hba->dev, "%s\n", ufs_uic_pa_err_str[bit]); + dev_err(hba->dev, "%s\n", ufs_uic_pa_err_str[bit]); } =20 if (evt =3D=3D UFS_EVT_DL_ERR) { for_each_set_bit(bit, ®, ARRAY_SIZE(ufs_uic_dl_err_str)) - dev_info(hba->dev, "%s\n", ufs_uic_dl_err_str[bit]); + dev_err(hba->dev, "%s\n", ufs_uic_dl_err_str[bit]); } } =20 @@ -2147,7 +2134,7 @@ static int ufs_mtk_mcq_config_resource(struct ufs_hba= *hba) =20 /* fail mcq initialization if interrupt is not filled properly */ if (!host->mcq_nr_intr) { - dev_info(hba->dev, "IRQs not ready. MCQ disabled."); + dev_err(hba->dev, "IRQs not ready. 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Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 While ufs_mtk_wait_idle state has some code smells for me (the VS_HCE_BASE early exit seems racey at best), it can still benefit from some general cleanup to make the code flow less convoluted. Use the iopoll helpers, for one, and specifically the one that sleeps and does not busy delay, as it's being done for up to 5ms. The register read is split out to a helper function that branches between new and old style flow. Every called uses the same 5ms timeout value, so there is no point in making this a parameter. Just assume a 5ms timeout in the function. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 71 +++++++++++++++++--------------------= ---- 1 file changed, 30 insertions(+), 41 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 8c9daf005e12..b07776f45acb 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -380,51 +381,39 @@ static void ufs_mtk_dbg_sel(struct ufs_hba *hba) } } =20 -static int ufs_mtk_wait_idle_state(struct ufs_hba *hba, - unsigned long retry_ms) +static u32 ufs_mtk_read_state(struct ufs_hba *hba, bool old_style) { - u64 timeout, time_checked; - u32 val, sm; - bool wait_idle; - struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); - - /* cannot use plain ktime_get() in suspend */ - timeout =3D ktime_get_mono_fast_ns() + retry_ms * 1000000UL; - - /* wait a specific time after check base */ - udelay(10); - wait_idle =3D false; + u32 val; =20 - do { - time_checked =3D ktime_get_mono_fast_ns(); - if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899) { - ufs_mtk_dbg_sel(hba); - val =3D ufshcd_readl(hba, REG_UFS_PROBE); - } else { - val =3D ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL); - val =3D val >> 16; - } + if (old_style) { + ufs_mtk_dbg_sel(hba); + val =3D ufshcd_readl(hba, REG_UFS_PROBE); + } else { + val =3D ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL) >> 16; + } =20 - sm =3D val & 0x1f; + return FIELD_GET(0x1f, val); +} =20 - /* - * if state is in H8 enter and H8 enter confirm - * wait until return to idle state. - */ - if ((sm >=3D VS_HIB_ENTER) && (sm <=3D VS_HIB_EXIT)) { - wait_idle =3D true; - udelay(50); - continue; - } else if (!wait_idle) - break; +static int ufs_mtk_wait_idle_state(struct ufs_hba *hba) +{ + struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); + bool old_style =3D (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899); + u32 val; + int ret; =20 - if (wait_idle && (sm =3D=3D VS_HCE_BASE)) - break; - } while (time_checked < timeout); + /* If the device is already in the base state after 10us, don't wait. */ + udelay(10); + if (ufs_mtk_read_state(hba, old_style) =3D=3D VS_HCE_BASE) + return 0; =20 - if (wait_idle && sm !=3D VS_HCE_BASE) { - dev_info(hba->dev, "wait idle tmo: 0x%x\n", val); - return -ETIMEDOUT; + /* Poll to wait for idle */ + ret =3D read_poll_timeout(ufs_mtk_read_state, val, + (val < VS_HIB_ENTER || val > VS_HIB_EXIT), 50, + 5 * USEC_PER_MSEC, false, hba, old_style); + if (ret) { + dev_err(hba->dev, "Timed out waiting for idle state, val =3D 0x%x\n", va= l); + return ret; } =20 return 0; @@ -1407,7 +1396,7 @@ static int ufs_mtk_auto_hibern8_disable(struct ufs_hb= a *hba) ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER); =20 /* wait host return to idle state when auto-hibern8 off */ - ret =3D ufs_mtk_wait_idle_state(hba, 5); + ret =3D ufs_mtk_wait_idle_state(hba); if (ret) goto out; =20 @@ -1611,7 +1600,7 @@ static int ufs_mtk_link_set_hpm(struct ufs_hba *hba) return err; =20 /* Check link state to make sure exit h8 success */ - err =3D ufs_mtk_wait_idle_state(hba, 5); + err =3D ufs_mtk_wait_idle_state(hba); if (err) { dev_err(hba->dev, "Failed to wait for idle: %pe\n", ERR_PTR(err)); return err; --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C1B033D6FE; Thu, 18 Dec 2025 12:58:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062697; cv=pass; b=sw5Zvm5wYDUYk7JvgQXWfMZoLuaReniRsb7MDIbYlLWk3f+mLZKmVrfJLP6q1/AXnwQrFfwuUe/CSIfFUyYcjElk21JrLfH0fKKK6XmK8AmsoDib+nUtI714Hh0DhQSvztIYLRkVHZO6Tx6uoWxrmJRFb66W12y1DR6mOMMJ9nA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=kP6+tesLXT6b6oe8yL/PwiMt0IZtyIkk3FBpDPLGZwE=; b=Shw6aL9ZZYU8f2qw1TB1B0HThItIk2Wqv0gB9mvnvQuDBb1TBjEgQmN5P31LB0ah X8s+4XJkjGtAZPrs/0Skb5sKU/NGpdTL/Y9GjgaItHNpMdRTsrTUgcnsyTIYnagfb5e 2X2u/QqKkLrY8+qEidHbcb9yyumaENk0ZSQVr3yo= Received: by mx.zohomail.com with SMTPS id 1766062658889766.5723795494483; Thu, 18 Dec 2025 04:57:38 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:55:10 +0100 Subject: [PATCH v4 20/25] scsi: ufs: mediatek: Don't acquire dvfsrc-vcore twice Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-20-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 As part of its featureset, the ufs-mediatek driver needs to play with an optional dvfsrc-vcore regulator for some of them. However, it currently does this by acquiring two different references to it in two different places, needlessly duplicating logic. Move reg_vcore to the host struct, acquire it in the same function as avdd09 is acquired, and rework the users of reg_vcore. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 73 +++++++++++++++++++------------------= ---- drivers/ufs/host/ufs-mediatek.h | 3 +- 2 files changed, 34 insertions(+), 42 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index b07776f45acb..a54c3aeb7bab 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -519,15 +519,13 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, = bool boost) { struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); struct ufs_mtk_crypt_cfg *cfg; - struct regulator *reg; int volt, ret; =20 - if (!ufs_mtk_is_boost_crypt_enabled(hba)) + if (!ufs_mtk_is_boost_crypt_enabled(hba) || !host->reg_vcore) return; =20 cfg =3D host->crypt; volt =3D cfg->vcore_volt; - reg =3D cfg->reg_vcore; =20 ret =3D clk_prepare_enable(cfg->clk_crypt_mux); if (ret) { @@ -537,7 +535,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bo= ol boost) } =20 if (boost) { - ret =3D regulator_set_voltage(reg, volt, INT_MAX); + ret =3D regulator_set_voltage(host->reg_vcore, volt, INT_MAX); if (ret) { dev_err(hba->dev, "%s: Failed to set vcore to %d: %pe\n", __func__, volt, ERR_PTR(ret)); @@ -548,7 +546,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bo= ol boost) if (ret) { dev_err(hba->dev, "%s: Failed to reparent clk_crypt_perf: %pe\n", __func__, ERR_PTR(ret)); - regulator_set_voltage(reg, 0, INT_MAX); + regulator_set_voltage(host->reg_vcore, 0, INT_MAX); goto out; } } else { @@ -559,7 +557,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bo= ol boost) goto out; } =20 - ret =3D regulator_set_voltage(reg, 0, INT_MAX); + ret =3D regulator_set_voltage(host->reg_vcore, 0, INT_MAX); if (ret) { dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n", __func__, ERR_PTR(ret)); @@ -576,16 +574,13 @@ static int ufs_mtk_init_boost_crypt(struct ufs_hba *h= ba) struct device *dev =3D hba->dev; int ret; =20 + if (!host->reg_vcore) + return 0; + cfg =3D devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL); if (!cfg) return -ENOMEM; =20 - cfg->reg_vcore =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); - if (IS_ERR(cfg->reg_vcore)) { - dev_err(dev, "Failed to get dvfsrc-vcore: %pe", cfg->reg_vcore); - return PTR_ERR(cfg->reg_vcore); - } - ret =3D of_property_read_u32(dev->of_node, "mediatek,boost-crypt-vcore-mi= n", &cfg->vcore_volt); if (ret) { @@ -891,7 +886,6 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) struct list_head *head =3D &hba->clk_list_head; struct ufs_clk_info *clki, *clki_tmp; struct device *dev =3D hba->dev; - struct regulator *reg; u32 volt; =20 /* @@ -932,16 +926,8 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) return; } =20 - /* - * Default get vcore if dts have these settings. - * No matter clock scaling support or not. (may disable by customer) - */ - reg =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); - if (IS_ERR(reg)) { - if (PTR_ERR(reg) !=3D -ENODEV) - dev_err(dev, "Failed to get dvfsrc-vcore: %pe\n", reg); + if (!host->reg_vcore) return; - } =20 if (of_property_read_u32(dev->of_node, "mediatek,clk-scale-up-vcore-min", &volt)) { @@ -949,12 +935,11 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) return; } =20 - host->mclk.reg_vcore =3D reg; host->mclk.vcore_volt =3D volt; =20 /* If default boot is max gear, request vcore */ - if (reg && volt && host->clk_scale_up) - if (regulator_set_voltage(reg, volt, INT_MAX)) + if (volt && host->clk_scale_up) + if (regulator_set_voltage(host->reg_vcore, volt, INT_MAX)) dev_err(hba->dev, "Failed to set vcore to %d\n", volt); } =20 @@ -1066,6 +1051,17 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host = *host) const struct ufs_mtk_soc_data *data =3D of_device_get_match_data(dev); int ret; =20 + host->reg_vcore =3D devm_regulator_get_optional(dev, "dvfsrc-vcore"); + if (IS_ERR(host->reg_vcore)) { + if (PTR_ERR(host->reg_vcore) !=3D -ENODEV) { + dev_err(dev, "Failed to get dvfsrc-vcore supply: %pe\n", + host->reg_vcore); + return PTR_ERR(host->reg_vcore); + } + + host->reg_vcore =3D NULL; + } + if (!data) return 0; =20 @@ -1099,14 +1095,13 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host= *host) =20 host->reg_avdd09 =3D devm_regulator_get_optional(dev, "avdd09"); if (IS_ERR(host->reg_avdd09)) { - if (PTR_ERR(host->reg_avdd09) =3D=3D -ENODEV) { - host->reg_avdd09 =3D NULL; - return 0; + if (PTR_ERR(host->reg_avdd09) !=3D -ENODEV) { + dev_err(dev, "Failed to get avdd09 regulator: %pe\n", + host->reg_avdd09); + return PTR_ERR(host->reg_avdd09); } =20 - dev_err(dev, "Failed to get avdd09 regulator: %pe\n", - host->reg_avdd09); - return PTR_ERR(host->reg_avdd09); + host->reg_avdd09 =3D NULL; } =20 return 0; @@ -1137,6 +1132,10 @@ static int ufs_mtk_init(struct ufs_hba *hba) host->hba =3D hba; ufshcd_set_variant(hba, host); =20 + err =3D ufs_mtk_get_supplies(host); + if (err) + goto out_variant_clear; + /* Initialize host capability */ ufs_mtk_init_host_caps(hba); =20 @@ -1191,10 +1190,6 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 ufs_mtk_init_clocks(hba); =20 - err =3D ufs_mtk_get_supplies(host); - if (err) - goto out_phy_exit; - /* * ufshcd_vops_init() is invoked after * ufshcd_setup_clock(true) in ufshcd_hba_init() thus @@ -1940,7 +1935,6 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, b= ool scale_up) struct ufs_mtk_clk *mclk =3D &host->mclk; struct ufs_clk_info *clki =3D mclk->ufs_sel_clki; struct ufs_clk_info *fde_clki =3D mclk->ufs_fde_clki; - struct regulator *reg; int volt, ret =3D 0; bool clk_bind_vcore =3D false; bool clk_fde_scale =3D false; @@ -1951,9 +1945,8 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, b= ool scale_up) if (!clki || !fde_clki) return; =20 - reg =3D host->mclk.reg_vcore; volt =3D host->mclk.vcore_volt; - if (reg && volt !=3D 0) + if (host->reg_vcore && volt) clk_bind_vcore =3D true; =20 if (mclk->ufs_fde_max_clki && mclk->ufs_fde_min_clki) @@ -1977,7 +1970,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, b= ool scale_up) =20 if (scale_up) { if (clk_bind_vcore) { - ret =3D regulator_set_voltage(reg, volt, INT_MAX); + ret =3D regulator_set_voltage(host->reg_vcore, volt, INT_MAX); if (ret) { dev_err(hba->dev, "Failed to set vcore to %d\n", volt); goto out; @@ -2017,7 +2010,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, b= ool scale_up) } =20 if (clk_bind_vcore) { - ret =3D regulator_set_voltage(reg, 0, INT_MAX); + ret =3D regulator_set_voltage(host->reg_vcore, 0, INT_MAX); if (ret) { dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n", __func__, ERR_PTR(ret)); diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index 5f096ed3f850..9586fe9c0441 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -141,7 +141,6 @@ enum ufs_mtk_host_caps { }; =20 struct ufs_mtk_crypt_cfg { - struct regulator *reg_vcore; struct clk *clk_crypt_perf; struct clk *clk_crypt_mux; struct clk *clk_crypt_lp; @@ -155,7 +154,6 @@ struct ufs_mtk_clk { struct ufs_clk_info *ufs_fde_clki; /* Mux */ struct ufs_clk_info *ufs_fde_max_clki; /* Max src */ struct ufs_clk_info *ufs_fde_min_clki; /* Min src */ - struct regulator *reg_vcore; int vcore_volt; }; =20 @@ -174,6 +172,7 @@ struct ufs_mtk_mcq_intr_info { struct ufs_mtk_host { struct phy *mphy; struct regulator *reg_avdd09; + struct regulator *reg_vcore; struct regulator_bulk_data *reg_misc; u8 num_reg_misc; struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS]; --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA32833D6CE; Thu, 18 Dec 2025 12:58:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062697; cv=pass; b=JUcebmSBQkiCT3ZbC7pHlaiVfZiH/m6KG3iIQsVBIyzy7/ZLeOCaNOxoWANJ1NfsbSsmAwPiwevwM8tcpBfJkgBxXQA/hrdbWGn/ESWSdjWOHko9cVAgn1OlLmu4Tpg+JNHzZlupIvhzXA1zfw0PYCr6Zz0s3VmAajBg1biE7XY= ARC-Message-Signature: i=2; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=zzJCSw73+4MzdkJoQR7lmQfAP5gggU/hOP3HQVDhUl8=; b=VNSBXX3IR6hks4zef6m3nfBPv3wtnxV2nkgJFJmMWMS5HwRvSY7luNeDZ9Sdw/s5 cM6DkNWNfSJbFO5B664LlxX5Sj57/zMmLcwLWVhhel88aXK3pYaf1+cTexxjdZOy8Af UGoG4hb0hknrfYagiLYBuqeQtGFoenafAxM6sMCE= Received: by mx.zohomail.com with SMTPS id 1766062665249280.6407866877553; Thu, 18 Dec 2025 04:57:45 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:55:11 +0100 Subject: [PATCH v4 21/25] scsi: ufs: mediatek: Rework hardware version reading Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-21-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Split assignment to the host struct out from the read function, and utilise bitfield helpers to simplify the code. Also move the debug print out of the legacy version helper, which means it no longer has to take a struct ufs_hba as an input, and can be rewritten as a pure function. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 65 +++++++++++++++++++++----------------= ---- 1 file changed, 33 insertions(+), 32 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index a54c3aeb7bab..4e545cc414ac 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -799,50 +799,47 @@ static void ufs_mtk_mcq_set_irq_affinity(struct ufs_h= ba *hba, unsigned int cpu) dev_dbg(hba->dev, "set irq %d affinity to CPU %d\n", irq, _cpu); } =20 -static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *hba, u32 hw_ip_ver) +static bool __pure ufs_mtk_is_legacy_chipset(u32 hw_ip_ver) { - bool is_legacy =3D false; - switch (hw_ip_ver) { case IP_LEGACY_VER_MT6893: case IP_LEGACY_VER_MT6781: /* can add other legacy chipset ID here accordingly */ - is_legacy =3D true; - break; - default: - break; + return true; } - dev_dbg(hba->dev, "IP version 0x%x, legacy =3D %s", hw_ip_ver, - str_true_false(is_legacy)); =20 - return is_legacy; + return false; } =20 -/* - * HW version format has been changed from 01MMmmmm to 1MMMmmmm, since - * project MT6878. In order to perform correct version comparison, - * version number is changed by SW for the following projects. - * IP_VER_MT6983 0x00360000 to 0x10360000 - * IP_VER_MT6897 0x01440000 to 0x10440000 - * IP_VER_MT6989 0x01450000 to 0x10450000 - * IP_VER_MT6991 0x01460000 to 0x10460000 +#define MTK_UFS_VER_PREFIX_M (0xFF << 24) + +/** + * ufs_mtk_get_hw_ip_version - read and return adjusted hardware version + * @hba: pointer to this device's &struct ufs_hba + * + * Reads, transforms and returns the hardware version. + * + * Since MT6878, the versioning scheme was changed from 01MMmmmm to 1MMMmm= mm. + * In order to support version comparisons across these different versioni= ng + * schemes, this function transforms the older style to the newer one. + * + * For example: + * MT6983 is transformed from 0x00360000 to 0x10360000 + * MT6897 is transformed from 0x01440000 to 0x10440000 + * MT6989 is transformed from 0x01450000 to 0x10450000 + * MT6991 is transformed from 0x01460000 to 0x10460000 + * + * Returns a u32 representing the hardware version. */ -static void ufs_mtk_get_hw_ip_version(struct ufs_hba *hba) +static u32 ufs_mtk_get_hw_ip_version(struct ufs_hba *hba) { - struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); - u32 hw_ip_ver; + u32 version =3D ufshcd_readl(hba, REG_UFS_MTK_IP_VER); + u32 prefix =3D FIELD_GET(MTK_UFS_VER_PREFIX_M, version); =20 - hw_ip_ver =3D ufshcd_readl(hba, REG_UFS_MTK_IP_VER); + if (prefix <=3D 1) + FIELD_MODIFY(MTK_UFS_VER_PREFIX_M, &version, BIT(28)); =20 - if (((hw_ip_ver & (0xFF << 24)) =3D=3D (0x1 << 24)) || - ((hw_ip_ver & (0xFF << 24)) =3D=3D 0)) { - hw_ip_ver &=3D ~(0xFF << 24); - hw_ip_ver |=3D (0x1 << 28); - } - - host->ip_ver =3D hw_ip_ver; - - host->legacy_ip_ver =3D ufs_mtk_is_legacy_chipset(hba, hw_ip_ver); + return version; } =20 static void ufs_mtk_get_controller_version(struct ufs_hba *hba) @@ -1209,7 +1206,11 @@ static int ufs_mtk_init(struct ufs_hba *hba) =20 ufs_mtk_setup_clocks(hba, true, POST_CHANGE); =20 - ufs_mtk_get_hw_ip_version(hba); + host->ip_ver =3D ufs_mtk_get_hw_ip_version(hba); + host->legacy_ip_ver =3D ufs_mtk_is_legacy_chipset(host->ip_ver); + + dev_dbg(hba->dev, "IP version 0x%x, legacy =3D %s", host->ip_ver, + str_true_false(host->legacy_ip_ver)); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-22-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 The MediaTek UFS driver uses a function-scope static variable to back up a hardware register across a power change in the ufs_mtk_pwr_change_notify function. This is dangerous, as it's only correct if only ever one instance of the driver is loaded, which isn't true if there's more than one device on a SoC that needs it, or it otherwise gets loaded a second time. Back it up into a member of the host struct instead, as this struct is per-instance. Rework the function to not use a pointless "ret" local as well. Fixes: f5ca8d0c7a63 ("scsi: ufs: host: mediatek: Disable auto-hibern8 durin= g power mode changes") Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 20 ++++++++------------ drivers/ufs/host/ufs-mediatek.h | 1 + 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 4e545cc414ac..147beb46a447 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1416,28 +1416,24 @@ static int ufs_mtk_pwr_change_notify(struct ufs_hba= *hba, const struct ufs_pa_layer_attr *dev_max_params, struct ufs_pa_layer_attr *dev_req_params) { - int ret =3D 0; - static u32 reg; + struct ufs_mtk_host *host =3D ufshcd_get_variant(hba); =20 switch (stage) { case PRE_CHANGE: if (ufshcd_is_auto_hibern8_supported(hba)) { - reg =3D ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER); + host->hibernate_idle_timer =3D ufshcd_readl( + hba, REG_AUTO_HIBERNATE_IDLE_TIMER); ufs_mtk_auto_hibern8_disable(hba); } - ret =3D ufs_mtk_pre_pwr_change(hba, dev_max_params, - dev_req_params); - break; + return ufs_mtk_pre_pwr_change(hba, dev_max_params, dev_req_params); case POST_CHANGE: if (ufshcd_is_auto_hibern8_supported(hba)) - ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER); - break; - default: - ret =3D -EINVAL; - break; + ufshcd_writel(hba, host->hibernate_idle_timer, + REG_AUTO_HIBERNATE_IDLE_TIMER); + return 0; } =20 - return ret; + return -EINVAL; } =20 static int ufs_mtk_unipro_set_lpm(struct ufs_hba *hba, bool lpm) diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediate= k.h index 9586fe9c0441..59fc432c84b5 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -189,6 +189,7 @@ struct ufs_mtk_host { u16 ref_clk_gating_wait_us; u32 ip_ver; bool legacy_ip_ver; + u32 hibernate_idle_timer; =20 bool mcq_set_intr; bool is_mcq_intr_enabled; --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40A6433BBA3; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-23-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 The scale_us values are constant, and should be declared as such. Do this, and use ARRAY_SIZE instead of a fixed <=3D comparison before accessing members of the array, to avoid possible future mistakes. This results in the same assembly with clang, so there is no functional change, but it makes me feel better. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 147beb46a447..7c5d30a79456 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -942,10 +942,10 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) =20 static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba) { + const u32 scale_us[] =3D {1, 10, 100, 1000, 10000, 100000}; unsigned long flags; u32 ah_ms =3D 10; u32 ah_scale, ah_timer; - u32 scale_us[] =3D {1, 10, 100, 1000, 10000, 100000}; =20 if (ufshcd_is_clkgating_allowed(hba)) { if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit) { @@ -953,7 +953,7 @@ static void ufs_mtk_setup_clk_gating(struct ufs_hba *hb= a) hba->ahit); ah_timer =3D FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); - if (ah_scale <=3D 5) + if (ah_scale < ARRAY_SIZE(scale_us)) ah_ms =3D ah_timer * scale_us[ah_scale] / 1000; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-24-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Remove the "ret" local variable from ufs_mtk_link_startup_notify, as it's pointless; in all cases it is assigned, it is returned right after without being read first. Rework the code to just return directly, and get rid of the default branch while at it. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index 7c5d30a79456..bec726ea15b7 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1518,21 +1518,15 @@ static void ufs_mtk_post_link(struct ufs_hba *hba) static int ufs_mtk_link_startup_notify(struct ufs_hba *hba, enum ufs_notify_change_status stage) { - int ret =3D 0; - switch (stage) { case PRE_CHANGE: - ret =3D ufs_mtk_pre_link(hba); - break; + return ufs_mtk_pre_link(hba); case POST_CHANGE: ufs_mtk_post_link(hba); - break; - default: - ret =3D -EINVAL; - break; + return 0; } =20 - return ret; + return -EINVAL; } =20 static int ufs_mtk_device_reset(struct ufs_hba *hba) --=20 2.52.0 From nobody Fri Dec 19 19:03:10 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54EFC33ADBB; Thu, 18 Dec 2025 12:58:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062731; cv=pass; b=VlYmLRoX/P390wgRNofE0HMBkbMJnZfBJRMzgqjPEFVRkBnC9hLECxV/Lov/qs36O6f7Akvx0q3rs4fX9V+bU2QQ6sA3JHJN11TuwKVY+lb+SJj2J+2tRbtre3AMARWVBtZnvpOGvCdnB3sXFuW5HlyCP7UfI2mE7w4n/meB/Uk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766062731; c=relaxed/simple; bh=BhXVI3fYrnLGeitqMIEvuVbdjOcV8uaKX/xIKn7JnIw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JV3PncL3aSClbPzGpsyOh4yKz6ioJgXTLYvdP3vI+hzZaHIrsqH0kn7YgXNAz0pm7xF6FOOTfxUZlFyBemIruTO1+tbHAHKf8asVFtG0COFYbHljihw7iHEynld+Q61PTqmy2cGiGvyy2pilWrJwNplWn95nf2MLQgF5WNlOM6o= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=X6ntBvoq; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="X6ntBvoq" ARC-Seal: i=1; a=rsa-sha256; t=1766062693; cv=none; d=zohomail.com; s=zohoarc; b=hyywE5dyVcThw+4qeNZ+H14mxwwRPxhf1e3BGLJkGVINGDH8CKvOdxHlTzzFA0EUcbfKxlTvExUQMBuQQdZtoXOLhYDNIj7RkCfvySSxs6UFQC1w95WI1FQCkCjbw1NEVbpL+7n4p660sZCzTXixxt/rWHMaolU8znkFfEJZU38= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766062693; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=kt6Xk+wA/MGprNVHAljiDI81GSDcfkOv+QkFybI0sNc=; b=MQVgNMhj05ufiTPjNOr8FFnSUjWlETFh2bEXqcoeb4RzIIWz2pmk2Xo6Lxdf10gvETKsxeV1wvCmGD2YLm1rCbGXIRs6YASDSZ+MBkJmyTc4yYXU3NLdpn47ZdxyiscaMlFxlg91P1IVzbEaEcg5KQbJpKad73TGub35+T5v0bY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1766062692; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=kt6Xk+wA/MGprNVHAljiDI81GSDcfkOv+QkFybI0sNc=; b=X6ntBvoqAQ7vP3DosBdzHq++GF4v2njQ8691hEHownQyPJuVjkGyUZCQQFHyDoVe Z7GPR1glWSSgdKmdnYRF/YbodxBsheLfVMGRZ2L+AHs/Hym7Ln1SoNzk0JprWu+ApaH 4hFz3x/CVb8Zskv/EPj+KQi+EiQt/b/A4z+6ZFaY= Received: by mx.zohomail.com with SMTPS id 1766062691694245.72284616675836; Thu, 18 Dec 2025 04:58:11 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 18 Dec 2025 13:55:15 +0100 Subject: [PATCH v4 25/25] scsi: ufs: mediatek: Add MT8196 compatible, update copyright Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-mt8196-ufs-v4-25-ddec7a369dd2@collabora.com> References: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> In-Reply-To: <20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown , Chaotian Jing , Neil Armstrong Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 THe MT8196's UFS controller has a new compatible. Add the necessary struct definitions to support it. Also update the copyrights and authors, without tabs following spaces to avoid checkpatch errors, to list myself as having contributed to this driver after the preceding rework patches. Signed-off-by: Nicolas Frattaroli --- drivers/ufs/host/ufs-mediatek.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediate= k.c index bec726ea15b7..09be752c3c0f 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1,9 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 MediaTek Inc. + * Copyright (C) 2025 Collabora Ltd. * Authors: - * Stanley Chu - * Peter Wang + * Stanley Chu + * Peter Wang + * Nicolas Frattaroli (Major clean= ups) */ =20 #include @@ -2243,6 +2245,10 @@ static const char *const ufs_mtk_regs_avdd12_ckbuf_a= vdd18[] =3D { "avdd12", "avdd12-ckbuf", "avdd18" }; =20 +static const char *const ufs_mtk_regs_avdd12_ckbuf[] =3D { + "avdd12", "avdd12-ckbuf" +}; + static const struct ufs_mtk_soc_data mt8183_data =3D { .has_avdd09 =3D true, .reg_names =3D ufs_mtk_regs_avdd12_avdd18, @@ -2255,10 +2261,17 @@ static const struct ufs_mtk_soc_data mt8192_8195_da= ta =3D { .num_reg_names =3D ARRAY_SIZE(ufs_mtk_regs_avdd12_ckbuf_avdd18), }; =20 +static const struct ufs_mtk_soc_data mt8196_data =3D { + .has_avdd09 =3D true, + .reg_names =3D ufs_mtk_regs_avdd12_ckbuf, + .num_reg_names =3D ARRAY_SIZE(ufs_mtk_regs_avdd12_ckbuf), +}; + static const struct of_device_id ufs_mtk_of_match[] =3D { { .compatible =3D "mediatek,mt8183-ufshci", .data =3D &mt8183_data }, { .compatible =3D "mediatek,mt8192-ufshci", .data =3D &mt8192_8195_data }, { .compatible =3D "mediatek,mt8195-ufshci", .data =3D &mt8192_8195_data }, + { .compatible =3D "mediatek,mt8196-ufshci", .data =3D &mt8196_data }, {}, }; MODULE_DEVICE_TABLE(of, ufs_mtk_of_match); --=20 2.52.0