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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b04e58d423sm2564824eec.6.2025.12.18.00.10.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 00:10:49 -0800 (PST) From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:48 -0800 Subject: [PATCH v2 08/12] coresight-tmc-etf: Refactor enable function for CPU cluster ETF support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-cpu_cluster_component_pm-v2-8-2335a6ae62a0@oss.qualcomm.com> References: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> In-Reply-To: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang , maulik.shah@oss.qualcomm.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766045439; l=5305; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=1g8pF946hN6QW1p+2Y+2RyrV1bnSaFCc0AvdfQQfoFE=; b=WalzKq5mo+m1DDBa+j4hcG65FGQtoJ3y4iK+EaoBGFEl1Vw118qcQjkGDdZHOm1k6i33ttt5x 1kKC8wGvW7OBjHIQk7Fy4CY0PWitDwlSVzZ8QiZKiX/Izb0Z5cmPHwy X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE4MDA2NiBTYWx0ZWRfXxqn+1JPv2NGr 1ibi6+J6b0ZgpWVmabtXiduG86myGwlDk8TtI58/YKpCAcFn+fa5FFTqMthU+Le8OjatyATB92r Gvrbs2h2ylL0QOMCqnA4jLDo3ly5mtW+zbbasNR3hZG1MMf34KSt1SMT/7J9kx7ayMS3iRITO4s bsA4Qf9coAcdoEj01v2z3LOYaRXftkbmZ/SJfXyPzng4xJke7fR5VgNRLiL5xi7f/a+/8gRwelw 37aEddvC8/ir/usRLJYLeLcjvQXcaevCdn9NOYQBYL2eh0MtX8ii6cADe+42699mIFP294N6VN3 1N1+X2VcrpxA16mHblYkBVNMe33VDPsmFQhARJTDoFsX7ca7JsTU/uTDZTIumJb5EkZPptv9FRn xayVRGx4o2nMF+Mif52LwFleTDtIQg== X-Proofpoint-GUID: QpOLvbSU1m8_Km-3UefQEUIeMGTICPPu X-Proofpoint-ORIG-GUID: QpOLvbSU1m8_Km-3UefQEUIeMGTICPPu X-Authority-Analysis: v=2.4 cv=Zpjg6t7G c=1 sm=1 tr=0 ts=6943b70b cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ArRTHoG_oAt2a2GmjD0A:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-18_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 clxscore=1015 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512180066 TMC-ETF devices associated with specific CPU clusters share the cluster's power domain. Accessing their registers requires the cluster to be powered on, which can only be guaranteed by running code on a CPU within that cluster. Refactor the enablement logic to support this requirement: 1. Split `tmc_etf_enable_hw` and `tmc_etb_enable_hw` into local and SMP-aware variants: - `*_local`: Performs the actual register access. - `*_smp_call`: Wrapper for `smp_call_function_single`. - The main entry point now detects if the device is CPU-bound and uses `smp_call_function_single` to execute the local variant on an appropriate CPU if necessary. 2. Adjust locking in `tmc_enable_etf_sink_sysfs` and `tmc_enable_etf_link`: - Drop the spinlock before calling `tmc_etf_enable_hw`. This is necessary because `smp_call_function_single` (used for cross-CPU calls) may require interrupts enabled or might sleep/wait, which is unsafe under a spinlock. - Re-acquire the lock afterwards to update driver state. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 87 +++++++++++++++++++++= +--- 1 file changed, 77 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtr= acing/coresight/coresight-tmc-etf.c index 8882b1c4cdc05353fb2efd6a9ba862943048f0ff..11357788e9d93c53980e99e0ef7= 8450e393f4059 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -47,7 +47,7 @@ static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdat= a) return rc; } =20 -static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) +static int tmc_etb_enable_hw_local(struct tmc_drvdata *drvdata) { int rc =3D coresight_claim_device(drvdata->csdev); =20 @@ -60,6 +60,36 @@ static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) return rc; } =20 +struct tmc_smp_arg { + struct tmc_drvdata *drvdata; + int rc; +}; + +static void tmc_etb_enable_hw_smp_call(void *info) +{ + struct tmc_smp_arg *arg =3D info; + + arg->rc =3D tmc_etb_enable_hw_local(arg->drvdata); +} + +static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) +{ + int cpu, ret; + struct tmc_smp_arg arg =3D { 0 }; + + if (!drvdata->supported_cpus) + return tmc_etb_enable_hw_local(drvdata); + + arg.drvdata =3D drvdata; + for_each_cpu(cpu, drvdata->supported_cpus) { + ret =3D smp_call_function_single(cpu, + tmc_etb_enable_hw_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + return ret; +} + static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata) { char *bufp; @@ -130,7 +160,7 @@ static int __tmc_etf_enable_hw(struct tmc_drvdata *drvd= ata) return rc; } =20 -static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) +static int tmc_etf_enable_hw_local(struct tmc_drvdata *drvdata) { int rc =3D coresight_claim_device(drvdata->csdev); =20 @@ -143,6 +173,32 @@ static int tmc_etf_enable_hw(struct tmc_drvdata *drvda= ta) return rc; } =20 +static void tmc_etf_enable_hw_smp_call(void *info) +{ + struct tmc_smp_arg *arg =3D info; + + arg->rc =3D tmc_etf_enable_hw_local(arg->drvdata); +} + +static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) +{ + int cpu, ret; + struct tmc_smp_arg arg =3D { 0 }; + + if (!drvdata->supported_cpus) + return tmc_etf_enable_hw_local(drvdata); + + arg.drvdata =3D drvdata; + + for_each_cpu(cpu, drvdata->supported_cpus) { + ret =3D smp_call_function_single(cpu, + tmc_etf_enable_hw_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + return ret; +} + static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata) { struct coresight_device *csdev =3D drvdata->csdev; @@ -228,7 +284,11 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_= device *csdev) used =3D true; drvdata->buf =3D buf; } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + ret =3D tmc_etb_enable_hw(drvdata); + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); if (!ret) { coresight_set_mode(csdev, CS_MODE_SYSFS); csdev->refcnt++; @@ -291,7 +351,11 @@ static int tmc_enable_etf_sink_perf(struct coresight_d= evice *csdev, break; } =20 - ret =3D tmc_etb_enable_hw(drvdata); + if (drvdata->supported_cpus && + !cpumask_test_cpu(smp_processor_id(), drvdata->supported_cpus)) + break; + + ret =3D tmc_etb_enable_hw_local(drvdata); if (!ret) { /* Associate with monitored process. */ drvdata->pid =3D pid; @@ -376,19 +440,22 @@ static int tmc_enable_etf_link(struct coresight_devic= e *csdev, return -EBUSY; } =20 - if (csdev->refcnt =3D=3D 0) { + if (csdev->refcnt =3D=3D 0) + first_enable =3D true; + + if (!first_enable) + csdev->refcnt++; + + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + if (first_enable) { ret =3D tmc_etf_enable_hw(drvdata); if (!ret) { coresight_set_mode(csdev, CS_MODE_SYSFS); - first_enable =3D true; + csdev->refcnt++; + dev_dbg(&csdev->dev, "TMC-ETF enabled\n"); } } - if (!ret) - csdev->refcnt++; - raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 - if (first_enable) - dev_dbg(&csdev->dev, "TMC-ETF enabled\n"); return ret; } =20 --=20 2.34.1