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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b04e58d423sm2564824eec.6.2025.12.18.00.10.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 00:10:41 -0800 (PST) From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:42 -0800 Subject: [PATCH v2 02/12] coresight-funnel: Support CPU cluster funnel initialization Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-cpu_cluster_component_pm-v2-2-2335a6ae62a0@oss.qualcomm.com> References: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> In-Reply-To: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang , maulik.shah@oss.qualcomm.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766045439; l=9011; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=Fpp/5eQxMyG5rpvoNvxSYiDKJ7rnTCbi3mj2igPMxLU=; b=BavpAy9r7xKAgf/EbkDhLS/jCe/ZLPOLxE+sU7ckt40H3lLyYD/fFw77y3H7DyHloXrCfJK9C K6Bc7EKVjfMD71KSm5dlRQXRyjiuhr6czi4m3WboiAsLxZvj4T1Jz6e X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-ORIG-GUID: GBXv0OmMkXi1HevBM0vkLrg7hTW7VEPQ X-Proofpoint-GUID: GBXv0OmMkXi1HevBM0vkLrg7hTW7VEPQ X-Authority-Analysis: v=2.4 cv=f8JFxeyM c=1 sm=1 tr=0 ts=6943b704 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ntKk2pyKPOpeOXeRekoA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE4MDA2NiBTYWx0ZWRfX0uhvcLauzp3c 4RWRmYqYCefMdvM/cIdhBGmhEVBCvY/+7eNwWKT1bBOJIrHu7Be6O9GpKmCjB0uWWLqv1Y9tK/K J6YTQRLlll22gtQYPdklTKhEDUCefnae347rIwp8aKANnk5eHlJAyj+0P8P7IQDxfMlwDf+0mFV fHXaRH96OI7fmDTWepTPHErx4IcVvwgo2OF0MwIPh19/EMllBWtGAFeem0bKou5HyifEkpayjC0 Xwt/uYoeQAxqv3pTu7jVAAY1q7uSaiZHMWwt3eKgyfl1vCBeKGgyg7rXWiRb7PRPcy1FKzGAtIf FoDtSgUj1/sh5YK5pxdqzkSP32ObY3MHwpb+geDtMo2I8hHO7guHmmDe+bAv/9IFRsbLsNUUCU8 irtHCZG/i3fshLUnpJMItJRp+x6bZg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-18_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 clxscore=1015 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512180066 Funnels associated with CPU clusters reside in the cluster's power domain. Unlike dynamic funnels (which are typically system-wide), these per-cluster funnels are only accessible when the cluster is powered on. Standard runtime PM may not suffice to wake up a cluster from low-power states, making direct register access unreliable. Enhance the funnel driver to support these per-cluster devices: 1. Safe Initialization: - Identify CPU cluster funnels via "qcom,cpu-bound-components". - Use smp_call_function_single() to perform hardware initialization (claim tag clearing) on a CPU within the cluster. - Refactor the probe flow to encapsulate device registration in funnel_add_coresight_dev(). 2. Cross-CPU Enablement: - Update funnel_enable() to use smp_call_function_single() when enabling the hardware on a cluster-bound funnel. 3. Debug Interface Support: - Update funnel_ctrl_show() to safely read the control register via cross-CPU calls when necessary. This ensures that funnel operations remain safe and functional even when the associated CPU cluster is in aggressive low-power states. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-funnel.c | 183 ++++++++++++++++++++-= ---- 1 file changed, 152 insertions(+), 31 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtra= cing/coresight/coresight-funnel.c index 3b248e54471a38f501777fe162fea850d1c851b3..a1264df84ab4c625c63dfbb9b77= 10b983a10c6b4 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,7 @@ DEFINE_CORESIGHT_DEVLIST(funnel_devs, "funnel"); * @csdev: component vitals needed by the framework. * @priority: port selection order. * @spinlock: serialize enable/disable operations. + * @supported_cpus: Represent the CPUs related to this funnel. */ struct funnel_drvdata { void __iomem *base; @@ -48,6 +50,13 @@ struct funnel_drvdata { struct coresight_device *csdev; unsigned long priority; raw_spinlock_t spinlock; + struct cpumask *supported_cpus; +}; + +struct funnel_smp_arg { + struct funnel_drvdata *drvdata; + int port; + int rc; }; =20 static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int po= rt) @@ -76,6 +85,33 @@ static int dynamic_funnel_enable_hw(struct funnel_drvdat= a *drvdata, int port) return rc; } =20 +static void funnel_enable_hw_smp_call(void *info) +{ + struct funnel_smp_arg *arg =3D info; + + arg->rc =3D dynamic_funnel_enable_hw(arg->drvdata, arg->port); +} + +static int funnel_enable_hw(struct funnel_drvdata *drvdata, int port) +{ + int cpu, ret; + struct funnel_smp_arg arg =3D { 0 }; + + if (!drvdata->supported_cpus) + return dynamic_funnel_enable_hw(drvdata, port); + + arg.drvdata =3D drvdata; + arg.port =3D port; + + for_each_cpu(cpu, drvdata->supported_cpus) { + ret =3D smp_call_function_single(cpu, + funnel_enable_hw_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + return ret; +} + static int funnel_enable(struct coresight_device *csdev, struct coresight_connection *in, struct coresight_connection *out) @@ -86,19 +122,24 @@ static int funnel_enable(struct coresight_device *csde= v, bool first_enable =3D false; =20 raw_spin_lock_irqsave(&drvdata->spinlock, flags); - if (in->dest_refcnt =3D=3D 0) { - if (drvdata->base) - rc =3D dynamic_funnel_enable_hw(drvdata, in->dest_port); - if (!rc) - first_enable =3D true; - } - if (!rc) + + if (in->dest_refcnt =3D=3D 0) + first_enable =3D true; + else in->dest_refcnt++; + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 - if (first_enable) - dev_dbg(&csdev->dev, "FUNNEL inport %d enabled\n", - in->dest_port); + if (first_enable) { + if (drvdata->base) + rc =3D funnel_enable_hw(drvdata, in->dest_port); + if (!rc) { + in->dest_refcnt++; + dev_dbg(&csdev->dev, "FUNNEL inport %d enabled\n", + in->dest_port); + } + } + return rc; } =20 @@ -188,15 +229,39 @@ static u32 get_funnel_ctrl_hw(struct funnel_drvdata *= drvdata) return functl; } =20 +static void get_funnel_ctrl_smp_call(void *info) +{ + struct funnel_smp_arg *arg =3D info; + + arg->rc =3D get_funnel_ctrl_hw(arg->drvdata); +} + static ssize_t funnel_ctrl_show(struct device *dev, struct device_attribute *attr, char *buf) { u32 val; + int cpu, ret; struct funnel_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + struct funnel_smp_arg arg =3D { 0 }; =20 pm_runtime_get_sync(dev->parent); - - val =3D get_funnel_ctrl_hw(drvdata); + if (!drvdata->supported_cpus) { + val =3D get_funnel_ctrl_hw(drvdata); + } else { + arg.drvdata =3D drvdata; + for_each_cpu(cpu, drvdata->supported_cpus) { + ret =3D smp_call_function_single(cpu, + get_funnel_ctrl_smp_call, &arg, 1); + if (!ret) + break; + } + if (!ret) { + val =3D arg.rc; + } else { + pm_runtime_put(dev->parent); + return ret; + } + } =20 pm_runtime_put(dev->parent); =20 @@ -211,22 +276,68 @@ static struct attribute *coresight_funnel_attrs[] =3D= { }; ATTRIBUTE_GROUPS(coresight_funnel); =20 +static void funnel_clear_self_claim_tag(struct funnel_drvdata *drvdata) +{ + struct csdev_access access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + + coresight_clear_self_claim_tag(&access); +} + +static void funnel_init_on_cpu(void *info) +{ + struct funnel_drvdata *drvdata =3D info; + + funnel_clear_self_claim_tag(drvdata); +} + +static int funnel_add_coresight_dev(struct device *dev) +{ + struct coresight_desc desc =3D { 0 }; + struct funnel_drvdata *drvdata =3D dev_get_drvdata(dev); + + if (drvdata->base) { + desc.groups =3D coresight_funnel_groups; + desc.access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + } + + desc.name =3D coresight_alloc_device_name(&funnel_devs, dev); + if (!desc.name) + return -ENOMEM; + + desc.type =3D CORESIGHT_DEV_TYPE_LINK; + desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_MERG; + desc.ops =3D &funnel_cs_ops; + desc.pdata =3D dev->platform_data; + desc.dev =3D dev; + + drvdata->csdev =3D coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + return 0; +} + +static struct cpumask *funnel_get_supported_cpus(struct device *dev) +{ + struct generic_pm_domain *pd; + + pd =3D pd_to_genpd(dev->pm_domain); + if (pd) + return pd->cpus; + + return NULL; +} + static int funnel_probe(struct device *dev, struct resource *res) { void __iomem *base; struct coresight_platform_data *pdata =3D NULL; struct funnel_drvdata *drvdata; - struct coresight_desc desc =3D { 0 }; - int ret; + int cpu, ret; =20 if (is_of_node(dev_fwnode(dev)) && of_device_is_compatible(dev->of_node, "arm,coresight-funnel")) dev_warn_once(dev, "Uses OBSOLETE CoreSight funnel binding\n"); =20 - desc.name =3D coresight_alloc_device_name(&funnel_devs, dev); - if (!desc.name) - return -ENOMEM; - drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; @@ -244,9 +355,6 @@ static int funnel_probe(struct device *dev, struct reso= urce *res) if (IS_ERR(base)) return PTR_ERR(base); drvdata->base =3D base; - desc.groups =3D coresight_funnel_groups; - desc.access =3D CSDEV_ACCESS_IOMEM(base); - coresight_clear_self_claim_tag(&desc.access); } =20 dev_set_drvdata(dev, drvdata); @@ -258,23 +366,36 @@ static int funnel_probe(struct device *dev, struct re= source *res) dev->platform_data =3D pdata; =20 raw_spin_lock_init(&drvdata->spinlock); - desc.type =3D CORESIGHT_DEV_TYPE_LINK; - desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_MERG; - desc.ops =3D &funnel_cs_ops; - desc.pdata =3D pdata; - desc.dev =3D dev; - drvdata->csdev =3D coresight_register(&desc); - if (IS_ERR(drvdata->csdev)) - return PTR_ERR(drvdata->csdev); =20 - return 0; + if (fwnode_property_present(dev_fwnode(dev), "qcom,cpu-bound-components")= ) { + drvdata->supported_cpus =3D funnel_get_supported_cpus(dev); + if (!drvdata->supported_cpus) + return -EINVAL; + + cpus_read_lock(); + for_each_cpu(cpu, drvdata->supported_cpus) { + ret =3D smp_call_function_single(cpu, + funnel_init_on_cpu, drvdata, 1); + if (!ret) + break; + } + cpus_read_unlock(); + + if (ret) + return 0; + } else if (res) { + funnel_clear_self_claim_tag(drvdata); + } + + return funnel_add_coresight_dev(dev); } =20 static int funnel_remove(struct device *dev) { struct funnel_drvdata *drvdata =3D dev_get_drvdata(dev); =20 - coresight_unregister(drvdata->csdev); + if (drvdata->csdev) + coresight_unregister(drvdata->csdev); =20 return 0; } --=20 2.34.1