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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b04e58d423sm2564824eec.6.2025.12.18.00.10.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 00:10:52 -0800 (PST) From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:51 -0800 Subject: [PATCH v2 11/12] coresight: Pass trace mode to link enable callback Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-cpu_cluster_component_pm-v2-11-2335a6ae62a0@oss.qualcomm.com> References: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> In-Reply-To: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang , maulik.shah@oss.qualcomm.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766045439; l=9596; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=ZizRFuPaK/LitwSdLNplW7Ev2jbzENlbotIRtyE7yN8=; b=DvqIqB9difxf+/WNfzFJe9N1imzh6BaFyNq7kAFHLDqhsY5fPBidwE1QfWrPkOYyWGR1N6cRo d8tKIhkyqE/DoVZXOYngviSgeIOuKSuS9KNpN6JPBrG7YgwGpi32Fhr X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-ORIG-GUID: j79qlZ0DstXiOtFOmwYHarrNq3NQQUdf X-Proofpoint-GUID: j79qlZ0DstXiOtFOmwYHarrNq3NQQUdf X-Authority-Analysis: v=2.4 cv=f8JFxeyM c=1 sm=1 tr=0 ts=6943b70f cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=_ycWAoKx6aYVZ7XB0rUA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE4MDA2NiBTYWx0ZWRfX8RoUg8ccLql8 RkIKMhqI9yQXRxN5Nr9jO3zcJ6mgOVyYiO5yMh0Ud7gHjmssqx2QguC+A8A++iziLiMz859l/Hw DsMaH6X0uoUJ/D8ifltuKfkF/7tSrLDYzx/sJKWzEssg3eAJMb4thMH16ibzYrbiPwTbUJkFThz z+pZxx6xhSSZUKPBv3IX2zBQAbxyEwBTus97StjJXf4yZ1TENwCVRF+aLlqkOWZYh2NgHcMos5g DvnszjiR/Rsnzpri8owdqcmf0ZCJclukdHX4qbpdwlujhNP+kCJonpbTsM9sXdq0nbQpMN30+Hu Px3D8fueFfC/kBtXxmLvEQSgHAqeaKjCK/BW4t/gW34RweX0ibjHVL8wzum7NBWkr6oV+0mQF8l Itmv+RFppJv1mMjY2eYyfQ+Pmoy86Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-18_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 clxscore=1015 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512180066 Currently, the link enable callback does not receive the CoreSight mode (enum cs_mode). This prevents link drivers from knowing whether they are being enabled for SysFS or Perf. This distinction is crucial because Perf mode runs in atomic context, where certain operations (like smp_call_function_single()) are unsafe. Without knowing the mode, drivers cannot conditionally avoid these unsafe calls. Update the `enable` callback in `struct coresight_ops_link` to accept `enum cs_mode`. This allows drivers to implement mode-specific logic, such as using atomic-safe enablement sequences when running in Perf mode. Update all call sites and driver implementations accordingly. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-core.c | 7 ++++--- drivers/hwtracing/coresight/coresight-funnel.c | 21 ++++++++++++++++++= +- drivers/hwtracing/coresight/coresight-replicator.c | 23 ++++++++++++++++++= +++- drivers/hwtracing/coresight/coresight-tmc-etf.c | 19 +++++++++++++++++- drivers/hwtracing/coresight/coresight-tnoc.c | 3 ++- drivers/hwtracing/coresight/coresight-tpda.c | 3 ++- include/linux/coresight.h | 3 ++- 7 files changed, 70 insertions(+), 9 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index c660cf8adb1c7cafff8f85e501f056e4e151e372..1863bdb57281b4fd405cf966d56= 5c581506ea270 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -314,7 +314,8 @@ static void coresight_disable_sink(struct coresight_dev= ice *csdev) static int coresight_enable_link(struct coresight_device *csdev, struct coresight_device *parent, struct coresight_device *child, - struct coresight_device *source) + struct coresight_device *source, + enum cs_mode mode) { int link_subtype; struct coresight_connection *inconn, *outconn; @@ -331,7 +332,7 @@ static int coresight_enable_link(struct coresight_devic= e *csdev, if (link_subtype =3D=3D CORESIGHT_DEV_SUBTYPE_LINK_SPLIT && IS_ERR(outcon= n)) return PTR_ERR(outconn); =20 - return link_ops(csdev)->enable(csdev, inconn, outconn); + return link_ops(csdev)->enable(csdev, inconn, outconn, mode); } =20 static void coresight_disable_link(struct coresight_device *csdev, @@ -550,7 +551,7 @@ int coresight_enable_path(struct coresight_path *path, = enum cs_mode mode) case CORESIGHT_DEV_TYPE_LINK: parent =3D list_prev_entry(nd, link)->csdev; child =3D list_next_entry(nd, link)->csdev; - ret =3D coresight_enable_link(csdev, parent, child, source); + ret =3D coresight_enable_link(csdev, parent, child, source, mode); if (ret) goto err_disable_helpers; break; diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtra= cing/coresight/coresight-funnel.c index 5d114ce1109f4f9a8b108110bdae258f216881d8..c50522c2854c7193a8c30b1a603= abe566a1c1ccf 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -121,7 +121,8 @@ static int funnel_enable_hw(struct funnel_drvdata *drvd= ata, int port) =20 static int funnel_enable(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { int rc =3D 0; struct funnel_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); @@ -135,6 +136,23 @@ static int funnel_enable(struct coresight_device *csde= v, else in->dest_refcnt++; =20 + if (mode =3D=3D CS_MODE_PERF) { + if (first_enable) { + if (drvdata->supported_cpus && + !cpumask_test_cpu(smp_processor_id(), drvdata->supported_cpus)) { + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EINVAL; + } + + if (drvdata->base) + rc =3D dynamic_funnel_enable_hw(drvdata, in->dest_port); + if (!rc) + in->dest_refcnt++; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return rc; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 if (first_enable) { @@ -183,6 +201,7 @@ static void funnel_disable(struct coresight_device *csd= ev, dynamic_funnel_disable_hw(drvdata, in->dest_port); last_disable =3D true; } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 if (last_disable) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/h= wtracing/coresight/coresight-replicator.c index a9f22d0e15de21aa06c8d1e193e5db06091efd75..cc7d3916b8b9d5d342d6cde0487= 722eeb8dee78b 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -199,7 +199,8 @@ static int replicator_enable_hw(struct replicator_drvda= ta *drvdata, =20 static int replicator_enable(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { int rc =3D 0; struct replicator_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); @@ -212,6 +213,25 @@ static int replicator_enable(struct coresight_device *= csdev, first_enable =3D true; else out->src_refcnt++; + + if (mode =3D=3D CS_MODE_PERF) { + if (first_enable) { + if (drvdata->supported_cpus && + !cpumask_test_cpu(smp_processor_id(), drvdata->supported_cpus)) { + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EINVAL; + } + + if (drvdata->base) + rc =3D dynamic_replicator_enable(drvdata, in->dest_port, + out->src_port); + if (!rc) + out->src_refcnt++; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return rc; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 if (first_enable) { @@ -272,6 +292,7 @@ static void replicator_disable(struct coresight_device = *csdev, out->src_port); last_disable =3D true; } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 if (last_disable) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtr= acing/coresight/coresight-tmc-etf.c index 11357788e9d93c53980e99e0ef78450e393f4059..f1b8264b4e5c8a8d38778c25515= cbf557c0993b7 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -427,7 +427,8 @@ static int tmc_disable_etf_sink(struct coresight_device= *csdev) =20 static int tmc_enable_etf_link(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { int ret =3D 0; unsigned long flags; @@ -446,6 +447,22 @@ static int tmc_enable_etf_link(struct coresight_device= *csdev, if (!first_enable) csdev->refcnt++; =20 + if (mode =3D=3D CS_MODE_PERF) { + if (first_enable) { + if (drvdata->supported_cpus && + !cpumask_test_cpu(smp_processor_id(), drvdata->supported_cpus)) { + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EINVAL; + } + + ret =3D tmc_etf_enable_hw_local(drvdata); + if (!ret) + csdev->refcnt++; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); if (first_enable) { ret =3D tmc_etf_enable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtraci= ng/coresight/coresight-tnoc.c index ff9a0a9cfe96e5f5e3077c750ea2f890cdd50d94..48e9e685b9439d92bdaae9e40d3= b3bc2d1ac1cd2 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.c +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -73,7 +73,8 @@ static void trace_noc_enable_hw(struct trace_noc_drvdata = *drvdata) } =20 static int trace_noc_enable(struct coresight_device *csdev, struct coresig= ht_connection *inport, - struct coresight_connection *outport) + struct coresight_connection *outport, + enum cs_mode mode) { struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); =20 diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtraci= ng/coresight/coresight-tpda.c index 3a3825d27f861585ca1d847929747f8096004089..e6f52abc5b023a997c36d74c0e3= b1a3de8236ba2 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -190,7 +190,8 @@ static int __tpda_enable(struct tpda_drvdata *drvdata, = int port) =20 static int tpda_enable(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { struct tpda_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); int ret =3D 0; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 2b48be97fcd0d7ea2692206692bd33f35ba4ec79..218eb1d1dcef61f5d98ebbfff38= 370192b8a6e45 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -383,7 +383,8 @@ struct coresight_ops_sink { struct coresight_ops_link { int (*enable)(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out); + struct coresight_connection *out, + enum cs_mode mode); void (*disable)(struct coresight_device *csdev, struct coresight_connection *in, struct coresight_connection *out); --=20 2.34.1