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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b04e58d423sm2564824eec.6.2025.12.18.00.10.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 00:10:40 -0800 (PST) From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:41 -0800 Subject: [PATCH v2 01/12] dt-bindings: arm: coresight: Add 'qcom,cpu-bound-components' property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-cpu_cluster_component_pm-v2-1-2335a6ae62a0@oss.qualcomm.com> References: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> In-Reply-To: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang , maulik.shah@oss.qualcomm.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766045439; l=3052; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=+Jqa7JFXnLG9afqUMCpYAS5qCe7jJ7CCqJKnko2EM/E=; b=QxzfOTMXLpA75RWYYuwBvLFwkh6xifOv2aAmFGxZ7X3aUgF6UJGRlSWV7WZkOOqFEveY2HRNN BZgiyJ9fG8+Bh902i2nsoVUOu33jThGzWU31j9n/CWl/Di2RwU1Bm8E X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-ORIG-GUID: NlURBfKWRAOD4aK81-bkDf1Z-zq0Iinl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE4MDA2NiBTYWx0ZWRfX0wtE7pNfkUvv U3lq5qU05I1D0RLVBpaNTD5a/Fe11AlOBymSAXIQMqqYMQBow6Ju9lS84KPpaFF8UlfRnxzOITE EZrLKNwa7wBDMUwG7kC8GSvCy8zFfo9K+YldUS6GWr0M0myu+u0ab5yZ+3wuRyc0nxx5uTOHKqF +mWRiPh0/IrfrOlfiYPQTrvQ0E7X1OZuueCqJjzNHREe/v7TLG/CbqYJ3RnIee9VBduvpefjzBI ZUhFeumxF9EDenMS+fIU6XmwUXDAqxGm4HASZ4e5MiB/ZXfjinv4uuoLU3wK74g50vl3WpqorMb JMNsX0b4rS7nukQ1xgsLTxkUCYY1gWhMWv2Avp1/vQn8v2FtD0B4mlOZSEESA4RC9EcsYe9zxhr MWB7Tfun+ZFeLFACPNPQkLJ9KrMzWQ== X-Authority-Analysis: v=2.4 cv=NPHYOk6g c=1 sm=1 tr=0 ts=6943b703 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=zthVEJJq2wqy0CFkTqIA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: NlURBfKWRAOD4aK81-bkDf1Z-zq0Iinl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-18_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 clxscore=1015 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512180066 Introduce the `qcom,cpu-bound-components` boolean property for CoreSight components (TMC, Funnel, and Replicator). This property indicates that the component is physically located within a CPU cluster power domain. Such components share the power state of the cluster and may require special handling (e.g., cross-CPU register access) compared to system-wide components. Signed-off-by: Yuanfang Zhang --- .../devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml | 5 += ++++ .../devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml | 5 += ++++ Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml | 5 += ++++ 3 files changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-fu= nnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-fun= nel.yaml index b74db15e5f8af2226b817f6af5f533b1bfc74736..a4c7333e8359da9035a9fed999e= c99159e00a1d9 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.ya= ml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.ya= ml @@ -57,6 +57,11 @@ properties: power-domains: maxItems: 1 =20 + qcom,cpu-bound-components: + type: boolean + description: + Indicates whether the funnel is located physically within cpu cluste= r. + label: description: Description of a coresight device. diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-re= plicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic= -replicator.yaml index 17ea936b796fd42bb885e539201276a11e91028c..2c6e78f02ed84d95bb4366e4c4b= bd1b3953efa32 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicato= r.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicato= r.yaml @@ -67,6 +67,11 @@ properties: Indicates that the replicator will lose register context when AMBA c= lock is removed which is observed in some replicator designs. =20 + qcom,cpu-bound-components: + type: boolean + description: + Indicates whether the replicator is located physically within cpu cl= uster. + in-ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b= /Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml index 96dd5b5f771a39138df9adde0c9c9a6f5583d9da..8c4f2244a5c74dc865489230502= 5a4e6bccbce07 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml @@ -86,6 +86,11 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 maximum: 15 =20 + qcom,cpu-bound-components: + type: boolean + description: + indicates whether the TMC-ETF is located physically within cpu clust= er. + in-ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false --=20 2.34.1 From nobody Mon Feb 9 01:00:52 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 636E22ECD14 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b04e58d423sm2564824eec.6.2025.12.18.00.10.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 00:10:41 -0800 (PST) From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:42 -0800 Subject: [PATCH v2 02/12] coresight-funnel: Support CPU cluster funnel initialization Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-cpu_cluster_component_pm-v2-2-2335a6ae62a0@oss.qualcomm.com> References: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> In-Reply-To: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang , maulik.shah@oss.qualcomm.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766045439; l=9011; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=Fpp/5eQxMyG5rpvoNvxSYiDKJ7rnTCbi3mj2igPMxLU=; b=BavpAy9r7xKAgf/EbkDhLS/jCe/ZLPOLxE+sU7ckt40H3lLyYD/fFw77y3H7DyHloXrCfJK9C K6Bc7EKVjfMD71KSm5dlRQXRyjiuhr6czi4m3WboiAsLxZvj4T1Jz6e X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-ORIG-GUID: GBXv0OmMkXi1HevBM0vkLrg7hTW7VEPQ X-Proofpoint-GUID: GBXv0OmMkXi1HevBM0vkLrg7hTW7VEPQ X-Authority-Analysis: v=2.4 cv=f8JFxeyM c=1 sm=1 tr=0 ts=6943b704 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ntKk2pyKPOpeOXeRekoA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE4MDA2NiBTYWx0ZWRfX0uhvcLauzp3c 4RWRmYqYCefMdvM/cIdhBGmhEVBCvY/+7eNwWKT1bBOJIrHu7Be6O9GpKmCjB0uWWLqv1Y9tK/K J6YTQRLlll22gtQYPdklTKhEDUCefnae347rIwp8aKANnk5eHlJAyj+0P8P7IQDxfMlwDf+0mFV fHXaRH96OI7fmDTWepTPHErx4IcVvwgo2OF0MwIPh19/EMllBWtGAFeem0bKou5HyifEkpayjC0 Xwt/uYoeQAxqv3pTu7jVAAY1q7uSaiZHMWwt3eKgyfl1vCBeKGgyg7rXWiRb7PRPcy1FKzGAtIf FoDtSgUj1/sh5YK5pxdqzkSP32ObY3MHwpb+geDtMo2I8hHO7guHmmDe+bAv/9IFRsbLsNUUCU8 irtHCZG/i3fshLUnpJMItJRp+x6bZg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-18_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 clxscore=1015 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512180066 Funnels associated with CPU clusters reside in the cluster's power domain. Unlike dynamic funnels (which are typically system-wide), these per-cluster funnels are only accessible when the cluster is powered on. Standard runtime PM may not suffice to wake up a cluster from low-power states, making direct register access unreliable. Enhance the funnel driver to support these per-cluster devices: 1. Safe Initialization: - Identify CPU cluster funnels via "qcom,cpu-bound-components". - Use smp_call_function_single() to perform hardware initialization (claim tag clearing) on a CPU within the cluster. - Refactor the probe flow to encapsulate device registration in funnel_add_coresight_dev(). 2. Cross-CPU Enablement: - Update funnel_enable() to use smp_call_function_single() when enabling the hardware on a cluster-bound funnel. 3. Debug Interface Support: - Update funnel_ctrl_show() to safely read the control register via cross-CPU calls when necessary. This ensures that funnel operations remain safe and functional even when the associated CPU cluster is in aggressive low-power states. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-funnel.c | 183 ++++++++++++++++++++-= ---- 1 file changed, 152 insertions(+), 31 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtra= cing/coresight/coresight-funnel.c index 3b248e54471a38f501777fe162fea850d1c851b3..a1264df84ab4c625c63dfbb9b77= 10b983a10c6b4 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,7 @@ DEFINE_CORESIGHT_DEVLIST(funnel_devs, "funnel"); * @csdev: component vitals needed by the framework. * @priority: port selection order. * @spinlock: serialize enable/disable operations. + * @supported_cpus: Represent the CPUs related to this funnel. */ struct funnel_drvdata { void __iomem *base; @@ -48,6 +50,13 @@ struct funnel_drvdata { struct coresight_device *csdev; unsigned long priority; raw_spinlock_t spinlock; + struct cpumask *supported_cpus; +}; + +struct funnel_smp_arg { + struct funnel_drvdata *drvdata; + int port; + int rc; }; =20 static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int po= rt) @@ -76,6 +85,33 @@ static int dynamic_funnel_enable_hw(struct funnel_drvdat= a *drvdata, int port) return rc; } =20 +static void funnel_enable_hw_smp_call(void *info) +{ + struct funnel_smp_arg *arg =3D info; + + arg->rc =3D dynamic_funnel_enable_hw(arg->drvdata, arg->port); +} + +static int funnel_enable_hw(struct funnel_drvdata *drvdata, int port) +{ + int cpu, ret; + struct funnel_smp_arg arg =3D { 0 }; + + if (!drvdata->supported_cpus) + return dynamic_funnel_enable_hw(drvdata, port); + + arg.drvdata =3D drvdata; + arg.port =3D port; + + for_each_cpu(cpu, drvdata->supported_cpus) { + ret =3D smp_call_function_single(cpu, + funnel_enable_hw_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + return ret; +} + static int funnel_enable(struct coresight_device *csdev, struct coresight_connection *in, struct coresight_connection *out) @@ -86,19 +122,24 @@ static int funnel_enable(struct coresight_device *csde= v, bool first_enable =3D false; =20 raw_spin_lock_irqsave(&drvdata->spinlock, flags); - if (in->dest_refcnt =3D=3D 0) { - if (drvdata->base) - rc =3D dynamic_funnel_enable_hw(drvdata, in->dest_port); - if (!rc) - first_enable =3D true; - } - if (!rc) + + if (in->dest_refcnt =3D=3D 0) + first_enable =3D true; + else in->dest_refcnt++; + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 - if (first_enable) - dev_dbg(&csdev->dev, "FUNNEL inport %d enabled\n", - in->dest_port); + if (first_enable) { + if (drvdata->base) + rc =3D funnel_enable_hw(drvdata, in->dest_port); + if (!rc) { + in->dest_refcnt++; + dev_dbg(&csdev->dev, "FUNNEL inport %d enabled\n", + in->dest_port); + } + } + return rc; } =20 @@ -188,15 +229,39 @@ static u32 get_funnel_ctrl_hw(struct funnel_drvdata *= drvdata) return functl; } =20 +static void get_funnel_ctrl_smp_call(void *info) +{ + struct funnel_smp_arg *arg =3D info; + + arg->rc =3D get_funnel_ctrl_hw(arg->drvdata); +} + static ssize_t funnel_ctrl_show(struct device *dev, struct device_attribute *attr, char *buf) { u32 val; + int cpu, ret; struct funnel_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + struct funnel_smp_arg arg =3D { 0 }; =20 pm_runtime_get_sync(dev->parent); - - val =3D get_funnel_ctrl_hw(drvdata); + if (!drvdata->supported_cpus) { + val =3D get_funnel_ctrl_hw(drvdata); + } else { + arg.drvdata =3D drvdata; + for_each_cpu(cpu, drvdata->supported_cpus) { + ret =3D smp_call_function_single(cpu, + get_funnel_ctrl_smp_call, &arg, 1); + if (!ret) + break; + } + if (!ret) { + val =3D arg.rc; + } else { + pm_runtime_put(dev->parent); + return ret; + } + } =20 pm_runtime_put(dev->parent); =20 @@ -211,22 +276,68 @@ static struct attribute *coresight_funnel_attrs[] =3D= { }; ATTRIBUTE_GROUPS(coresight_funnel); =20 +static void funnel_clear_self_claim_tag(struct funnel_drvdata *drvdata) +{ + struct csdev_access access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + + coresight_clear_self_claim_tag(&access); +} + +static void funnel_init_on_cpu(void *info) +{ + struct funnel_drvdata *drvdata =3D info; + + funnel_clear_self_claim_tag(drvdata); +} + +static int funnel_add_coresight_dev(struct device *dev) +{ + struct coresight_desc desc =3D { 0 }; + struct funnel_drvdata *drvdata =3D dev_get_drvdata(dev); + + if (drvdata->base) { + desc.groups =3D coresight_funnel_groups; + desc.access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + } + + desc.name =3D coresight_alloc_device_name(&funnel_devs, dev); + if (!desc.name) + return -ENOMEM; + + desc.type =3D CORESIGHT_DEV_TYPE_LINK; + desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_MERG; + desc.ops =3D &funnel_cs_ops; + desc.pdata =3D dev->platform_data; + desc.dev =3D dev; + + drvdata->csdev =3D coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + return 0; +} + +static struct cpumask *funnel_get_supported_cpus(struct device *dev) +{ + struct generic_pm_domain *pd; + + pd =3D pd_to_genpd(dev->pm_domain); + if (pd) + return pd->cpus; + + return NULL; +} + static int funnel_probe(struct device *dev, struct resource *res) { void __iomem *base; struct coresight_platform_data *pdata =3D NULL; struct funnel_drvdata *drvdata; - struct coresight_desc desc =3D { 0 }; - int ret; + int cpu, ret; =20 if (is_of_node(dev_fwnode(dev)) && of_device_is_compatible(dev->of_node, "arm,coresight-funnel")) dev_warn_once(dev, "Uses OBSOLETE CoreSight funnel binding\n"); =20 - desc.name =3D coresight_alloc_device_name(&funnel_devs, dev); - if (!desc.name) - return -ENOMEM; - drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; @@ -244,9 +355,6 @@ static int funnel_probe(struct device *dev, struct reso= urce *res) if (IS_ERR(base)) return PTR_ERR(base); drvdata->base =3D base; - desc.groups =3D coresight_funnel_groups; - desc.access =3D CSDEV_ACCESS_IOMEM(base); - coresight_clear_self_claim_tag(&desc.access); } =20 dev_set_drvdata(dev, drvdata); @@ -258,23 +366,36 @@ static int funnel_probe(struct device *dev, struct re= source *res) dev->platform_data =3D pdata; =20 raw_spin_lock_init(&drvdata->spinlock); - desc.type =3D CORESIGHT_DEV_TYPE_LINK; - desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_MERG; - desc.ops =3D &funnel_cs_ops; - desc.pdata =3D pdata; - desc.dev =3D dev; - drvdata->csdev =3D coresight_register(&desc); - if (IS_ERR(drvdata->csdev)) - return PTR_ERR(drvdata->csdev); =20 - return 0; + if (fwnode_property_present(dev_fwnode(dev), "qcom,cpu-bound-components")= ) { + drvdata->supported_cpus =3D funnel_get_supported_cpus(dev); + if (!drvdata->supported_cpus) + return -EINVAL; + + cpus_read_lock(); + for_each_cpu(cpu, drvdata->supported_cpus) { + ret =3D smp_call_function_single(cpu, + funnel_init_on_cpu, drvdata, 1); + if (!ret) + break; + } + cpus_read_unlock(); + + if (ret) + return 0; + } else if (res) { + funnel_clear_self_claim_tag(drvdata); + } + + return funnel_add_coresight_dev(dev); } =20 static int funnel_remove(struct device *dev) { struct funnel_drvdata *drvdata =3D dev_get_drvdata(dev); =20 - coresight_unregister(drvdata->csdev); + if (drvdata->csdev) + coresight_unregister(drvdata->csdev); =20 return 0; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b04e58d423sm2564824eec.6.2025.12.18.00.10.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 00:10:42 -0800 (PST) From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:43 -0800 Subject: [PATCH v2 03/12] coresight-funnel: Defer probe when associated CPUs are offline Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-cpu_cluster_component_pm-v2-3-2335a6ae62a0@oss.qualcomm.com> References: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> In-Reply-To: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang , maulik.shah@oss.qualcomm.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766045439; l=4434; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=WwWv1dVaZYPvnR6R1Ei7R4iTlI2WTlIv5BffkfyWev4=; b=dQbvHI/2v1JuiMMRpKrCwOIQtDDEOZwHfzA72YQzaiRyUwGSbgCOeeOfPl3bFQ0Jul2DlNY4K ht2uOJpJoqdDwGuOsdrhbjOl8X4rA+yM6MB/IqMkHYK5eN8/KFdZPt5 X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-ORIG-GUID: SJG7XIIT0vSwV4CIHzeQj2c6FcnsA4yD X-Proofpoint-GUID: SJG7XIIT0vSwV4CIHzeQj2c6FcnsA4yD X-Authority-Analysis: v=2.4 cv=f8JFxeyM c=1 sm=1 tr=0 ts=6943b704 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=B8lwgTuz66jIMM7eRW8A:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE4MDA2NiBTYWx0ZWRfXxDfBoSdeByo9 4xnv/QquqBr9Up4mGTjxYrJ9CtAERuGm9L8HOPFvo8cCaKbH5Y/lou1MrTto5KDgXganDWuzM// 9fcLXQKeVpVhtDeYhFBvLEdHOPO7iEvfo4iO/k/2/Ezy1syoDmsxsG9KuQCGG+MPjyP1YWvTgr0 IqEhU+qF5ksK1uIt1tJ5ahRxy1ywKKW1mEIK9ezay91LddCMJ9BkTyFHG7GTSsbhQleYjnDMkuK YBIL8/JHCIPPFthi72eOp4XEjd9uhgV/YQB8/JDX/wuw4b3FlTkJ4dDMJ1MjOIrjX3EDyeju2Ia pjTfhmN3RzZSIbGe6RgvQ/rqVBK+ugTkjbwuuHr/0tm6i1m9fvtupxW6EZCRq60zx0e5Eabo6z5 FwIRWnAxBdl019CxCcyZU++eiT2wvg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-18_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 clxscore=1015 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512180066 Per-cluster funnels rely on the associated CPU cluster being online to securely access registers during initialization. If all CPUs in the cluster are offline during probe, these operations fail. Support deferred initialization for these devices: 1. Track funnels that fail to probe due to offline CPUs in a global list. 2. Register a CPU hotplug notifier (funnel_online_cpu) to detect when a relevant CPU comes online. 3. Upon CPU online, retry the hardware initialization and registration with the CoreSight framework. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-funnel.c | 62 ++++++++++++++++++++++= +--- 1 file changed, 57 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtra= cing/coresight/coresight-funnel.c index a1264df84ab4c625c63dfbb9b7710b983a10c6b4..5d114ce1109f4f9a8b108110bda= e258f216881d8 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -32,6 +32,9 @@ #define FUNNEL_ENSx_MASK 0xff =20 DEFINE_CORESIGHT_DEVLIST(funnel_devs, "funnel"); +static LIST_HEAD(funnel_delay_probe); +static enum cpuhp_state hp_online; +static DEFINE_SPINLOCK(delay_lock); =20 /** * struct funnel_drvdata - specifics associated to a funnel component @@ -42,6 +45,8 @@ DEFINE_CORESIGHT_DEVLIST(funnel_devs, "funnel"); * @priority: port selection order. * @spinlock: serialize enable/disable operations. * @supported_cpus: Represent the CPUs related to this funnel. + * @dev: pointer to the device associated with this funnel. + * @link: list node for adding this funnel to the delayed probe list. */ struct funnel_drvdata { void __iomem *base; @@ -51,6 +56,8 @@ struct funnel_drvdata { unsigned long priority; raw_spinlock_t spinlock; struct cpumask *supported_cpus; + struct device *dev; + struct list_head link; }; =20 struct funnel_smp_arg { @@ -371,7 +378,7 @@ static int funnel_probe(struct device *dev, struct reso= urce *res) drvdata->supported_cpus =3D funnel_get_supported_cpus(dev); if (!drvdata->supported_cpus) return -EINVAL; - + drvdata->dev =3D dev; cpus_read_lock(); for_each_cpu(cpu, drvdata->supported_cpus) { ret =3D smp_call_function_single(cpu, @@ -379,10 +386,15 @@ static int funnel_probe(struct device *dev, struct re= source *res) if (!ret) break; } - cpus_read_unlock(); =20 - if (ret) + if (ret) { + scoped_guard(spinlock, &delay_lock) + list_add(&drvdata->link, &funnel_delay_probe); + cpus_read_unlock(); return 0; + } + + cpus_read_unlock(); } else if (res) { funnel_clear_self_claim_tag(drvdata); } @@ -394,9 +406,12 @@ static int funnel_remove(struct device *dev) { struct funnel_drvdata *drvdata =3D dev_get_drvdata(dev); =20 - if (drvdata->csdev) + if (drvdata->csdev) { coresight_unregister(drvdata->csdev); - + } else { + scoped_guard(spinlock, &delay_lock) + list_del(&drvdata->link); + } return 0; } =20 @@ -533,8 +548,41 @@ static struct amba_driver dynamic_funnel_driver =3D { .id_table =3D dynamic_funnel_ids, }; =20 +static int funnel_online_cpu(unsigned int cpu) +{ + struct funnel_drvdata *drvdata, *tmp; + int ret; + + list_for_each_entry_safe(drvdata, tmp, &funnel_delay_probe, link) { + if (cpumask_test_cpu(cpu, drvdata->supported_cpus)) { + scoped_guard(spinlock, &delay_lock) + list_del(&drvdata->link); + + ret =3D pm_runtime_resume_and_get(drvdata->dev); + if (ret < 0) + return 0; + + funnel_clear_self_claim_tag(drvdata); + funnel_add_coresight_dev(drvdata->dev); + pm_runtime_put(drvdata->dev); + } + } + return 0; +} + static int __init funnel_init(void) { + int ret; + + ret =3D cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, + "arm/coresight-funnel:online", + funnel_online_cpu, NULL); + + if (ret > 0) + hp_online =3D ret; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b04e58d423sm2564824eec.6.2025.12.18.00.10.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 00:10:43 -0800 (PST) From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:44 -0800 Subject: [PATCH v2 04/12] coresight-replicator: Support CPU cluster replicator initialization Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-cpu_cluster_component_pm-v2-4-2335a6ae62a0@oss.qualcomm.com> References: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> In-Reply-To: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang , maulik.shah@oss.qualcomm.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766045439; l=9933; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=zad/+HKvgqcPRsu64plFTKJAgpaj4lRh7Ypv4wC8mi4=; b=OxEMcFDqCRURYR2alE9C+qytbvWhgSWbsRUFrDfHwwuMaF1z3EtogAhvMR2S9BtRQMmz0t2Hd JGRF9VSAJPVAGqkrNLKWa2i3wDL6eSSDWffrwWGD1JSmqtVJS3Igms8 X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-ORIG-GUID: wIjJuoCPi3-dG3EQoIZKm0vU7-_m6dSP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE4MDA2NiBTYWx0ZWRfX0u4RS9DNvB7b s9TGmPetvhbl0Bm6nQ5R2Gcvs9dVkLpC30QEC+aDJYB0jwd+ghltgowLwDgOj0gYluXDV9Yof5Y m7kMgHWe85Vhc56qh/WN99A6F3ah3F4lbctOPS5pu8EKSsY1kWvsKfDn860Yc6GfdoD5bBe6kDV 4FxAH1ytP28UTEIWdcba+CPvh9xyLoxGbDErL1IQ0xnPI7agg4fMAIYP4eFUcxxtgksirxQnDm7 wBRvAMP3fuFzrXLXyukwxR/qssouel6zqBFbvtZxDzhC+cI7gRkYqqouKtcHglzjXzR2OsrnfCB mvVF4m5WyfDXl020HijEk7VncadA7n8foSNZSnH1McMKPO//mWK+gvDiAuLkVW2yPYG6ITTvotS 5gKKyrfoqbLO3ssh4lHu6YyAmT7irg== X-Authority-Analysis: v=2.4 cv=NPHYOk6g c=1 sm=1 tr=0 ts=6943b706 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=iEGaxejzB682sgr3lzYA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-GUID: wIjJuoCPi3-dG3EQoIZKm0vU7-_m6dSP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-18_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 clxscore=1015 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512180066 Replicators associated with CPU clusters reside in the cluster's power domain. Unlike system-wide replicators, their registers are only accessible when the cluster is powered on. Standard runtime PM may not suffice to wake up a cluster from low-power states, making direct register access unreliable during initialization or operation. Enhance the replicator driver to support these per-cluster devices: 1. Safe Initialization: - Identify per-cluster replicators via device properties. - Use smp_call_function_single() to perform hardware initialization (reset and claim tag clearing) on a CPU within the cluster. - Refactor the probe flow to encapsulate device registration in replicator_add_coresight_dev(). 2. Cross-CPU Enablement: - Update replicator_enable() to use smp_call_function_single() when enabling the hardware on a cluster-bound replicator. 3. Claim/Disclaim Handling: - Introduce replicator_claim/disclaim_device_unlocked() to manage device access safely before full framework registration. This ensures that replicator operations remain robust even when the associated CPU cluster is in low-power states, while maintaining compatibility with existing system-level replicators. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-replicator.c | 200 +++++++++++++++++= ---- 1 file changed, 167 insertions(+), 33 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/h= wtracing/coresight/coresight-replicator.c index e6472658235dc479cec91ac18f3737f76f8c74f0..c11da452559c73af6709b39d03b= 646cb4779736f 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -35,6 +36,7 @@ DEFINE_CORESIGHT_DEVLIST(replicator_devs, "replicator"); * @csdev: component vitals needed by the framework * @spinlock: serialize enable/disable operations. * @check_idfilter_val: check if the context is lost upon clock removal. + * @supported_cpus: Represent the CPUs related to this funnel. */ struct replicator_drvdata { void __iomem *base; @@ -43,18 +45,61 @@ struct replicator_drvdata { struct coresight_device *csdev; raw_spinlock_t spinlock; bool check_idfilter_val; + struct cpumask *supported_cpus; }; =20 -static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) +struct replicator_smp_arg { + struct replicator_drvdata *drvdata; + int outport; + int rc; +}; + +static void replicator_clear_self_claim_tag(struct replicator_drvdata *drv= data) +{ + struct csdev_access access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + + coresight_clear_self_claim_tag(&access); +} + +static int replicator_claim_device_unlocked(struct replicator_drvdata *drv= data) +{ + struct coresight_device *csdev =3D drvdata->csdev; + struct csdev_access access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + u32 claim_tag; + + if (csdev) + return coresight_claim_device_unlocked(csdev); + + writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, drvdata->base + CORESIGHT_CLA= IMSET); + + claim_tag =3D readl_relaxed(drvdata->base + CORESIGHT_CLAIMCLR); + if (claim_tag !=3D CORESIGHT_CLAIM_SELF_HOSTED) { + coresight_clear_self_claim_tag_unlocked(&access); + return -EBUSY; + } + + return 0; +} + +static void replicator_disclaim_device_unlocked(struct replicator_drvdata = *drvdata) { struct coresight_device *csdev =3D drvdata->csdev; + struct csdev_access access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + + if (csdev) + return coresight_disclaim_device_unlocked(csdev); =20 + coresight_clear_self_claim_tag_unlocked(&access); +} + +static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) +{ CS_UNLOCK(drvdata->base); =20 - if (!coresight_claim_device_unlocked(csdev)) { + if (!replicator_claim_device_unlocked(drvdata)) { writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0); writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1); - coresight_disclaim_device_unlocked(csdev); + replicator_disclaim_device_unlocked(drvdata); } =20 CS_LOCK(drvdata->base); @@ -116,6 +161,34 @@ static int dynamic_replicator_enable(struct replicator= _drvdata *drvdata, return rc; } =20 +static void replicator_enable_hw_smp_call(void *info) +{ + struct replicator_smp_arg *arg =3D info; + + arg->rc =3D dynamic_replicator_enable(arg->drvdata, 0, arg->outport); +} + +static int replicator_enable_hw(struct replicator_drvdata *drvdata, + int inport, int outport) +{ + int cpu, ret; + struct replicator_smp_arg arg =3D { 0 }; + + if (!drvdata->supported_cpus) + return dynamic_replicator_enable(drvdata, 0, outport); + + arg.drvdata =3D drvdata; + arg.outport =3D outport; + + for_each_cpu(cpu, drvdata->supported_cpus) { + ret =3D smp_call_function_single(cpu, replicator_enable_hw_smp_call, &ar= g, 1); + if (!ret) + return arg.rc; + } + + return ret; +} + static int replicator_enable(struct coresight_device *csdev, struct coresight_connection *in, struct coresight_connection *out) @@ -126,19 +199,24 @@ static int replicator_enable(struct coresight_device = *csdev, bool first_enable =3D false; =20 raw_spin_lock_irqsave(&drvdata->spinlock, flags); - if (out->src_refcnt =3D=3D 0) { - if (drvdata->base) - rc =3D dynamic_replicator_enable(drvdata, in->dest_port, - out->src_port); - if (!rc) - first_enable =3D true; - } - if (!rc) + + if (out->src_refcnt =3D=3D 0) + first_enable =3D true; + else out->src_refcnt++; raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 - if (first_enable) - dev_dbg(&csdev->dev, "REPLICATOR enabled\n"); + if (first_enable) { + if (drvdata->base) + rc =3D replicator_enable_hw(drvdata, in->dest_port, + out->src_port); + if (!rc) { + out->src_refcnt++; + dev_dbg(&csdev->dev, "REPLICATOR enabled\n"); + return rc; + } + } + return rc; } =20 @@ -217,23 +295,69 @@ static const struct attribute_group *replicator_group= s[] =3D { NULL, }; =20 +static int replicator_add_coresight_dev(struct device *dev) +{ + struct coresight_desc desc =3D { 0 }; + struct replicator_drvdata *drvdata =3D dev_get_drvdata(dev); + + if (drvdata->base) { + desc.groups =3D replicator_groups; + desc.access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + } + + desc.name =3D coresight_alloc_device_name(&replicator_devs, dev); + if (!desc.name) + return -ENOMEM; + + desc.type =3D CORESIGHT_DEV_TYPE_LINK; + desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_SPLIT; + desc.ops =3D &replicator_cs_ops; + desc.pdata =3D dev->platform_data; + desc.dev =3D dev; + + drvdata->csdev =3D coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + return 0; +} + +static void replicator_init_hw(struct replicator_drvdata *drvdata) +{ + replicator_clear_self_claim_tag(drvdata); + replicator_reset(drvdata); +} + +static void replicator_init_on_cpu(void *info) +{ + struct replicator_drvdata *drvdata =3D info; + + replicator_init_hw(drvdata); +} + +static struct cpumask *replicator_get_supported_cpus(struct device *dev) +{ + struct generic_pm_domain *pd; + + pd =3D pd_to_genpd(dev->pm_domain); + if (pd) + return pd->cpus; + + return NULL; +} + static int replicator_probe(struct device *dev, struct resource *res) { struct coresight_platform_data *pdata =3D NULL; struct replicator_drvdata *drvdata; - struct coresight_desc desc =3D { 0 }; void __iomem *base; - int ret; + int cpu, ret; =20 if (is_of_node(dev_fwnode(dev)) && of_device_is_compatible(dev->of_node, "arm,coresight-replicator")) dev_warn_once(dev, "Uses OBSOLETE CoreSight replicator binding\n"); =20 - desc.name =3D coresight_alloc_device_name(&replicator_devs, dev); - if (!desc.name) - return -ENOMEM; - drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; @@ -251,9 +375,6 @@ static int replicator_probe(struct device *dev, struct = resource *res) if (IS_ERR(base)) return PTR_ERR(base); drvdata->base =3D base; - desc.groups =3D replicator_groups; - desc.access =3D CSDEV_ACCESS_IOMEM(base); - coresight_clear_self_claim_tag(&desc.access); } =20 if (fwnode_property_present(dev_fwnode(dev), @@ -268,25 +389,38 @@ static int replicator_probe(struct device *dev, struc= t resource *res) dev->platform_data =3D pdata; =20 raw_spin_lock_init(&drvdata->spinlock); - desc.type =3D CORESIGHT_DEV_TYPE_LINK; - desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_SPLIT; - desc.ops =3D &replicator_cs_ops; - desc.pdata =3D dev->platform_data; - desc.dev =3D dev; =20 - drvdata->csdev =3D coresight_register(&desc); - if (IS_ERR(drvdata->csdev)) - return PTR_ERR(drvdata->csdev); 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If all CPUs in the cluster are offline during probe, these operations fail. Support deferred initialization for these devices: 1. Track replicators that fail to probe due to offline CPUs in a global list. 2. Register a CPU hotplug notifier (`replicator_online_cpu`) to detect when a relevant CPU comes online. 3. Upon CPU online, retry the hardware initialization and registration with the CoreSight framework. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-replicator.c | 65 ++++++++++++++++++= ++-- 1 file changed, 61 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/h= wtracing/coresight/coresight-replicator.c index c11da452559c73af6709b39d03b646cb4779736f..f8d13894098f1e414fb0da8d6ee= b1da4f0d55a8c 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -26,6 +26,9 @@ #define REPLICATOR_IDFILTER1 0x004 =20 DEFINE_CORESIGHT_DEVLIST(replicator_devs, "replicator"); +static LIST_HEAD(replicator_delay_probe); +static enum cpuhp_state hp_online; +static DEFINE_SPINLOCK(delay_lock); =20 /** * struct replicator_drvdata - specifics associated to a replicator compon= ent @@ -37,6 +40,8 @@ DEFINE_CORESIGHT_DEVLIST(replicator_devs, "replicator"); * @spinlock: serialize enable/disable operations. * @check_idfilter_val: check if the context is lost upon clock removal. * @supported_cpus: Represent the CPUs related to this funnel. + * @dev: pointer to the device associated with this replicator. + * @link: link to the delay_probed list. */ struct replicator_drvdata { void __iomem *base; @@ -46,6 +51,8 @@ struct replicator_drvdata { raw_spinlock_t spinlock; bool check_idfilter_val; struct cpumask *supported_cpus; + struct device *dev; + struct list_head link; }; =20 struct replicator_smp_arg { @@ -394,7 +401,7 @@ static int replicator_probe(struct device *dev, struct = resource *res) drvdata->supported_cpus =3D replicator_get_supported_cpus(dev); if (!drvdata->supported_cpus) return -EINVAL; - + drvdata->dev =3D dev; cpus_read_lock(); for_each_cpu(cpu, drvdata->supported_cpus) { ret =3D smp_call_function_single(cpu, @@ -402,10 +409,15 @@ static int replicator_probe(struct device *dev, struc= t resource *res) if (!ret) break; } - cpus_read_unlock(); =20 - if (ret) + if (ret) { + scoped_guard(spinlock, &delay_lock) + list_add(&drvdata->link, &replicator_delay_probe); + cpus_read_unlock(); return 0; + } + + cpus_read_unlock(); } else if (res) { replicator_init_hw(drvdata); } @@ -419,8 +431,13 @@ static int replicator_remove(struct device *dev) { struct replicator_drvdata *drvdata =3D dev_get_drvdata(dev); =20 - if (drvdata->csdev) + if (drvdata->csdev) { coresight_unregister(drvdata->csdev); + } else { + scoped_guard(spinlock, &delay_lock) + list_del(&drvdata->link); + } + return 0; } =20 @@ -552,8 +569,44 @@ static struct amba_driver dynamic_replicator_driver = =3D { .id_table =3D dynamic_replicator_ids, }; =20 +static int replicator_online_cpu(unsigned int cpu) +{ + struct replicator_drvdata *drvdata, *tmp; + int ret; + + spin_lock(&delay_lock); + list_for_each_entry_safe(drvdata, tmp, &replicator_delay_probe, link) { + if (cpumask_test_cpu(cpu, drvdata->supported_cpus)) { + list_del(&drvdata->link); + spin_unlock(&delay_lock); + ret =3D pm_runtime_resume_and_get(drvdata->dev); + if (ret < 0) + return 0; + + replicator_clear_self_claim_tag(drvdata); + replicator_reset(drvdata); + replicator_add_coresight_dev(drvdata->dev); + pm_runtime_put(drvdata->dev); + spin_lock(&delay_lock); + } + } + spin_unlock(&delay_lock); + return 0; +} + static int __init replicator_init(void) { + int ret; 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However, replicators associated with specific CPU clusters share the cluster's power domain and require access via a CPU within that domain. Replace the standard `coresight_simple_reg*` accessors with custom handlers (`coresight_replicator_reg*`) to support these devices: - For cluster-bound replicators (indicated by `supported_cpus`), use `smp_call_function_single()` to read registers on an associated CPU. - For standard replicators, retain the direct access behavior. This ensures correct operation for per-cluster replicators while maintaining compatibility for existing system-level devices. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-replicator.c | 61 ++++++++++++++++++= +++- 1 file changed, 59 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/h= wtracing/coresight/coresight-replicator.c index f8d13894098f1e414fb0da8d6eeb1da4f0d55a8c..a9f22d0e15de21aa06c8d1e193e= 5db06091efd75 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -58,6 +58,7 @@ struct replicator_drvdata { struct replicator_smp_arg { struct replicator_drvdata *drvdata; int outport; + u32 offset; int rc; }; =20 @@ -286,9 +287,65 @@ static const struct coresight_ops replicator_cs_ops = =3D { .link_ops =3D &replicator_link_ops, }; =20 +static void replicator_read_register_smp_call(void *info) +{ + struct replicator_smp_arg *arg =3D info; + + arg->rc =3D readl_relaxed(arg->drvdata->base + arg->offset); +} + +static ssize_t coresight_replicator_reg32_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct replicator_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + struct cs_off_attribute *cs_attr =3D container_of(attr, struct cs_off_att= ribute, attr); + unsigned long flags; + struct replicator_smp_arg arg =3D { 0 }; + u32 val; + int ret, cpu; + + pm_runtime_get_sync(dev->parent); + + if (!drvdata->supported_cpus) { + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + val =3D readl_relaxed(drvdata->base + cs_attr->off); + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + + } else { + arg.drvdata =3D drvdata; + arg.offset =3D cs_attr->off; + for_each_cpu(cpu, drvdata->supported_cpus) { + ret =3D smp_call_function_single(cpu, + replicator_read_register_smp_call, + &arg, 1); + if (!ret) + break; + } + if (!ret) { + val =3D arg.rc; + } else { + pm_runtime_put_sync(dev->parent); + return ret; + } + } + + pm_runtime_put_sync(dev->parent); + + return sysfs_emit(buf, "0x%x\n", val); +} + +#define coresight_replicator_reg32(name, offset) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_replicator_reg32_show, NULL), \ + offset \ + } \ + })[0].attr.attr) + static struct attribute *replicator_mgmt_attrs[] =3D { - coresight_simple_reg32(idfilter0, REPLICATOR_IDFILTER0), - coresight_simple_reg32(idfilter1, REPLICATOR_IDFILTER1), + coresight_replicator_reg32(idfilter0, REPLICATOR_IDFILTER0), + coresight_replicator_reg32(idfilter1, REPLICATOR_IDFILTER1), NULL, }; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b04e58d423sm2564824eec.6.2025.12.18.00.10.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 00:10:48 -0800 (PST) From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:47 -0800 Subject: [PATCH v2 07/12] coresight-tmc: Support probe and initialization for CPU cluster TMCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-cpu_cluster_component_pm-v2-7-2335a6ae62a0@oss.qualcomm.com> References: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> In-Reply-To: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang , maulik.shah@oss.qualcomm.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766045439; l=10021; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=VBlkATc/lcj6oh/+7N99ClnqOVJCbTvJk8ZfbtYCMaA=; b=jPtCN8o60f4IkWzznTnCyUC6rslRS9R4ZDA/TzyqRs8sWyR9Yt8N50nKiAJy8EX9fQoI6jH3U XSqF9/R2s1CA6VXJXu1DlV28z856e2Q1l3xIErAGKWsTiEJ9ABM+3rh X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE4MDA2NiBTYWx0ZWRfX/aYem23IyMhD 0Pjq+bdO++cXxtOLXSjP+AVlC5NAzxYILKpe9EeZJ4KH/zO+CEFul0w3tGxX9sp0Lna9ifsMoDP +jmbK15rqT3DJemNE+d2TbECFDEbaeoJVvVj7IVeixmGGMrtl51orlePLGS2bKZOcpMfV+PFKCb 86JagRitQfslKMnheNMr5cYmoHDad1NUahBGaPciRBgCx7JQ6K8VyFOC+ONs8aO7TypuD4pSk5W nmHDUZFsxtGSUudjBpE3Qj9uYk9BMW0ADS60A4wEXDTmWjAEonGptOQpzMWJxVn/9yNQitbODTk U0hdr0dNUUf/0QPAu1qNp5IwtMOffYn9WLD3vShS5bgZxqN/Zeo4izRqLrARPlVNolGjvAVARaM XkiEqFALFCERQZ+Kk1Lou/0UQjnzZQ== X-Proofpoint-GUID: -gm8fN9-CybYo107Mmw8OS26kYQNWEcB X-Proofpoint-ORIG-GUID: -gm8fN9-CybYo107Mmw8OS26kYQNWEcB X-Authority-Analysis: v=2.4 cv=Zpjg6t7G c=1 sm=1 tr=0 ts=6943b70b cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=AsHEykryqctiG1ll_fEA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-18_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 clxscore=1015 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512180066 TMC instances associated with CPU clusters reside in the cluster's power domain. Unlike system-level TMCs, their registers are only accessible when the cluster is powered on. Standard runtime PM may not suffice to wake up a cluster from low-power states during probe, making direct register access unreliable. Refactor the probe sequence to handle these per-cluster devices safely: 1. Identify per-cluster TMCs using the "qcom,cpu-bound-components" property. 2. For such devices, use `smp_call_function_single()` to perform hardware initialization (`tmc_init_hw_config`) on a CPU within the cluster. This ensures the domain is powered during access. 3. Factor out the device registration logic into `tmc_add_coresight_dev()`. This allows common registration code to be shared between the standard probe path and the deferred probe path (used when the associated CPUs are initially offline). This change ensures reliable initialization for per-cluster TMCs while maintaining backward compatibility for standard system-level TMCs. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tmc-core.c | 195 +++++++++++++++----= ---- drivers/hwtracing/coresight/coresight-tmc.h | 6 + 2 files changed, 132 insertions(+), 69 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 36599c431be6203e871fdcb8de569cc6701c52bb..0e1b5956398d3cefdd938a8a840= 4076eb4850b44 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -769,56 +770,14 @@ static void register_crash_dev_interface(struct tmc_d= rvdata *drvdata, "Valid crash tracedata found\n"); } =20 -static int __tmc_probe(struct device *dev, struct resource *res) +static int tmc_add_coresight_dev(struct device *dev) { - int ret =3D 0; - u32 devid; - void __iomem *base; - struct coresight_platform_data *pdata =3D NULL; - struct tmc_drvdata *drvdata; + struct tmc_drvdata *drvdata =3D dev_get_drvdata(dev); struct coresight_desc desc =3D { 0 }; struct coresight_dev_list *dev_list =3D NULL; + int ret =3D 0; =20 - drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); - if (!drvdata) - return -ENOMEM; - - dev_set_drvdata(dev, drvdata); - - ret =3D coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk); - if (ret) - return ret; - - ret =3D -ENOMEM; - - /* Validity for the resource is already checked by the AMBA core */ - base =3D devm_ioremap_resource(dev, res); - if (IS_ERR(base)) { - ret =3D PTR_ERR(base); - goto out; - } - - drvdata->base =3D base; - desc.access =3D CSDEV_ACCESS_IOMEM(base); - - raw_spin_lock_init(&drvdata->spinlock); - - devid =3D readl_relaxed(drvdata->base + CORESIGHT_DEVID); - drvdata->config_type =3D BMVAL(devid, 6, 7); - drvdata->memwidth =3D tmc_get_memwidth(devid); - /* This device is not associated with a session */ - drvdata->pid =3D -1; - drvdata->etr_mode =3D ETR_MODE_AUTO; - - if (drvdata->config_type =3D=3D TMC_CONFIG_TYPE_ETR) { - drvdata->size =3D tmc_etr_get_default_buffer_size(dev); - drvdata->max_burst_size =3D tmc_etr_get_max_burst_size(dev); - } else { - drvdata->size =3D readl_relaxed(drvdata->base + TMC_RSZ) * 4; - } - - tmc_get_reserved_region(dev); - + desc.access =3D CSDEV_ACCESS_IOMEM(drvdata->base); desc.dev =3D dev; =20 switch (drvdata->config_type) { @@ -834,9 +793,9 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) desc.type =3D CORESIGHT_DEV_TYPE_SINK; desc.subtype.sink_subtype =3D CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM; desc.ops =3D &tmc_etr_cs_ops; - ret =3D tmc_etr_setup_caps(dev, devid, &desc.access); + ret =3D tmc_etr_setup_caps(dev, drvdata->devid, &desc.access); if (ret) - goto out; + return ret; idr_init(&drvdata->idr); mutex_init(&drvdata->idr_mutex); dev_list =3D &etr_devs; @@ -851,44 +810,141 @@ static int __tmc_probe(struct device *dev, struct re= source *res) break; default: pr_err("%s: Unsupported TMC config\n", desc.name); - ret =3D -EINVAL; - goto out; + return -EINVAL; } =20 desc.name =3D coresight_alloc_device_name(dev_list, dev); - if (!desc.name) { - ret =3D -ENOMEM; + if (!desc.name) + return -ENOMEM; + + drvdata->desc_name =3D desc.name; + + desc.pdata =3D dev->platform_data; + + drvdata->csdev =3D coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + drvdata->miscdev.name =3D desc.name; + drvdata->miscdev.minor =3D MISC_DYNAMIC_MINOR; + drvdata->miscdev.fops =3D &tmc_fops; + ret =3D misc_register(&drvdata->miscdev); + if (ret) + coresight_unregister(drvdata->csdev); + + return ret; +} + +static void tmc_clear_self_claim_tag(struct tmc_drvdata *drvdata) +{ + struct csdev_access access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + + coresight_clear_self_claim_tag(&access); +} + +static void tmc_init_hw_config(struct tmc_drvdata *drvdata) +{ + u32 devid; + + devid =3D readl_relaxed(drvdata->base + CORESIGHT_DEVID); + drvdata->config_type =3D BMVAL(devid, 6, 7); + drvdata->memwidth =3D tmc_get_memwidth(devid); + drvdata->devid =3D devid; + drvdata->size =3D readl_relaxed(drvdata->base + TMC_RSZ) * 4; + tmc_clear_self_claim_tag(drvdata); +} + +static void tmc_init_on_cpu(void *info) +{ + struct tmc_drvdata *drvdata =3D info; + + tmc_init_hw_config(drvdata); +} + +static struct cpumask *tmc_get_supported_cpus(struct device *dev) +{ + struct generic_pm_domain *pd; + + pd =3D pd_to_genpd(dev->pm_domain); + if (pd) + return pd->cpus; + + return NULL; +} + +static int __tmc_probe(struct device *dev, struct resource *res) +{ + int cpu, ret =3D 0; + void __iomem *base; + struct coresight_platform_data *pdata =3D NULL; + struct tmc_drvdata *drvdata; + + drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + dev_set_drvdata(dev, drvdata); + + ret =3D coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk); + if (ret) + return ret; + + ret =3D -ENOMEM; + + /* Validity for the resource is already checked by the AMBA core */ + base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(base)) { + ret =3D PTR_ERR(base); goto out; } =20 + drvdata->base =3D base; + + raw_spin_lock_init(&drvdata->spinlock); + /* This device is not associated with a session */ + drvdata->pid =3D -1; + drvdata->etr_mode =3D ETR_MODE_AUTO; + tmc_get_reserved_region(dev); + pdata =3D coresight_get_platform_data(dev); if (IS_ERR(pdata)) { ret =3D PTR_ERR(pdata); goto out; } dev->platform_data =3D pdata; - desc.pdata =3D pdata; =20 - coresight_clear_self_claim_tag(&desc.access); - drvdata->csdev =3D coresight_register(&desc); - if (IS_ERR(drvdata->csdev)) { - ret =3D PTR_ERR(drvdata->csdev); - goto out; + if (fwnode_property_present(dev_fwnode(dev), "qcom,cpu-bound-components")= ) { + drvdata->supported_cpus =3D tmc_get_supported_cpus(dev); + if (!drvdata->supported_cpus) + return -EINVAL; + + cpus_read_lock(); + for_each_cpu(cpu, drvdata->supported_cpus) { + ret =3D smp_call_function_single(cpu, + tmc_init_on_cpu, drvdata, 1); + if (!ret) + break; + } + cpus_read_unlock(); + if (ret) { + ret =3D 0; + goto out; + } + } else { + tmc_init_hw_config(drvdata); } =20 - drvdata->miscdev.name =3D desc.name; - drvdata->miscdev.minor =3D MISC_DYNAMIC_MINOR; - drvdata->miscdev.fops =3D &tmc_fops; - ret =3D misc_register(&drvdata->miscdev); - if (ret) { - coresight_unregister(drvdata->csdev); - goto out; + if (drvdata->config_type =3D=3D TMC_CONFIG_TYPE_ETR) { + drvdata->size =3D tmc_etr_get_default_buffer_size(dev); + drvdata->max_burst_size =3D tmc_etr_get_max_burst_size(dev); } =20 + ret =3D tmc_add_coresight_dev(dev); + out: if (is_tmc_crashdata_valid(drvdata) && !tmc_prepare_crashdata(drvdata)) - register_crash_dev_interface(drvdata, desc.name); + register_crash_dev_interface(drvdata, drvdata->desc_name); return ret; } =20 @@ -934,10 +990,12 @@ static void __tmc_remove(struct device *dev) * etb fops in this case, device is there until last file * handler to this device is closed. */ - misc_deregister(&drvdata->miscdev); + if (!drvdata->supported_cpus) + misc_deregister(&drvdata->miscdev); if (drvdata->crashdev.fops) misc_deregister(&drvdata->crashdev); - coresight_unregister(drvdata->csdev); + if (drvdata->csdev) + coresight_unregister(drvdata->csdev); } =20 static void tmc_remove(struct amba_device *adev) @@ -992,7 +1050,6 @@ static void tmc_platform_remove(struct platform_device= *pdev) =20 if (WARN_ON(!drvdata)) return; - __tmc_remove(&pdev->dev); pm_runtime_disable(&pdev->dev); } diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 95473d1310323425b7d136cbd46f118faa7256be..b104b7bf82d2a7a99382636e41d= 3718cf258d820 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -243,6 +243,9 @@ struct tmc_resrv_buf { * (after crash) by default. * @crash_mdata: Reserved memory for storing tmc crash metadata. * Used by ETR/ETF. + * @supported_cpus: Represent the CPUs related to this TMC. + * @devid: TMC variant ID inferred from the device configuration register. + * @desc_name: Name to be used while creating crash interface. */ struct tmc_drvdata { struct clk *atclk; @@ -273,6 +276,9 @@ struct tmc_drvdata { struct etr_buf *perf_buf; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b04e58d423sm2564824eec.6.2025.12.18.00.10.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 00:10:49 -0800 (PST) From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:48 -0800 Subject: [PATCH v2 08/12] coresight-tmc-etf: Refactor enable function for CPU cluster ETF support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-cpu_cluster_component_pm-v2-8-2335a6ae62a0@oss.qualcomm.com> References: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> In-Reply-To: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang , maulik.shah@oss.qualcomm.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766045439; l=5305; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=1g8pF946hN6QW1p+2Y+2RyrV1bnSaFCc0AvdfQQfoFE=; b=WalzKq5mo+m1DDBa+j4hcG65FGQtoJ3y4iK+EaoBGFEl1Vw118qcQjkGDdZHOm1k6i33ttt5x 1kKC8wGvW7OBjHIQk7Fy4CY0PWitDwlSVzZ8QiZKiX/Izb0Z5cmPHwy X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE4MDA2NiBTYWx0ZWRfXxqn+1JPv2NGr 1ibi6+J6b0ZgpWVmabtXiduG86myGwlDk8TtI58/YKpCAcFn+fa5FFTqMthU+Le8OjatyATB92r Gvrbs2h2ylL0QOMCqnA4jLDo3ly5mtW+zbbasNR3hZG1MMf34KSt1SMT/7J9kx7ayMS3iRITO4s bsA4Qf9coAcdoEj01v2z3LOYaRXftkbmZ/SJfXyPzng4xJke7fR5VgNRLiL5xi7f/a+/8gRwelw 37aEddvC8/ir/usRLJYLeLcjvQXcaevCdn9NOYQBYL2eh0MtX8ii6cADe+42699mIFP294N6VN3 1N1+X2VcrpxA16mHblYkBVNMe33VDPsmFQhARJTDoFsX7ca7JsTU/uTDZTIumJb5EkZPptv9FRn xayVRGx4o2nMF+Mif52LwFleTDtIQg== X-Proofpoint-GUID: QpOLvbSU1m8_Km-3UefQEUIeMGTICPPu X-Proofpoint-ORIG-GUID: QpOLvbSU1m8_Km-3UefQEUIeMGTICPPu X-Authority-Analysis: v=2.4 cv=Zpjg6t7G c=1 sm=1 tr=0 ts=6943b70b cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ArRTHoG_oAt2a2GmjD0A:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-18_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 clxscore=1015 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512180066 TMC-ETF devices associated with specific CPU clusters share the cluster's power domain. Accessing their registers requires the cluster to be powered on, which can only be guaranteed by running code on a CPU within that cluster. Refactor the enablement logic to support this requirement: 1. Split `tmc_etf_enable_hw` and `tmc_etb_enable_hw` into local and SMP-aware variants: - `*_local`: Performs the actual register access. - `*_smp_call`: Wrapper for `smp_call_function_single`. - The main entry point now detects if the device is CPU-bound and uses `smp_call_function_single` to execute the local variant on an appropriate CPU if necessary. 2. Adjust locking in `tmc_enable_etf_sink_sysfs` and `tmc_enable_etf_link`: - Drop the spinlock before calling `tmc_etf_enable_hw`. This is necessary because `smp_call_function_single` (used for cross-CPU calls) may require interrupts enabled or might sleep/wait, which is unsafe under a spinlock. - Re-acquire the lock afterwards to update driver state. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 87 +++++++++++++++++++++= +--- 1 file changed, 77 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtr= acing/coresight/coresight-tmc-etf.c index 8882b1c4cdc05353fb2efd6a9ba862943048f0ff..11357788e9d93c53980e99e0ef7= 8450e393f4059 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -47,7 +47,7 @@ static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdat= a) return rc; } =20 -static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) +static int tmc_etb_enable_hw_local(struct tmc_drvdata *drvdata) { int rc =3D coresight_claim_device(drvdata->csdev); =20 @@ -60,6 +60,36 @@ static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) return rc; } =20 +struct tmc_smp_arg { + struct tmc_drvdata *drvdata; + int rc; +}; + +static void tmc_etb_enable_hw_smp_call(void *info) +{ + struct tmc_smp_arg *arg =3D info; + + arg->rc =3D tmc_etb_enable_hw_local(arg->drvdata); +} + +static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) +{ + int cpu, ret; + struct tmc_smp_arg arg =3D { 0 }; + + if (!drvdata->supported_cpus) + return tmc_etb_enable_hw_local(drvdata); + + arg.drvdata =3D drvdata; + for_each_cpu(cpu, drvdata->supported_cpus) { + ret =3D smp_call_function_single(cpu, + tmc_etb_enable_hw_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + return ret; +} + static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata) { char *bufp; @@ -130,7 +160,7 @@ static int __tmc_etf_enable_hw(struct tmc_drvdata *drvd= ata) return rc; } =20 -static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) +static int tmc_etf_enable_hw_local(struct tmc_drvdata *drvdata) { int rc =3D coresight_claim_device(drvdata->csdev); =20 @@ -143,6 +173,32 @@ static int tmc_etf_enable_hw(struct tmc_drvdata *drvda= ta) return rc; } =20 +static void tmc_etf_enable_hw_smp_call(void *info) +{ + struct tmc_smp_arg *arg =3D info; + + arg->rc =3D tmc_etf_enable_hw_local(arg->drvdata); +} + +static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) +{ + int cpu, ret; + struct tmc_smp_arg arg =3D { 0 }; + + if (!drvdata->supported_cpus) + return tmc_etf_enable_hw_local(drvdata); + + arg.drvdata =3D drvdata; + + for_each_cpu(cpu, drvdata->supported_cpus) { + ret =3D smp_call_function_single(cpu, + tmc_etf_enable_hw_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + return ret; +} + static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata) { struct coresight_device *csdev =3D drvdata->csdev; @@ -228,7 +284,11 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_= device *csdev) used =3D true; drvdata->buf =3D buf; } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + ret =3D tmc_etb_enable_hw(drvdata); + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); if (!ret) { coresight_set_mode(csdev, CS_MODE_SYSFS); csdev->refcnt++; @@ -291,7 +351,11 @@ static int tmc_enable_etf_sink_perf(struct coresight_d= evice *csdev, break; } =20 - ret =3D tmc_etb_enable_hw(drvdata); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b04e58d423sm2564824eec.6.2025.12.18.00.10.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 00:10:50 -0800 (PST) From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:49 -0800 Subject: [PATCH v2 09/12] coresight-tmc: Update management interface for CPU-bound TMCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-cpu_cluster_component_pm-v2-9-2335a6ae62a0@oss.qualcomm.com> References: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> In-Reply-To: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang , maulik.shah@oss.qualcomm.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766045439; l=5365; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=xSVwvf3r4THug/toaP/HzyHA8CkwtVjVbu+nopQb9No=; b=/9hBxZh5Oxuk1NiyBSNu5X4oibJZHzow5zfIAp/BBYoPkFuENMTHG6mReTKKYRE6E3WH70Tl1 xpME9EbqVX8CGkwTRi1SabeS+B1ywtGX0VHhQdWPM4HXR3n58/Cgb1U X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-ORIG-GUID: JRvVJtYSFfPY6V_Untd47Qjz2l2Cp3_q X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE4MDA2NiBTYWx0ZWRfX2QfsD8UucK2A GlRaJ9y4qtnrMG3rUbKA+W6a/8b832jCGOwKezapu64c3QoYAbD50ZjsTbTUjvkosKIBuvhoqIh UXuJI4L09zGLWjYlDJrO9uESHSuAZQD7/TC0LwsOlRTQr49rn+yv+hIIhXLbxbXF9q94CS3s/TY 7s/nAPs6SculE9biI7RWfx1OMU9Ps1bizVcD8VnQYjnHgQa+uIqhIwBFPmkLiU7KwTgt4vq99Oq xfP+rViWuPSR8lA6idCAc6iu3m2m/tb/ZOdDmDwEQO2HJ23FfGJTdkRWfhkj2iPlH7bdpQ5s5oH 5x7nobJaBtz7Qb2Dtl6wE4lvUzHu2acjIKdIKBd4ybqF1PeFS2uKR7Jm3yFyamwZSuqjGYIGHVM U35hkoc+7lLh0xGS0hYA/Gl7HjVfjQ== X-Authority-Analysis: v=2.4 cv=NPHYOk6g c=1 sm=1 tr=0 ts=6943b70c cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ZEnZJDymvn760SlnwMgA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: JRvVJtYSFfPY6V_Untd47Qjz2l2Cp3_q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-18_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 clxscore=1015 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512180066 The current TMC management interface (sysfs attributes) assumes that device registers can be accessed directly from any CPU. However, for TMCs associated with specific CPU clusters, registers must be accessed from a CPU within that cluster. Replace the standard `coresight_simple_reg*` handlers with custom accessors (`coresight_tmc_reg*`). These new handlers check if the TMC is bound to a specific set of CPUs: - If bound, they use `smp_call_function_single()` to read the register on an appropriate CPU. - If not bound (global TMC), they fall back to direct access. This ensures correct register reads for per-cluster TMC devices while maintaining backward compatibility for global TMCs. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tmc-core.c | 137 +++++++++++++++++++= +--- 1 file changed, 123 insertions(+), 14 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 0e1b5956398d3cefdd938a8a8404076eb4850b44..5b9f2e57c78f42f0f1460d8a8dc= bac72b5f6085e 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -458,21 +458,130 @@ static enum tmc_mem_intf_width tmc_get_memwidth(u32 = devid) return memwidth; } =20 +struct tmc_smp_arg { + struct tmc_drvdata *drvdata; + u32 offset; + int rc; +}; + +static void tmc_read_reg_smp_call(void *info) +{ + struct tmc_smp_arg *arg =3D info; + + arg->rc =3D readl_relaxed(arg->drvdata->base + arg->offset); +} + +static u32 cpu_tmc_read_reg(struct tmc_drvdata *drvdata, u32 offset) +{ + struct tmc_smp_arg arg =3D { + .drvdata =3D drvdata, + .offset =3D offset, + }; + int cpu, ret =3D 0; + + for_each_cpu(cpu, drvdata->supported_cpus) { + ret =3D smp_call_function_single(cpu, + tmc_read_reg_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + + return ret; +} + +static ssize_t coresight_tmc_reg32_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tmc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + struct cs_off_attribute *cs_attr =3D container_of(attr, struct cs_off_att= ribute, attr); + int ret; + u32 val; + + ret =3D pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; + + if (!drvdata->supported_cpus) + val =3D readl_relaxed(drvdata->base + cs_attr->off); + else + val =3D cpu_tmc_read_reg(drvdata, cs_attr->off); + + pm_runtime_put(dev->parent); + + if (ret < 0) + return ret; + else + return sysfs_emit(buf, "0x%x\n", val); +} + +static ssize_t coresight_tmc_reg64_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tmc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + struct cs_pair_attribute *cs_attr =3D container_of(attr, struct cs_pair_a= ttribute, attr); + int ret; + u64 val; + + ret =3D pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; + if (!drvdata->supported_cpus) { + val =3D readl_relaxed(drvdata->base + cs_attr->lo_off) | + ((u64)readl_relaxed(drvdata->base + cs_attr->hi_off) << 32); + } else { + ret =3D cpu_tmc_read_reg(drvdata, cs_attr->lo_off); + + if (ret < 0) + goto out; + + val =3D ret; + + ret =3D cpu_tmc_read_reg(drvdata, cs_attr->hi_off); + if (ret < 0) + goto out; + + val |=3D ((u64)ret << 32); + } + +out: + pm_runtime_put_sync(dev->parent); + if (ret < 0) + return ret; + else + return sysfs_emit(buf, "0x%llx\n", val); +} + +#define coresight_tmc_reg32(name, offset) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_tmc_reg32_show, NULL), \ + offset \ + } \ + })[0].attr.attr) +#define coresight_tmc_reg64(name, lo_off, hi_off) \ + (&((struct cs_pair_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_tmc_reg64_show, NULL), \ + lo_off, hi_off \ + } \ + })[0].attr.attr) static struct attribute *coresight_tmc_mgmt_attrs[] =3D { - coresight_simple_reg32(rsz, TMC_RSZ), - coresight_simple_reg32(sts, TMC_STS), - coresight_simple_reg64(rrp, TMC_RRP, TMC_RRPHI), - coresight_simple_reg64(rwp, TMC_RWP, TMC_RWPHI), - coresight_simple_reg32(trg, TMC_TRG), - coresight_simple_reg32(ctl, TMC_CTL), - coresight_simple_reg32(ffsr, TMC_FFSR), - coresight_simple_reg32(ffcr, TMC_FFCR), - coresight_simple_reg32(mode, TMC_MODE), - coresight_simple_reg32(pscr, TMC_PSCR), - coresight_simple_reg32(devid, CORESIGHT_DEVID), - coresight_simple_reg64(dba, TMC_DBALO, TMC_DBAHI), - coresight_simple_reg32(axictl, TMC_AXICTL), - coresight_simple_reg32(authstatus, TMC_AUTHSTATUS), + coresight_tmc_reg32(rsz, TMC_RSZ), + coresight_tmc_reg32(sts, TMC_STS), + coresight_tmc_reg64(rrp, TMC_RRP, TMC_RRPHI), + coresight_tmc_reg64(rwp, TMC_RWP, TMC_RWPHI), + coresight_tmc_reg32(trg, TMC_TRG), + coresight_tmc_reg32(ctl, TMC_CTL), + coresight_tmc_reg32(ffsr, TMC_FFSR), + coresight_tmc_reg32(ffcr, TMC_FFCR), + coresight_tmc_reg32(mode, TMC_MODE), + coresight_tmc_reg32(pscr, TMC_PSCR), + coresight_tmc_reg32(devid, CORESIGHT_DEVID), + coresight_tmc_reg64(dba, TMC_DBALO, TMC_DBAHI), + coresight_tmc_reg32(axictl, TMC_AXICTL), + coresight_tmc_reg32(authstatus, TMC_AUTHSTATUS), NULL, }; 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This prevents the driver from securely accessing the hardware or configuring it via smp_call_function_single(), which requires the target CPU to be available. To address this, defer the hardware initialization if the associated CPUs are offline: 1. Track such deferred devices in a global list. 2. Register a CPU hotplug callback (`tmc_online_cpu`) to detect when a relevant CPU comes online. 3. Upon CPU online, retry the hardware initialization and registration for the waiting TMC devices. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tmc-core.c | 59 ++++++++++++++++++++= +++- drivers/hwtracing/coresight/coresight-tmc.h | 4 ++ 2 files changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 5b9f2e57c78f42f0f1460d8a8dcbac72b5f6085e..9182fa8e4074a7c9739494b2f5d= 59be2e96f1d3d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -36,6 +36,9 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); +static LIST_HEAD(tmc_delay_probe); +static enum cpuhp_state hp_online; +static DEFINE_SPINLOCK(delay_lock); =20 int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) { @@ -1027,6 +1030,8 @@ static int __tmc_probe(struct device *dev, struct res= ource *res) if (!drvdata->supported_cpus) return -EINVAL; =20 + drvdata->dev =3D dev; + cpus_read_lock(); for_each_cpu(cpu, drvdata->supported_cpus) { ret =3D smp_call_function_single(cpu, @@ -1034,11 +1039,16 @@ static int __tmc_probe(struct device *dev, struct r= esource *res) if (!ret) break; } - cpus_read_unlock(); + if (ret) { + scoped_guard(spinlock, &delay_lock) + list_add(&drvdata->link, &tmc_delay_probe); + cpus_read_unlock(); ret =3D 0; goto out; } + + cpus_read_unlock(); } else { tmc_init_hw_config(drvdata); } @@ -1103,8 +1113,12 @@ static void __tmc_remove(struct device *dev) misc_deregister(&drvdata->miscdev); if (drvdata->crashdev.fops) misc_deregister(&drvdata->crashdev); - if (drvdata->csdev) + if (drvdata->csdev) { coresight_unregister(drvdata->csdev); + } else { + scoped_guard(spinlock, &delay_lock) + list_del(&drvdata->link); + } } =20 static void tmc_remove(struct amba_device *adev) @@ -1215,14 +1229,55 @@ static struct platform_driver tmc_platform_driver = =3D { }, }; =20 +static int tmc_online_cpu(unsigned int cpu) +{ + struct tmc_drvdata *drvdata, *tmp; + int ret; + + spin_lock(&delay_lock); + list_for_each_entry_safe(drvdata, tmp, &tmc_delay_probe, link) { + if (cpumask_test_cpu(cpu, drvdata->supported_cpus)) { + list_del(&drvdata->link); + + spin_unlock(&delay_lock); + ret =3D pm_runtime_resume_and_get(drvdata->dev); + if (ret < 0) + return 0; + + tmc_init_hw_config(drvdata); + tmc_clear_self_claim_tag(drvdata); + tmc_add_coresight_dev(drvdata->dev); + pm_runtime_put(drvdata->dev); + spin_lock(&delay_lock); + } + } + spin_unlock(&delay_lock); + return 0; +} + static int __init tmc_init(void) { + int ret; + + ret =3D cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, + "arm/coresight-tmc:online", + tmc_online_cpu, NULL); + + if (ret > 0) + hp_online =3D ret; + else + return ret; + return coresight_init_driver("tmc", &tmc_driver, &tmc_platform_driver, TH= IS_MODULE); } =20 static void __exit tmc_exit(void) { coresight_remove_driver(&tmc_driver, &tmc_platform_driver); + if (hp_online) { + cpuhp_remove_state_nocalls(hp_online); + hp_online =3D 0; + } } module_init(tmc_init); module_exit(tmc_exit); diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index b104b7bf82d2a7a99382636e41d3718cf258d820..2583bc4f556195cd814e674dc66= f08909dea61b2 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -246,6 +246,8 @@ struct tmc_resrv_buf { * @supported_cpus: Represent the CPUs related to this TMC. * @devid: TMC variant ID inferred from the device configuration register. * @desc_name: Name to be used while creating crash interface. + * @dev: pointer to the device associated with this TMC. + * @link: link to the delay_probed list. */ struct tmc_drvdata { struct clk *atclk; @@ -279,6 +281,8 @@ struct tmc_drvdata { struct cpumask *supported_cpus; u32 devid; const char *desc_name; + struct device *dev; + struct list_head link; }; =20 struct etr_buf_operations { --=20 2.34.1 From nobody Mon Feb 9 01:00:52 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86C1632FA05 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b04e58d423sm2564824eec.6.2025.12.18.00.10.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 00:10:52 -0800 (PST) From: Yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:51 -0800 Subject: [PATCH v2 11/12] coresight: Pass trace mode to link enable callback Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-cpu_cluster_component_pm-v2-11-2335a6ae62a0@oss.qualcomm.com> References: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> In-Reply-To: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang , maulik.shah@oss.qualcomm.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766045439; l=9596; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=ZizRFuPaK/LitwSdLNplW7Ev2jbzENlbotIRtyE7yN8=; b=DvqIqB9difxf+/WNfzFJe9N1imzh6BaFyNq7kAFHLDqhsY5fPBidwE1QfWrPkOYyWGR1N6cRo d8tKIhkyqE/DoVZXOYngviSgeIOuKSuS9KNpN6JPBrG7YgwGpi32Fhr X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-ORIG-GUID: j79qlZ0DstXiOtFOmwYHarrNq3NQQUdf X-Proofpoint-GUID: j79qlZ0DstXiOtFOmwYHarrNq3NQQUdf X-Authority-Analysis: v=2.4 cv=f8JFxeyM c=1 sm=1 tr=0 ts=6943b70f cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=_ycWAoKx6aYVZ7XB0rUA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE4MDA2NiBTYWx0ZWRfX8RoUg8ccLql8 RkIKMhqI9yQXRxN5Nr9jO3zcJ6mgOVyYiO5yMh0Ud7gHjmssqx2QguC+A8A++iziLiMz859l/Hw DsMaH6X0uoUJ/D8ifltuKfkF/7tSrLDYzx/sJKWzEssg3eAJMb4thMH16ibzYrbiPwTbUJkFThz z+pZxx6xhSSZUKPBv3IX2zBQAbxyEwBTus97StjJXf4yZ1TENwCVRF+aLlqkOWZYh2NgHcMos5g DvnszjiR/Rsnzpri8owdqcmf0ZCJclukdHX4qbpdwlujhNP+kCJonpbTsM9sXdq0nbQpMN30+Hu Px3D8fueFfC/kBtXxmLvEQSgHAqeaKjCK/BW4t/gW34RweX0ibjHVL8wzum7NBWkr6oV+0mQF8l Itmv+RFppJv1mMjY2eYyfQ+Pmoy86Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-18_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 clxscore=1015 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512180066 Currently, the link enable callback does not receive the CoreSight mode (enum cs_mode). This prevents link drivers from knowing whether they are being enabled for SysFS or Perf. This distinction is crucial because Perf mode runs in atomic context, where certain operations (like smp_call_function_single()) are unsafe. Without knowing the mode, drivers cannot conditionally avoid these unsafe calls. Update the `enable` callback in `struct coresight_ops_link` to accept `enum cs_mode`. This allows drivers to implement mode-specific logic, such as using atomic-safe enablement sequences when running in Perf mode. Update all call sites and driver implementations accordingly. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-core.c | 7 ++++--- drivers/hwtracing/coresight/coresight-funnel.c | 21 ++++++++++++++++++= +- drivers/hwtracing/coresight/coresight-replicator.c | 23 ++++++++++++++++++= +++- drivers/hwtracing/coresight/coresight-tmc-etf.c | 19 +++++++++++++++++- drivers/hwtracing/coresight/coresight-tnoc.c | 3 ++- drivers/hwtracing/coresight/coresight-tpda.c | 3 ++- include/linux/coresight.h | 3 ++- 7 files changed, 70 insertions(+), 9 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index c660cf8adb1c7cafff8f85e501f056e4e151e372..1863bdb57281b4fd405cf966d56= 5c581506ea270 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -314,7 +314,8 @@ static void coresight_disable_sink(struct coresight_dev= ice *csdev) static int coresight_enable_link(struct coresight_device *csdev, struct coresight_device *parent, struct coresight_device *child, - struct coresight_device *source) + struct coresight_device *source, + enum cs_mode mode) { int link_subtype; struct coresight_connection *inconn, *outconn; @@ -331,7 +332,7 @@ static int coresight_enable_link(struct coresight_devic= e *csdev, if (link_subtype =3D=3D CORESIGHT_DEV_SUBTYPE_LINK_SPLIT && IS_ERR(outcon= n)) return PTR_ERR(outconn); =20 - return link_ops(csdev)->enable(csdev, inconn, outconn); + return link_ops(csdev)->enable(csdev, inconn, outconn, mode); } =20 static void coresight_disable_link(struct coresight_device *csdev, @@ -550,7 +551,7 @@ int coresight_enable_path(struct coresight_path *path, = enum cs_mode mode) case CORESIGHT_DEV_TYPE_LINK: parent =3D list_prev_entry(nd, link)->csdev; child =3D list_next_entry(nd, link)->csdev; - ret =3D coresight_enable_link(csdev, parent, child, source); + ret =3D coresight_enable_link(csdev, parent, child, source, mode); if (ret) goto err_disable_helpers; break; diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtra= cing/coresight/coresight-funnel.c index 5d114ce1109f4f9a8b108110bdae258f216881d8..c50522c2854c7193a8c30b1a603= abe566a1c1ccf 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -121,7 +121,8 @@ static int funnel_enable_hw(struct funnel_drvdata *drvd= ata, int port) =20 static int funnel_enable(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { int rc =3D 0; struct funnel_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); @@ -135,6 +136,23 @@ static int funnel_enable(struct coresight_device *csde= v, else in->dest_refcnt++; =20 + if (mode =3D=3D CS_MODE_PERF) { + if (first_enable) { + if (drvdata->supported_cpus && + !cpumask_test_cpu(smp_processor_id(), drvdata->supported_cpus)) { + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EINVAL; + } + + if (drvdata->base) + rc =3D dynamic_funnel_enable_hw(drvdata, in->dest_port); + if (!rc) + in->dest_refcnt++; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return rc; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 if (first_enable) { @@ -183,6 +201,7 @@ static void funnel_disable(struct coresight_device *csd= ev, dynamic_funnel_disable_hw(drvdata, in->dest_port); last_disable =3D true; } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 if (last_disable) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/h= wtracing/coresight/coresight-replicator.c index a9f22d0e15de21aa06c8d1e193e5db06091efd75..cc7d3916b8b9d5d342d6cde0487= 722eeb8dee78b 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -199,7 +199,8 @@ static int replicator_enable_hw(struct replicator_drvda= ta *drvdata, =20 static int replicator_enable(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { int rc =3D 0; struct replicator_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); @@ -212,6 +213,25 @@ static int replicator_enable(struct coresight_device *= csdev, first_enable =3D true; else out->src_refcnt++; + + if (mode =3D=3D CS_MODE_PERF) { + if (first_enable) { + if (drvdata->supported_cpus && + !cpumask_test_cpu(smp_processor_id(), drvdata->supported_cpus)) { + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EINVAL; + } + + if (drvdata->base) + rc =3D dynamic_replicator_enable(drvdata, in->dest_port, + out->src_port); + if (!rc) + out->src_refcnt++; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return rc; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 if (first_enable) { @@ -272,6 +292,7 @@ static void replicator_disable(struct coresight_device = *csdev, out->src_port); last_disable =3D true; } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 if (last_disable) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtr= acing/coresight/coresight-tmc-etf.c index 11357788e9d93c53980e99e0ef78450e393f4059..f1b8264b4e5c8a8d38778c25515= cbf557c0993b7 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -427,7 +427,8 @@ static int tmc_disable_etf_sink(struct coresight_device= *csdev) =20 static int tmc_enable_etf_link(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { int ret =3D 0; unsigned long flags; @@ -446,6 +447,22 @@ static int tmc_enable_etf_link(struct coresight_device= *csdev, if (!first_enable) csdev->refcnt++; =20 + if (mode =3D=3D CS_MODE_PERF) { + if (first_enable) { + if (drvdata->supported_cpus && + !cpumask_test_cpu(smp_processor_id(), drvdata->supported_cpus)) { + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EINVAL; + } + + ret =3D tmc_etf_enable_hw_local(drvdata); + if (!ret) + csdev->refcnt++; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); if (first_enable) { ret =3D tmc_etf_enable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtraci= ng/coresight/coresight-tnoc.c index ff9a0a9cfe96e5f5e3077c750ea2f890cdd50d94..48e9e685b9439d92bdaae9e40d3= b3bc2d1ac1cd2 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.c +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -73,7 +73,8 @@ static void trace_noc_enable_hw(struct trace_noc_drvdata = *drvdata) } =20 static int trace_noc_enable(struct coresight_device *csdev, struct coresig= ht_connection *inport, - struct coresight_connection *outport) + struct coresight_connection *outport, + enum cs_mode mode) { struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); =20 diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtraci= ng/coresight/coresight-tpda.c index 3a3825d27f861585ca1d847929747f8096004089..e6f52abc5b023a997c36d74c0e3= b1a3de8236ba2 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -190,7 +190,8 @@ static int __tpda_enable(struct tpda_drvdata *drvdata, = int port) =20 static int tpda_enable(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { struct tpda_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); int ret =3D 0; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 2b48be97fcd0d7ea2692206692bd33f35ba4ec79..218eb1d1dcef61f5d98ebbfff38= 370192b8a6e45 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -383,7 +383,8 @@ struct coresight_ops_sink { struct coresight_ops_link { int (*enable)(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b04e58d423sm2564824eec.6.2025.12.18.00.10.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 00:10:53 -0800 (PST) From: yuanfang Zhang Date: Thu, 18 Dec 2025 00:09:52 -0800 Subject: [PATCH v2 12/12] arm64: dts: qcom: hamoa: Add CoreSight nodes for APSS debug block Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251218-cpu_cluster_component_pm-v2-12-2335a6ae62a0@oss.qualcomm.com> References: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> In-Reply-To: <20251218-cpu_cluster_component_pm-v2-0-2335a6ae62a0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang , maulik.shah@oss.qualcomm.com, Jie Gan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1766045439; l=20225; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=OSpn+qOE01+ChQYG4B4E7m17DuVeVtvMUxcLoJ3PwDU=; b=YafyrU0mQNdNr7r/T2pwh3fMGQJww52o1W/HEABZaTXedXw+u3EBGOYrqpr2tDZj+D1boOLIq I7n8I1ypa6mAnDJ6CsXHm752F6qKICRgwdD3xmIckiFuZX7rO5i9ygC X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-GUID: pGne7_SEuq_ifesVIlYN2oHj8a5rxEFX X-Authority-Analysis: v=2.4 cv=DsBbOW/+ c=1 sm=1 tr=0 ts=6943b70f cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=rG_eRC_tWg5vcVVOg78A:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE4MDA2NiBTYWx0ZWRfX8XpCmSG5p9L7 6CDyclmqbQACJWRLvZLvJTTSQ+obDgT9IEpuLpNjyZmm8Zor+NwtrjmPQNYxKoAkuAY4/JRWNkJ HP7R1V39cT7efg7WPVDE/gES+Whx9QDKnc8Z83qEckkWjoXF0+t/0OD51a2GcJbqFGKPD4RNjVB X+0PO9Rzz74TRe3Tun2Qzfq5nrpMuTanZbVcGy8rPMx2kKgQR4lraFVK7m/npnLXzthSPrTpFVl kEfiaX9sxd8oU5wHh+8wcwLCLvLSdv6laGAtznYtzD4RiOyUleHvdOlivnweFxHTMJvpvQe2Iug lJ5FDh4XXsIwg7ucB0omQSd8weKVW8Z2G68kwBv0H5ILpvY3TjwBB7uQ3NfjOJxmp0KVztlVBh4 qkjJrTrZPREjhnYDswgVrVxT9Alb1Q== X-Proofpoint-ORIG-GUID: pGne7_SEuq_ifesVIlYN2oHj8a5rxEFX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-18_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 adultscore=0 clxscore=1015 bulkscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512180066 From: Jie Gan The APSS debug block is built with CoreSight devices like ETM, replicator, funnel and TMC ETF. Add dt nodes for these devices to enable ETM trace. Signed-off-by: Jie Gan Co-developed-by: Yuanfang Zhang Signed-off-by: Yuanfang Zhang --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 926 ++++++++++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/purwa.dtsi | 12 + 2 files changed, 938 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom= /hamoa.dtsi index a17900eacb20396a9792efcfcd6ce6dd877435d1..8c3de8bf058daa681db040c4a9a= 38253863e6c78 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -305,6 +305,210 @@ eud_in: endpoint { }; }; =20 + etm-0 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu0>; + qcom,skip-power-up; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint =3D <&ncc0_0_rep_in>; + }; + }; + }; + }; + + etm-1 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu1>; + qcom,skip-power-up; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint =3D <&ncc0_1_rep_in>; + }; + }; + }; + }; + + etm-2 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu2>; + qcom,skip-power-up; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint =3D <&ncc0_2_rep_in>; + }; + }; + }; + }; + + etm-3 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu3>; + qcom,skip-power-up; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint =3D <&ncc0_3_rep_in>; + }; + }; + }; + }; + + etm-4 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu4>; + qcom,skip-power-up; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint =3D <&ncc1_0_rep_in>; + }; + }; + }; + }; + + etm-5 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu5>; + qcom,skip-power-up; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint =3D <&ncc1_1_rep_in>; + }; + }; + }; + }; + + etm-6 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu6>; + qcom,skip-power-up; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint =3D <&ncc1_2_rep_in>; + }; + }; + }; + }; + + etm-7 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu7>; + qcom,skip-power-up; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint =3D <&ncc1_3_rep_in>; + }; + }; + }; + }; + + etm8: etm-8 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu8>; + qcom,skip-power-up; + + out-ports { + port { + etm8_out: endpoint { + remote-endpoint =3D <&ncc2_0_rep_in>; + }; + }; + }; + }; + + etm9: etm-9 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu9>; + qcom,skip-power-up; + + out-ports { + port { + etm9_out: endpoint { + remote-endpoint =3D <&ncc2_1_rep_in>; + }; + }; + }; + }; + + etm10: etm-10 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu10>; + qcom,skip-power-up; + + out-ports { + port { + etm10_out: endpoint { + remote-endpoint =3D <&ncc2_2_rep_in>; + }; + }; + }; + }; + + etm11: etm-11 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu11>; + qcom,skip-power-up; + + out-ports { + port { + etm11_out: endpoint { + remote-endpoint =3D <&ncc2_3_rep_in>; + }; + }; + }; + }; + firmware { scm: scm { compatible =3D "qcom,scm-x1e80100", "qcom,scm"; @@ -6864,6 +7068,14 @@ funnel1_in2: endpoint { }; }; =20 + port@4 { + reg =3D <4>; + + funnel1_in4: endpoint { + remote-endpoint =3D <&apss_funnel_out>; + }; + }; + port@5 { reg =3D <5>; =20 @@ -8154,6 +8366,720 @@ ddr_funnel1_out: endpoint { }; }; =20 + apss_funnel: funnel@12080000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x12080000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + apss_funnel_in0: endpoint { + remote-endpoint =3D <&ncc0_etf_out>; + }; + }; + + port@1 { + reg =3D <1>; + + apss_funnel_in1: endpoint { + remote-endpoint =3D <&ncc1_etf_out>; + }; + }; + + port@2 { + reg =3D <2>; + + apss_funnel_in2: endpoint { + remote-endpoint =3D <&ncc2_etf_out>; + }; + }; + }; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint =3D <&funnel1_in4>; + }; + }; + }; + }; + + funnel@13401000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb908>; + reg =3D <0x0 0x13401000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd0>; + qcom,cpu-bound-components; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + + ncc0_2_funnel_in2: endpoint { + remote-endpoint =3D <&ncc0_1_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc0_2_funnel_out: endpoint { + remote-endpoint =3D <&ncc0_etf_in>; + }; + }; + }; + }; + + tmc@13409000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb961>; + reg =3D <0x0 0x13409000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd0>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_etf_in: endpoint { + remote-endpoint =3D <&ncc0_2_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc0_etf_out: endpoint { + remote-endpoint =3D <&apss_funnel_in0>; + }; + }; + }; + }; + + replicator@13490000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb909>; + reg =3D <0x0 0x13490000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd0>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_0_rep_in: endpoint { + remote-endpoint =3D <&etm0_out>; + }; + }; + }; + + out-ports { + port { + ncc0_0_rep_out: endpoint { + remote-endpoint =3D <&ncc0_1_funnel_in0>; + }; + }; + }; + }; + + replicator@134a0000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb909>; + reg =3D <0x0 0x134a0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd0>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_1_rep_in: endpoint { + remote-endpoint =3D <&etm1_out>; + }; + }; + }; + + out-ports { + port { + ncc0_1_rep_out: endpoint { + remote-endpoint =3D <&ncc0_1_funnel_in1>; + }; + }; + }; + }; + + replicator@134b0000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb909>; + reg =3D <0x0 0x134b0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd0>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_2_rep_in: endpoint { + remote-endpoint =3D <&etm2_out>; + }; + }; + }; + + out-ports { + port { + ncc0_2_rep_out: endpoint { + remote-endpoint =3D <&ncc0_1_funnel_in2>; + }; + }; + }; + }; + + replicator@134c0000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb909>; + reg =3D <0x0 0x134c0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd0>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc0_3_rep_in: endpoint { + remote-endpoint =3D <&etm3_out>; + }; + }; + }; + + out-ports { + port { + ncc0_3_rep_out: endpoint { + remote-endpoint =3D <&ncc0_1_funnel_in3>; + }; + }; + }; + }; + + funnel@134d0000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb908>; + reg =3D <0x0 0x134d0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd0>; + qcom,cpu-bound-components; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + ncc0_1_funnel_in0: endpoint { + remote-endpoint =3D <&ncc0_0_rep_out>; + }; + }; + + port@1 { + reg =3D <1>; + + ncc0_1_funnel_in1: endpoint { + remote-endpoint =3D <&ncc0_1_rep_out>; + }; + }; + + port@2 { + reg =3D <2>; + + ncc0_1_funnel_in2: endpoint { + remote-endpoint =3D <&ncc0_2_rep_out>; + }; + }; + + port@3 { + reg =3D <3>; + + ncc0_1_funnel_in3: endpoint { + remote-endpoint =3D <&ncc0_3_rep_out>; + }; + }; + }; + + out-ports { + port { + ncc0_1_funnel_out: endpoint { + remote-endpoint =3D <&ncc0_2_funnel_in2>; + }; + }; + }; + }; + + funnel@13901000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb908>; + reg =3D <0x0 0x13901000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd1>; + qcom,cpu-bound-components; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + + ncc1_2_funnel_in2: endpoint { + remote-endpoint =3D <&ncc1_1_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc1_2_funnel_out: endpoint { + remote-endpoint =3D <&ncc1_etf_in>; + }; + }; + }; + }; + + tmc@13909000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb961>; + reg =3D <0x0 0x13909000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd1>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_etf_in: endpoint { + remote-endpoint =3D <&ncc1_2_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc1_etf_out: endpoint { + remote-endpoint =3D <&apss_funnel_in1>; + }; + }; + }; + }; + + replicator@13990000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb909>; + reg =3D <0x0 0x13990000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd1>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_0_rep_in: endpoint { + remote-endpoint =3D <&etm4_out>; + }; + }; + }; + + out-ports { + port { + ncc1_0_rep_out: endpoint { + remote-endpoint =3D <&ncc1_1_funnel_in0>; + }; + }; + }; + }; + + replicator@139a0000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb909>; + reg =3D <0x0 0x139a0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd1>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_1_rep_in: endpoint { + remote-endpoint =3D <&etm5_out>; + }; + }; + }; + + out-ports { + port { + ncc1_1_rep_out: endpoint { + remote-endpoint =3D <&ncc1_1_funnel_in1>; + }; + }; + }; + }; + + replicator@139b0000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb909>; + reg =3D <0x0 0x139b0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd1>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_2_rep_in: endpoint { + remote-endpoint =3D <&etm6_out>; + }; + }; + }; + + out-ports { + port { + ncc1_2_rep_out: endpoint { + remote-endpoint =3D <&ncc1_1_funnel_in2>; + }; + }; + }; + }; + + replicator@139c0000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb909>; + reg =3D <0x0 0x139c0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd1>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc1_3_rep_in: endpoint { + remote-endpoint =3D <&etm7_out>; + }; + }; + }; + + out-ports { + port { + ncc1_3_rep_out: endpoint { + remote-endpoint =3D <&ncc1_1_funnel_in3>; + }; + }; + }; + }; + + funnel@139d0000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb908>; + reg =3D <0x0 0x139d0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd1>; + qcom,cpu-bound-components; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + ncc1_1_funnel_in0: endpoint { + remote-endpoint =3D <&ncc1_0_rep_out>; + }; + }; + + port@1 { + reg =3D <1>; + + ncc1_1_funnel_in1: endpoint { + remote-endpoint =3D <&ncc1_1_rep_out>; + }; + }; + + port@2 { + reg =3D <2>; + + ncc1_1_funnel_in2: endpoint { + remote-endpoint =3D <&ncc1_2_rep_out>; + }; + }; + + port@3 { + reg =3D <3>; + + ncc1_1_funnel_in3: endpoint { + remote-endpoint =3D <&ncc1_3_rep_out>; + }; + }; + }; + + out-ports { + port { + ncc1_1_funnel_out: endpoint { + remote-endpoint =3D <&ncc1_2_funnel_in2>; + }; + }; + }; + }; + + cluster2_funnel_l2: funnel@13e01000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb908>; + reg =3D <0x0 0x13e01000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd2>; + qcom,cpu-bound-components; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + + ncc2_2_funnel_in2: endpoint { + remote-endpoint =3D <&ncc2_1_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc2_2_funnel_out: endpoint { + remote-endpoint =3D <&ncc2_etf_in>; + }; + }; + }; + }; + + cluster2_etf: tmc@13e09000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb961>; + reg =3D <0x0 0x13e09000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd2>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_etf_in: endpoint { + remote-endpoint =3D <&ncc2_2_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc2_etf_out: endpoint { + remote-endpoint =3D <&apss_funnel_in2>; + }; + }; + }; + }; + + cluster2_rep_2_0: replicator@13e90000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb909>; + reg =3D <0x0 0x13e90000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd2>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_0_rep_in: endpoint { + remote-endpoint =3D <&etm8_out>; + }; + }; + }; + + out-ports { + port { + ncc2_0_rep_out: endpoint { + remote-endpoint =3D <&ncc2_1_funnel_in0>; + }; + }; + }; + }; + + cluster2_rep_2_1: replicator@13ea0000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb909>; + reg =3D <0x0 0x13ea0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd2>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_1_rep_in: endpoint { + remote-endpoint =3D <&etm9_out>; + }; + }; + }; + + out-ports { + port { + ncc2_1_rep_out: endpoint { + remote-endpoint =3D <&ncc2_1_funnel_in1>; + }; + }; + }; + }; + + cluster2_rep_2_2: replicator@13eb0000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb909>; + reg =3D <0x0 0x13eb0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd2>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_2_rep_in: endpoint { + remote-endpoint =3D <&etm10_out>; + }; + }; + }; + + out-ports { + port { + ncc2_2_rep_out: endpoint { + remote-endpoint =3D <&ncc2_1_funnel_in2>; + }; + }; + }; + }; + + cluster2_rep_2_3: replicator@13ec0000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb909>; + reg =3D <0x0 0x13ec0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd2>; + qcom,cpu-bound-components; + + in-ports { + port { + ncc2_3_rep_in: endpoint { + remote-endpoint =3D <&etm11_out>; + }; + }; + }; + + out-ports { + port { + ncc2_3_rep_out: endpoint { + remote-endpoint =3D <&ncc2_1_funnel_in3>; + }; + }; + }; + }; + + cluster2_funnel_l1: funnel@13ed0000 { + compatible =3D "arm,primecell"; + arm,primecell-periphid =3D <0x000bb908>; + reg =3D <0x0 0x13ed0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd2>; + qcom,cpu-bound-components; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + ncc2_1_funnel_in0: endpoint { + remote-endpoint =3D <&ncc2_0_rep_out>; + }; + }; + + port@1 { + reg =3D <1>; + + ncc2_1_funnel_in1: endpoint { + remote-endpoint =3D <&ncc2_1_rep_out>; + }; + }; + + port@2 { + reg =3D <2>; + + ncc2_1_funnel_in2: endpoint { + remote-endpoint =3D <&ncc2_2_rep_out>; + }; + }; + + port@3 { + reg =3D <3>; + + ncc2_1_funnel_in3: endpoint { + remote-endpoint =3D <&ncc2_3_rep_out>; + }; + }; + }; + + out-ports { + port { + ncc2_1_funnel_out: endpoint { + remote-endpoint =3D <&ncc2_2_funnel_in2>; + }; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible =3D "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg =3D <0 0x15000000 0 0x100000>; diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom= /purwa.dtsi index 2cecd2dd0de8c39f0702d6983bead2bc2adccf9b..38f2df9e42b60b5f22decfb4643= 81bce214d414d 100644 --- a/arch/arm64/boot/dts/qcom/purwa.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa.dtsi @@ -21,6 +21,18 @@ /delete-node/ &gpu_speed_bin; /delete-node/ &pcie3_phy; /delete-node/ &thermal_zones; +/delete-node/ &etm8; +/delete-node/ &etm9; +/delete-node/ &etm10; +/delete-node/ &etm11; +/delete-node/ &cluster2_funnel_l1; +/delete-node/ &cluster2_funnel_l2; +/delete-node/ &cluster2_etf; +/delete-node/ &cluster2_rep_2_0; +/delete-node/ &cluster2_rep_2_1; +/delete-node/ &cluster2_rep_2_2; +/delete-node/ &cluster2_rep_2_3; +/delete-node/ &apss_funnel_in2; =20 &gcc { compatible =3D "qcom,x1p42100-gcc", "qcom,x1e80100-gcc"; --=20 2.34.1