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b=YGprAFTCKpvpd/JNfYny0Ev/d6Z9FTyNnfPl5+uB3hK37sbFYGLN2RF7Z9zIKjA95nBpSPsybg+I6oEYJpH86pU4c5v3HPR9eb1Wvn1gXSlSoGf8L/Zvr64NYFQcvwOu+VUa91kmIdyEYRuzVdStljejp3FoW+O4x1NQXg5aYlQ= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=valinux.co.jp; Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) by TYCP286MB2863.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:306::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.6; Wed, 17 Dec 2025 15:16:28 +0000 Received: from TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03]) by TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM ([fe80::fb7e:f4ed:a580:9d03%5]) with mapi id 15.20.9434.001; Wed, 17 Dec 2025 15:16:28 +0000 From: Koichiro Den To: Frank.Li@nxp.com, dave.jiang@intel.com, ntb@lists.linux.dev, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: mani@kernel.org, kwilczynski@kernel.org, kishon@kernel.org, bhelgaas@google.com, corbet@lwn.net, geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, jdmason@kudzu.us, allenbh@gmail.com, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com, kurt.schwemmer@microsemi.com, logang@deltatee.com, jingoohan1@gmail.com, lpieralisi@kernel.org, utkarsh02t@gmail.com, jbrunet@baylibre.com, dlemoal@kernel.org, arnd@arndb.de, elfring@users.sourceforge.net, den@valinux.co.jp Subject: [RFC PATCH v3 17/35] dmaengine: dw-edma: Add helper func to retrieve register base and size Date: Thu, 18 Dec 2025 00:15:51 +0900 Message-ID: <20251217151609.3162665-18-den@valinux.co.jp> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251217151609.3162665-1-den@valinux.co.jp> References: <20251217151609.3162665-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCP286CA0045.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:29d::19) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:24c::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYWP286MB2697:EE_|TYCP286MB2863:EE_ X-MS-Office365-Filtering-Correlation-Id: ef2448f9-ffd7-4a4a-56ba-08de3d7f4093 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|10070799003|1800799024|366016; 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charset="utf-8" Remote eDMA users (e.g. NTB) may need to expose the integrated DW eDMA register block through a memory window. Add a helper function that returns the physical base and size for a given DesignWare EP controller. Signed-off-by: Koichiro Den --- .../pci/controller/dwc/pcie-designware-ep.c | 1 + drivers/pci/controller/dwc/pcie-designware.c | 25 +++++++++++++++++++ include/linux/dma/edma.h | 24 ++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 9480aebaa32a..46d18e7945db 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -12,6 +12,7 @@ #include =20 #include "pcie-designware.h" +#include #include #include =20 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 75fc8b767fcc..1de88df7b1af 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -162,8 +162,12 @@ int dw_pcie_get_resources(struct dw_pcie *pci) pci->edma.reg_base =3D devm_ioremap_resource(pci->dev, res); if (IS_ERR(pci->edma.reg_base)) return PTR_ERR(pci->edma.reg_base); + pci->edma.reg_phys =3D res->start; + pci->edma.reg_size =3D resource_size(res); } else if (pci->atu_size >=3D 2 * DEFAULT_DBI_DMA_OFFSET) { pci->edma.reg_base =3D pci->atu_base + DEFAULT_DBI_DMA_OFFSET; + pci->edma.reg_phys =3D pci->atu_phys_addr + DEFAULT_DBI_DMA_OFFSET; + pci->edma.reg_size =3D pci->atu_size - DEFAULT_DBI_DMA_OFFSET; } } =20 @@ -1204,3 +1208,24 @@ resource_size_t dw_pcie_parent_bus_offset(struct dw_= pcie *pci, =20 return cpu_phys_addr - reg_addr; } + +int dw_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys, size_t = *sz) +{ + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); + struct dw_pcie *pci; + + if (!ep) + return -ENODEV; + + pci =3D to_dw_pcie_from_ep(ep); + if (!pci->edma.reg_base || !pci->edma.reg_phys) + return -ENODEV; + + if (phys) + *phys =3D pci->edma.reg_phys; + if (sz) + *sz =3D pci->edma.reg_size; + + return 0; +} +EXPORT_SYMBOL_GPL(dw_edma_get_reg_window); diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 3080747689f6..11d6eeb19fff 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -11,6 +11,7 @@ =20 #include #include +#include =20 #define EDMA_MAX_WR_CH 8 #define EDMA_MAX_RD_CH 8 @@ -60,6 +61,27 @@ enum dw_edma_chip_flags { DW_EDMA_CHIP_LOCAL =3D BIT(0), }; =20 +#if IS_REACHABLE(CONFIG_PCIE_DW) +/** + * dw_edma_get_reg_window - get eDMA register base and size + * + * @epc: the EPC device with which the eDMA instance is integrated + * @phys: the output parameter that returns the register base address + * @sz: the output parameter that returns the register space size + * + * Remote eDMA users (e.g. NTB) may need to expose the integrated DW eDMA + * register block through a memory window. This helper returns the physical + * base and size for a given DesignWare EP controller. + */ +int dw_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys, size_t = *sz); +#else +static inline int dw_edma_get_reg_window(struct pci_epc *epc, phys_addr_t = *phys, + size_t *sz) +{ + return -ENODEV; +} +#endif /* CONFIG_PCIE_DW */ + /** * struct dw_edma_chip - representation of DesignWare eDMA controller hard= ware * @dev: struct device of the eDMA controller @@ -85,6 +107,8 @@ struct dw_edma_chip { u32 flags; =20 void __iomem *reg_base; + phys_addr_t reg_phys; + size_t reg_size; =20 u16 ll_wr_cnt; u16 ll_rd_cnt; --=20 2.51.0