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([82.78.167.134]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4310adf701csm4508000f8f.42.2025.12.17.05.52.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Dec 2025 05:52:27 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, fabrizio.castro.jz@renesas.com, biju.das.jz@bp.renesas.com, geert+renesas@glider.be, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , stable@vger.kernel.org Subject: [PATCH v5 2/6] dmaengine: sh: rz-dmac: Move all CHCTRL updates under spinlock Date: Wed, 17 Dec 2025 15:52:09 +0200 Message-ID: <20251217135213.400280-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> References: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Both rz_dmac_disable_hw() and rz_dmac_irq_handle_channel() update the CHCTRL registers. To avoid concurrency issues when updating these registers, take the virtual channel lock. All other CHCTRL updates were already protected by the same lock. Previously, rz_dmac_disable_hw() disabled and re-enabled local IRQs, before accessing CHCTRL registers but this does not ensure race-free access. Remove the local IRQ disable/enable code as well. Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Cc: stable@vger.kernel.org Signed-off-by: Claudiu Beznea --- Changes in v5: - none, this patch is new drivers/dma/sh/rz-dmac.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index c8e3d9f77b8a..c013bf30fa5e 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -298,13 +298,10 @@ static void rz_dmac_disable_hw(struct rz_dmac_chan *c= hannel) { struct dma_chan *chan =3D &channel->vc.chan; struct rz_dmac *dmac =3D to_rz_dmac(chan->device); - unsigned long flags; =20 dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index); =20 - local_irq_save(flags); rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); - local_irq_restore(flags); } =20 static void rz_dmac_set_dmars_register(struct rz_dmac *dmac, int nr, u32 d= mars) @@ -569,8 +566,8 @@ static int rz_dmac_terminate_all(struct dma_chan *chan) unsigned int i; LIST_HEAD(head); =20 - rz_dmac_disable_hw(channel); spin_lock_irqsave(&channel->vc.lock, flags); + rz_dmac_disable_hw(channel); for (i =3D 0; i < DMAC_NR_LMDESC; i++) lmdesc[i].header =3D 0; =20 @@ -721,6 +718,8 @@ static irqreturn_t rz_dmac_irq_handler(int irq, void *d= ev_id) { struct rz_dmac_chan *channel =3D dev_id; =20 + guard(spinlock)(&channel->vc.lock); + if (channel) { rz_dmac_irq_handle_channel(channel); return IRQ_WAKE_THREAD; --=20 2.43.0