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([82.78.167.134]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4310adf701csm4508000f8f.42.2025.12.17.05.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Dec 2025 05:52:26 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, fabrizio.castro.jz@renesas.com, biju.das.jz@bp.renesas.com, geert+renesas@glider.be, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , stable@vger.kernel.org Subject: [PATCH v5 1/6] dmaengine: sh: rz-dmac: Protect the driver specific lists Date: Wed, 17 Dec 2025 15:52:08 +0200 Message-ID: <20251217135213.400280-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> References: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The driver lists (ld_free, ld_queue) are used in rz_dmac_free_chan_resources(), rz_dmac_terminate_all(), rz_dmac_issue_pending(), and rz_dmac_irq_handler_thread(), all under the virtual channel lock. Take the same lock in rz_dmac_prep_slave_sg() and rz_dmac_prep_dma_memcpy() as well to avoid concurrency issues, since these functions also check whether the lists are empty and update or remove list entries. Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Cc: stable@vger.kernel.org Signed-off-by: Claudiu Beznea --- Changes in v5: - none, this patch is new drivers/dma/sh/rz-dmac.c | 57 ++++++++++++++++++++++------------------ 1 file changed, 32 insertions(+), 25 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 9e5f088355e2..c8e3d9f77b8a 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -10,6 +10,7 @@ */ =20 #include +#include #include #include #include @@ -448,6 +449,7 @@ static int rz_dmac_alloc_chan_resources(struct dma_chan= *chan) if (!desc) break; =20 + /* No need to lock. This is called only for the 1st client. */ list_add_tail(&desc->node, &channel->ld_free); channel->descs_allocated++; } @@ -503,18 +505,21 @@ rz_dmac_prep_dma_memcpy(struct dma_chan *chan, dma_ad= dr_t dest, dma_addr_t src, dev_dbg(dmac->dev, "%s channel: %d src=3D0x%pad dst=3D0x%pad len=3D%zu\n", __func__, channel->index, &src, &dest, len); =20 - if (list_empty(&channel->ld_free)) - return NULL; + scoped_guard(spinlock_irqsave, &channel->vc.lock) { + if (list_empty(&channel->ld_free)) + return NULL; + + desc =3D list_first_entry(&channel->ld_free, struct rz_dmac_desc, node); =20 - desc =3D list_first_entry(&channel->ld_free, struct rz_dmac_desc, node); + desc->type =3D RZ_DMAC_DESC_MEMCPY; + desc->src =3D src; + desc->dest =3D dest; + desc->len =3D len; + desc->direction =3D DMA_MEM_TO_MEM; =20 - desc->type =3D RZ_DMAC_DESC_MEMCPY; - desc->src =3D src; - desc->dest =3D dest; - desc->len =3D len; - desc->direction =3D DMA_MEM_TO_MEM; + list_move_tail(channel->ld_free.next, &channel->ld_queue); + } =20 - list_move_tail(channel->ld_free.next, &channel->ld_queue); return vchan_tx_prep(&channel->vc, &desc->vd, flags); } =20 @@ -530,27 +535,29 @@ rz_dmac_prep_slave_sg(struct dma_chan *chan, struct s= catterlist *sgl, int dma_length =3D 0; int i =3D 0; =20 - if (list_empty(&channel->ld_free)) - return NULL; + scoped_guard(spinlock_irqsave, &channel->vc.lock) { + if (list_empty(&channel->ld_free)) + return NULL; =20 - desc =3D list_first_entry(&channel->ld_free, struct rz_dmac_desc, node); + desc =3D list_first_entry(&channel->ld_free, struct rz_dmac_desc, node); =20 - for_each_sg(sgl, sg, sg_len, i) { - dma_length +=3D sg_dma_len(sg); - } + for_each_sg(sgl, sg, sg_len, i) + dma_length +=3D sg_dma_len(sg); =20 - desc->type =3D RZ_DMAC_DESC_SLAVE_SG; - desc->sg =3D sgl; - desc->sgcount =3D sg_len; - desc->len =3D dma_length; - desc->direction =3D direction; + desc->type =3D RZ_DMAC_DESC_SLAVE_SG; + desc->sg =3D sgl; + desc->sgcount =3D sg_len; + desc->len =3D dma_length; + desc->direction =3D direction; =20 - if (direction =3D=3D DMA_DEV_TO_MEM) - desc->src =3D channel->src_per_address; - else - desc->dest =3D channel->dst_per_address; + if (direction =3D=3D DMA_DEV_TO_MEM) + desc->src =3D channel->src_per_address; + else + desc->dest =3D channel->dst_per_address; + + list_move_tail(channel->ld_free.next, &channel->ld_queue); + } =20 - list_move_tail(channel->ld_free.next, &channel->ld_queue); return vchan_tx_prep(&channel->vc, &desc->vd, flags); } =20 --=20 2.43.0 From nobody Mon Feb 9 14:34:43 2026 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 910632701D9 for ; Wed, 17 Dec 2025 13:52:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765979554; cv=none; b=fo4X7AL2gOvcnNJleBfooqQ8KpvxnGJOl1nR3Kl+19cVJqS5sS83379ps3X310elfq/b7tvpBiX22B+En504JsghmjCyyc1cATgUQTnh+j/yJFM9Zoz+/YDhDZ2HF7ORBCey2BJrad23Z7aK3AqyBBwhwr9orolIcsiAXSKr7CY= ARC-Message-Signature: i=1; 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([82.78.167.134]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4310adf701csm4508000f8f.42.2025.12.17.05.52.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Dec 2025 05:52:27 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, fabrizio.castro.jz@renesas.com, biju.das.jz@bp.renesas.com, geert+renesas@glider.be, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , stable@vger.kernel.org Subject: [PATCH v5 2/6] dmaengine: sh: rz-dmac: Move all CHCTRL updates under spinlock Date: Wed, 17 Dec 2025 15:52:09 +0200 Message-ID: <20251217135213.400280-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> References: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Both rz_dmac_disable_hw() and rz_dmac_irq_handle_channel() update the CHCTRL registers. To avoid concurrency issues when updating these registers, take the virtual channel lock. All other CHCTRL updates were already protected by the same lock. Previously, rz_dmac_disable_hw() disabled and re-enabled local IRQs, before accessing CHCTRL registers but this does not ensure race-free access. Remove the local IRQ disable/enable code as well. Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Cc: stable@vger.kernel.org Signed-off-by: Claudiu Beznea --- Changes in v5: - none, this patch is new drivers/dma/sh/rz-dmac.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index c8e3d9f77b8a..c013bf30fa5e 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -298,13 +298,10 @@ static void rz_dmac_disable_hw(struct rz_dmac_chan *c= hannel) { struct dma_chan *chan =3D &channel->vc.chan; struct rz_dmac *dmac =3D to_rz_dmac(chan->device); - unsigned long flags; =20 dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index); =20 - local_irq_save(flags); rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); - local_irq_restore(flags); } =20 static void rz_dmac_set_dmars_register(struct rz_dmac *dmac, int nr, u32 d= mars) @@ -569,8 +566,8 @@ static int rz_dmac_terminate_all(struct dma_chan *chan) unsigned int i; LIST_HEAD(head); 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([82.78.167.134]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4310adf701csm4508000f8f.42.2025.12.17.05.52.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Dec 2025 05:52:29 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, fabrizio.castro.jz@renesas.com, biju.das.jz@bp.renesas.com, geert+renesas@glider.be, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v5 3/6] dmaengine: sh: rz-dmac: Drop unnecessary local_irq_save() call Date: Wed, 17 Dec 2025 15:52:10 +0200 Message-ID: <20251217135213.400280-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> References: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea rz_dmac_enable_hw() calls local_irq_save()/local_irq_restore(), but this is not needed because the callers of rz_dmac_enable_hw() already protect the critical section using spin_lock_irqsave()/spin_lock_irqrestore= (). Remove the local_irq_save()/local_irq_restore() calls. Signed-off-by: Claudiu Beznea --- Changes in v5: - none, this patch is new drivers/dma/sh/rz-dmac.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index c013bf30fa5e..ae8a4bd9d7fa 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -267,15 +267,12 @@ static void rz_dmac_enable_hw(struct rz_dmac_chan *ch= annel) { struct dma_chan *chan =3D &channel->vc.chan; struct rz_dmac *dmac =3D to_rz_dmac(chan->device); - unsigned long flags; u32 nxla; u32 chctrl; u32 chstat; =20 dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index); =20 - local_irq_save(flags); - rz_dmac_lmdesc_recycle(channel); =20 nxla =3D channel->lmdesc.base_dma + @@ -290,8 +287,6 @@ static void rz_dmac_enable_hw(struct rz_dmac_chan *chan= nel) rz_dmac_ch_writel(channel, CHCTRL_SWRST, CHCTRL, 1); rz_dmac_ch_writel(channel, chctrl, CHCTRL, 1); } - - local_irq_restore(flags); } =20 static void rz_dmac_disable_hw(struct rz_dmac_chan *channel) --=20 2.43.0 From nobody Mon Feb 9 14:34:43 2026 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA90C36CE0B for ; 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([82.78.167.134]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4310adf701csm4508000f8f.42.2025.12.17.05.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Dec 2025 05:52:30 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, fabrizio.castro.jz@renesas.com, biju.das.jz@bp.renesas.com, geert+renesas@glider.be, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v5 4/6] dmaengine: sh: rz-dmac: Add rz_dmac_invalidate_lmdesc() Date: Wed, 17 Dec 2025 15:52:11 +0200 Message-ID: <20251217135213.400280-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> References: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add rz_dmac_invalidate_lmdesc() so that the same code can be shared between rz_dmac_terminate_all() and rz_dmac_free_chan_resources(). Based on a patch in the BSP by Long Luu . Signed-off-by: Biju Das [claudiu.beznea: adjusted the commit description; defined the lmdesc inside the for block to have more compact code] Signed-off-by: Claudiu Beznea --- Changes in v5: - adjusted the commit description - defined the lmdesc inside the for block drivers/dma/sh/rz-dmac.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index ae8a4bd9d7fa..bb5677f5a318 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -250,6 +250,13 @@ static void rz_lmdesc_setup(struct rz_dmac_chan *chann= el, * Descriptors preparation */ =20 +static void rz_dmac_invalidate_lmdesc(struct rz_dmac_chan *channel) +{ + for (struct rz_lmdesc *lmdesc =3D channel->lmdesc.base; + lmdesc < channel->lmdesc.base + DMAC_NR_LMDESC; lmdesc++) + lmdesc->header =3D 0; +} + static void rz_dmac_lmdesc_recycle(struct rz_dmac_chan *channel) { struct rz_lmdesc *lmdesc =3D channel->lmdesc.head; @@ -456,15 +463,12 @@ static void rz_dmac_free_chan_resources(struct dma_ch= an *chan) { struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); struct rz_dmac *dmac =3D to_rz_dmac(chan->device); - struct rz_lmdesc *lmdesc =3D channel->lmdesc.base; struct rz_dmac_desc *desc, *_desc; unsigned long flags; - unsigned int i; =20 spin_lock_irqsave(&channel->vc.lock, flags); =20 - for (i =3D 0; i < DMAC_NR_LMDESC; i++) - lmdesc[i].header =3D 0; + rz_dmac_invalidate_lmdesc(channel); =20 rz_dmac_disable_hw(channel); list_splice_tail_init(&channel->ld_active, &channel->ld_free); @@ -556,15 +560,12 @@ rz_dmac_prep_slave_sg(struct dma_chan *chan, struct s= catterlist *sgl, static int rz_dmac_terminate_all(struct dma_chan *chan) { struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); - struct rz_lmdesc *lmdesc =3D channel->lmdesc.base; unsigned long flags; - unsigned int i; LIST_HEAD(head); =20 spin_lock_irqsave(&channel->vc.lock, flags); rz_dmac_disable_hw(channel); - for (i =3D 0; i < DMAC_NR_LMDESC; i++) - lmdesc[i].header =3D 0; + rz_dmac_invalidate_lmdesc(channel); =20 list_splice_tail_init(&channel->ld_active, &channel->ld_free); list_splice_tail_init(&channel->ld_queue, &channel->ld_free); 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([82.78.167.134]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4310adf701csm4508000f8f.42.2025.12.17.05.52.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Dec 2025 05:52:31 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, fabrizio.castro.jz@renesas.com, biju.das.jz@bp.renesas.com, geert+renesas@glider.be, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v5 5/6] dmaengine: sh: rz-dmac: Add device_tx_status() callback Date: Wed, 17 Dec 2025 15:52:12 +0200 Message-ID: <20251217135213.400280-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> References: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for device_tx_status() callback as it is needed for RZ/G2L SCIFA driver. Based on a patch in the BSP similar to rcar-dmac by Long Luu . Signed-off-by: Biju Das [claudiu.beznea: - post-increment lmdesc in rz_dmac_get_next_lmdesc() to allow the next pointer to advance - use 'lmdesc->nxla !=3D crla' comparison instead of '!(lmdesc->nxla =3D=3D crla)' in rz_dmac_calculate_residue_bytes_in_vd() - in rz_dmac_calculate_residue_bytes_in_vd() use '++i >=3D DMAC_NR_LMDESC' to verify if the full lmdesc list was checked - drop rz_dmac_calculate_total_bytes_in_vd() and use desc->len instead - re-arranged comments so they span fewer lines and are wrapped to ~80 characters - use u32 for the residue value and the functions returning it - use u32 for the variables storing register values - fixed typos] Signed-off-by: Claudiu Beznea --- Changes in v5: - post-increment lmdesc in rz_dmac_get_next_lmdesc() to allow the next pointer to advance - use 'lmdesc->nxla !=3D crla' comparison instead of '!(lmdesc->nxla =3D=3D crla)' in rz_dmac_calculate_residue_bytes_in_vd() - in rz_dmac_calculate_residue_bytes_in_vd() use '++i >=3D DMAC_NR_LMDESC' to verify if the full lmdesc list was checked - drop rz_dmac_calculate_total_bytes_in_vd() and use desc->len instead - re-arranged comments so they span fewer lines and are wrapped to ~80 characters - use u32 for the residue value and the functions returning it - use u32 for the variables storing register values - fixed typos drivers/dma/sh/rz-dmac.c | 144 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 143 insertions(+), 1 deletion(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index bb5677f5a318..c3035b94ef2c 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -119,10 +119,12 @@ struct rz_dmac { * Registers */ =20 +#define CRTB 0x0020 #define CHSTAT 0x0024 #define CHCTRL 0x0028 #define CHCFG 0x002c #define NXLA 0x0038 +#define CRLA 0x003c =20 #define DCTRL 0x0000 =20 @@ -685,6 +687,146 @@ static void rz_dmac_device_synchronize(struct dma_cha= n *chan) } } =20 +static struct rz_lmdesc * +rz_dmac_get_next_lmdesc(struct rz_lmdesc *base, struct rz_lmdesc *lmdesc) +{ + struct rz_lmdesc *next =3D ++lmdesc; + + if (next >=3D base + DMAC_NR_LMDESC) + next =3D base; + + return next; +} + +static u32 rz_dmac_calculate_residue_bytes_in_vd(struct rz_dmac_chan *chan= nel) +{ + struct rz_lmdesc *lmdesc =3D channel->lmdesc.head; + struct dma_chan *chan =3D &channel->vc.chan; + struct rz_dmac *dmac =3D to_rz_dmac(chan->device); + u32 residue =3D 0, crla, i =3D 0; + + crla =3D rz_dmac_ch_readl(channel, CRLA, 1); + while (lmdesc->nxla !=3D crla) { + lmdesc =3D rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); + if (++i >=3D DMAC_NR_LMDESC) + return 0; + } + + /* Calculate residue from next lmdesc to end of virtual desc */ + while (lmdesc->chcfg & CHCFG_DEM) { + residue +=3D lmdesc->tb; + lmdesc =3D rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); + } + + dev_dbg(dmac->dev, "%s: VD residue is %u\n", __func__, residue); + + return residue; +} + +static u32 rz_dmac_chan_get_residue(struct rz_dmac_chan *channel, + dma_cookie_t cookie) +{ + struct rz_dmac_desc *current_desc, *desc; + enum dma_status status; + u32 crla, crtb, i; + + /* Get current processing virtual descriptor */ + current_desc =3D list_first_entry(&channel->ld_active, + struct rz_dmac_desc, node); + if (!current_desc) + return 0; + + /* + * If the cookie corresponds to a descriptor that has been completed + * there is no residue. The same check has already been performed by the + * caller but without holding the channel lock, so the descriptor could + * now be complete. + */ + status =3D dma_cookie_status(&channel->vc.chan, cookie, NULL); + if (status =3D=3D DMA_COMPLETE) + return 0; + + /* + * If the cookie doesn't correspond to the currently processing virtual + * descriptor then the descriptor hasn't been processed yet, and the + * residue is equal to the full descriptor size. Also, a client driver + * is possible to call this function before rz_dmac_irq_handler_thread() + * runs. In this case, the running descriptor will be the next + * descriptor, and will appear in the done list. So, if the argument + * cookie matches the done list's cookie, we can assume the residue is + * zero. + */ + if (cookie !=3D current_desc->vd.tx.cookie) { + list_for_each_entry(desc, &channel->ld_free, node) { + if (cookie =3D=3D desc->vd.tx.cookie) + return 0; + } + + list_for_each_entry(desc, &channel->ld_queue, node) { + if (cookie =3D=3D desc->vd.tx.cookie) + return desc->len; + } + + list_for_each_entry(desc, &channel->ld_active, node) { + if (cookie =3D=3D desc->vd.tx.cookie) + return desc->len; + } + + /* + * No descriptor found for the cookie, there's thus no residue. + * This shouldn't happen if the calling driver passes a correct + * cookie value. + */ + WARN(1, "No descriptor for cookie!"); + return 0; + } + + /* + * We need to read two registers. Make sure the hardware does not move + * to next lmdesc while reading the current lmdesc. Trying it 3 times + * should be enough: initial read, retry, retry for the paranoid. + */ + for (i =3D 0; i < 3; i++) { + crla =3D rz_dmac_ch_readl(channel, CRLA, 1); + crtb =3D rz_dmac_ch_readl(channel, CRTB, 1); + /* Still the same? */ + if (crla =3D=3D rz_dmac_ch_readl(channel, CRLA, 1)) + break; + } + + WARN_ONCE(i >=3D 3, "residue might not be continuous!"); + + /* + * Calculate number of byte transferred in processing virtual descriptor. + * One virtual descriptor can have many lmdesc. + */ + return crtb + rz_dmac_calculate_residue_bytes_in_vd(channel); +} + +static enum dma_status rz_dmac_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); + enum dma_status status; + u32 residue; + + status =3D dma_cookie_status(chan, cookie, txstate); + if (status =3D=3D DMA_COMPLETE || !txstate) + return status; + + scoped_guard(spinlock_irqsave, &channel->vc.lock) + residue =3D rz_dmac_chan_get_residue(channel, cookie); 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([82.78.167.134]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4310adf701csm4508000f8f.42.2025.12.17.05.52.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Dec 2025 05:52:33 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, fabrizio.castro.jz@renesas.com, biju.das.jz@bp.renesas.com, geert+renesas@glider.be, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v5 6/6] dmaengine: sh: rz-dmac: Add device_{pause,resume}() callbacks Date: Wed, 17 Dec 2025 15:52:13 +0200 Message-ID: <20251217135213.400280-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> References: <20251217135213.400280-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for device_{pause, resume}() callbacks. These are required by the RZ/G2L SCIFA driver. Signed-off-by: Claudiu Beznea --- Changes in v5: - used suspend capability of the controller to pause/resume the transfers drivers/dma/sh/rz-dmac.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index c3035b94ef2c..e349ade1845f 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -135,6 +135,7 @@ struct rz_dmac { #define CHANNEL_8_15_COMMON_BASE 0x0700 =20 #define CHSTAT_ER BIT(4) +#define CHSTAT_SUS BIT(3) #define CHSTAT_EN BIT(0) =20 #define CHCTRL_CLRINTMSK BIT(17) @@ -827,6 +828,38 @@ static enum dma_status rz_dmac_tx_status(struct dma_ch= an *chan, return status; } =20 +static int rz_dmac_device_pause(struct dma_chan *chan) +{ + struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); + u32 val; + + scoped_guard(spinlock_irqsave, &channel->vc.lock) { + val =3D rz_dmac_ch_readl(channel, CHCTRL, 1); + val |=3D CHCTRL_CLRSUS; + rz_dmac_ch_writel(channel, val, CHCTRL, 1); + } + + return read_poll_timeout_atomic(rz_dmac_ch_readl, val, + (val & CHSTAT_SUS), 1, 1024, false, + channel, CHSTAT, 1); +} + +static int rz_dmac_device_resume(struct dma_chan *chan) +{ + struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); + u32 val; + + scoped_guard(spinlock_irqsave, &channel->vc.lock) { + val =3D rz_dmac_ch_readl(channel, CHCTRL, 1); + val &=3D ~CHCTRL_CLRSUS; + rz_dmac_ch_writel(channel, val, CHCTRL, 1); + } + + return read_poll_timeout_atomic(rz_dmac_ch_readl, val, + !(val & CHSTAT_SUS), 1, 1024, false, + channel, CHSTAT, 1); +} + /* * -----------------------------------------------------------------------= ------ * IRQ handling @@ -1164,6 +1197,8 @@ static int rz_dmac_probe(struct platform_device *pdev) engine->device_terminate_all =3D rz_dmac_terminate_all; engine->device_issue_pending =3D rz_dmac_issue_pending; engine->device_synchronize =3D rz_dmac_device_synchronize; + engine->device_pause =3D rz_dmac_device_pause; + engine->device_resume =3D rz_dmac_device_resume; =20 engine->copy_align =3D DMAENGINE_ALIGN_1_BYTE; dma_set_max_seg_size(engine->dev, U32_MAX); --=20 2.43.0