From nobody Fri Dec 19 04:24:43 2025 Received: from canpmsgout08.his.huawei.com (canpmsgout08.his.huawei.com [113.46.200.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 231BD38256C for ; Wed, 17 Dec 2025 10:24:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765967050; cv=none; b=bGgqQCRUyMrah5FvgYJPXH6ZvByYsPIMoX+JI45+Aapkzu32G58eBnXlTcqJvqWyFoISErId2XOJSEBjnCSKJIddbZ7FX5aBA3GkMraYaK03MxnRlnOnQiuuHz85mn73foRNf4vuLsU3q8liDVhpTH2D+IZX/wzbNBchx2xsC98= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765967050; c=relaxed/simple; bh=Y282AHykFxSpmLu+oop34QDySHbT7EXtQn6iqIwSf2s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Pt2ySUPnL0RRLT+1PYapgKbSADhVFRcAFg6NQo9dSb6tAWRglk9nXeBADnYgIvNMTah3ZL4mfwM9SnH+pmXm+8AOZjHUz27kz850py/LNdypqvGURG+IxTH+10/t16hYBPLA7RGjNpjA80oxZzU4751uCXjQVmlfqWoHXoSKvhU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=V75LHEwz; arc=none smtp.client-ip=113.46.200.223 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="V75LHEwz" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=/11PSfoNJiCB0S3r7lxetYykBp8m2J09NrdyjAFKzW0=; b=V75LHEwzoX+WZ+qwBi2raIZc6V3x+6v/Pj1S9pQU3RirSZ4DPt+SGAY3Y8YoO+C06h8Z/TB/k Pf20zG8wbR3n3NriNojMJfvxsXDDRX23q6+Vj8T6AQbOo6SQV8y88DzBu8dgwfqqZOwvSQGWoSP gk7XtqUpELVGNW/i2upeGuM= Received: from mail.maildlp.com (unknown [172.19.162.112]) by canpmsgout08.his.huawei.com (SkyGuard) with ESMTPS id 4dWVGH3VywzmV6s; Wed, 17 Dec 2025 18:21:59 +0800 (CST) Received: from dggemv712-chm.china.huawei.com (unknown [10.1.198.32]) by mail.maildlp.com (Postfix) with ESMTPS id 5325A140109; Wed, 17 Dec 2025 18:24:00 +0800 (CST) Received: from kwepemn100008.china.huawei.com (7.202.194.111) by dggemv712-chm.china.huawei.com (10.1.198.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 17 Dec 2025 18:24:00 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemn100008.china.huawei.com (7.202.194.111) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Wed, 17 Dec 2025 18:23:59 +0800 From: Yushan Wang To: , , , , , CC: , , , , , , , , Subject: [PATCH RFC v2 3/3] Documentation: soc cache: Add documentation to HiSilicon SoC cache Date: Wed, 17 Dec 2025 18:23:57 +0800 Message-ID: <20251217102357.1730573-4-wangyushan12@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20251217102357.1730573-1-wangyushan12@huawei.com> References: <20251217102357.1730573-1-wangyushan12@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500001.china.huawei.com (7.221.188.70) To kwepemn100008.china.huawei.com (7.202.194.111) Content-Type: text/plain; charset="utf-8" Add necessary documentation to HiSilicon SoC cache for reference. Signed-off-by: Yushan Wang --- Documentation/driver-api/hisi-soc-cache.rst | 62 +++++++++++++++++++++ Documentation/driver-api/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 64 insertions(+) create mode 100644 Documentation/driver-api/hisi-soc-cache.rst diff --git a/Documentation/driver-api/hisi-soc-cache.rst b/Documentation/dr= iver-api/hisi-soc-cache.rst new file mode 100644 index 000000000000..3c17de79bba2 --- /dev/null +++ b/Documentation/driver-api/hisi-soc-cache.rst @@ -0,0 +1,62 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D +HiSilicon SoC Cache Driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D + +Introduction +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +HiSilicon SoC cache provides the capabilities of preventing given range of +memory from being evicted from L3 cache. The driver exports the lockdown A= PI to +userspace, allowing allocation of memory that is guranteed to be placed in= L3 +cache, thus decreasing average memory access latency. + +Usage +=3D=3D=3D=3D=3D + +Kernel built with CONFIG_HISI_SOC_CACHE on will have the device file at +`/dev/hisi_l3c`, cache operations can be performed through it. + +mmap(): +------- + +This interface can be used to allocate memory that is guranteed to not be +evicted out of HiSilicon L3 cache. Newly allocated memory will be prefetch= ed to +L3 cache automatically. + +Users should set `PROT_READ` or `PROT_WRITE` to enable read/write to the m= emory +region. Once mmap call succeeds, read and write can be applied to the memo= ry +region indicated by the returned pointer. + +Calling `munmap()` to the pointer can be used to unlock the memory regions. + +Restrictions of the cache lockdown are listed below: + - Only limited number of memory regions are supported, the exact number = is + reported by firmware. + - Sum of the sizes of locked memory regions should be less than 70% of t= he + total size of cache instance. + - Lock/unlock can only be performed during allocation/deallocation, lock= ing + existing memory is not supported yet. + +ioctl(): +-------- + +This interface provides useful information of HiSilicon L3 cache. + +HISI_L3C_LOCK_INFO + - struct hisi_l3c_lock_info (read) + + Gets detailed information of L3 cache lock restrictions. + +This ioctl call returns the detailed information of HiSilicon L3 cache lock +restriction. Information will be presented in the form of:: + + struct hisi_l3c_lock_info { + unsigned int lock_region_num; + size_t lock_size; + bool address_alignment; + size_t max_lock_size; + size_t min_lock_size; + }; + +User may perform a query before issueing cache lock to check for available +resource. diff --git a/Documentation/driver-api/index.rst b/Documentation/driver-api/= index.rst index 1833e6a0687e..a1d4bf2a22de 100644 --- a/Documentation/driver-api/index.rst +++ b/Documentation/driver-api/index.rst @@ -95,6 +95,7 @@ Subsystem-specific APIs generic-counter generic_pt gpio/index + hisi-soc-cache hsi hte/index hw-recoverable-errors diff --git a/MAINTAINERS b/MAINTAINERS index f09b718f59fd..bb79ed1f9d45 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11369,6 +11369,7 @@ F: drivers/soc/hisilicon/kunpeng_hccs.h HISILICON SOC L3C DRIVER M: Yushan Wang S: Maintained +F: Documentation/driver-api/hisi-soc-cache.rst F: drivers/soc/hisilicon/hisi_soc_l3c.c F: include/uapi/misc/hisi_l3c.h =20 --=20 2.33.0