From nobody Fri Dec 19 17:16:33 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43D0333EB04 for ; Wed, 17 Dec 2025 08:25:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765959937; cv=none; b=Elvv56ybWgLkpF+L3zO1HlM2b79OJuKxkrEVlw89zu53vU+QaTITsjS4cbwxgWPyaqP0DpySOzgn9FMiEQwoW+NG/57P1ws+1olN9dmpO0c7x32FyUPUVZbOjfJ92a7jpD8NiKedbRV8xLegXYdalU5N52CAJhcdvCNQmYvqdgc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765959937; c=relaxed/simple; bh=evFZwjlzvXHjkqK0R2AFe3sUyEqQ9n7YUfDCJh3pUhI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Bjji38wq9xan2492fxjrUhnsP4RNw4ZdbegwHlztHM7h6W37/nOwdw91+SejTf6vuDxv1M0FVQ4sD8saoy2X1KnRCuGTLFpXKJ97ZB8+kuk92WQBwr//fPRtb4qLD9VgBrZWuMkOVokwTR/YLG96GtwBjUsqguxBgNd/6CWOo0A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=U8AhfwTm; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="U8AhfwTm" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 83FF21A2278; Wed, 17 Dec 2025 08:25:32 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5B16D6072F; Wed, 17 Dec 2025 08:25:32 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 0079F119502E3; Wed, 17 Dec 2025 09:25:27 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1765959929; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=aEM5QbdUXJsRLpURVvs7QvZzTARrGZdkj7npX4h2AHg=; b=U8AhfwTmv42+iyY4wmGOZfLDUHZG27Q5ff7hdfcZu88RprrIP8d0vS1cIF8wM+Oz1sOOGS YmTiHbZx+VgpQnIUhOYQ5hDOUMKZYtq7kzVCcuF8mqw42D/QQgbLzqQDs0vwEDPrlkjLxm jFDNKEZcCg4qucRvrT4fPox5YjszphmoKOzzl0X+iLBg3N5JSuYEnc0k1uKYi5SC25GxE6 NmfRcCJY+dc+eiIaQnFRHnA9SddSCHY01n02PV/eA6XIAMnlwS73SqWqywgFGTp1zzGnJS JJqj+Gir9Aja9kpo2rKbMwKLQkRQu6bhVAVkNp/xwcuAk2UQz24qcEq0HDaO0A== From: Richard Genoud To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel Cc: Thomas Petazzoni , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud , Joao Schim Subject: [PATCH v2 3/4] arm64: dts: allwinner: h616: add PWM controller Date: Wed, 17 Dec 2025 09:25:03 +0100 Message-ID: <20251217082504.80226-4-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251217082504.80226-1-richard.genoud@bootlin.com> References: <20251217082504.80226-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The H616 has a PWM controller that can provide PWM signals, but also plain clocks. Add the PWM controller node and pins in the device tree. Tested-by: Joao Schim Signed-off-by: Richard Genoud --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-h616.dtsi index 8d1110c14bad..1c7628a6e4bb 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -236,6 +236,17 @@ watchdog: watchdog@30090a0 { clocks =3D <&osc24M>; }; =20 + pwm: pwm@300a000 { + compatible =3D "allwinner,sun50i-h616-pwm"; + reg =3D <0x0300a000 0x400>; + clocks =3D <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names =3D "mod", "bus"; + resets =3D <&ccu RST_BUS_PWM>; + #pwm-cells =3D <3>; + #clock-cells =3D <1>; + status =3D "disabled"; + }; + pio: pinctrl@300b000 { compatible =3D "allwinner,sun50i-h616-pinctrl"; reg =3D <0x0300b000 0x400>; @@ -340,6 +351,42 @@ nand_rb1_pin: nand-rb1-pin { bias-pull-up; }; =20 + /omit-if-no-ref/ + pwm0_pin: pwm0-pin { + pins =3D "PD28"; + function =3D "pwm0"; + }; + + /omit-if-no-ref/ + pwm1_pin: pwm1-pin { + pins =3D "PG19"; + function =3D "pwm1"; + }; + + /omit-if-no-ref/ + pwm2_pin: pwm2-pin { + pins =3D "PH2"; + function =3D "pwm2"; + }; + + /omit-if-no-ref/ + pwm3_pin: pwm3-pin { + pins =3D "PH0"; + function =3D "pwm3"; + }; + + /omit-if-no-ref/ + pwm4_pin: pwm4-pin { + pins =3D "PI14"; + function =3D "pwm4"; + }; + + /omit-if-no-ref/ + pwm5_pin: pwm5-pin { + pins =3D "PA12"; + function =3D "pwm5"; + }; + /omit-if-no-ref/ spi0_pins: spi0-pins { pins =3D "PC0", "PC2", "PC4"; --=20 2.47.3