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On Stratix10 and Agilex7, the SDM accesses a reserved buffer located in the first 32 MB of DDR, which starts at physical address 0x0. Agilex5 differs in that DDR begins at 0x8000_0000. Because the SDM address bus is limited to 24 bits, it can only reach the 0=E2=80=93512 MB range and theref= ore cannot directly access DDR on Agilex5. Agilex5 platforms rely on SMMU translation to make DDR reachable to the SDM. This patch enables SMMU usage when the driver is probed with the new `"intel,agilex5-svc"` compatible. A carveout IOVA domain is created, and allocated buffers are mapped through the SMMU so that the SDM can access them via an IOVA that falls within its accessible range. Signed-off-by: Adrian Ng Ho Yin --- drivers/firmware/stratix10-svc.c | 160 ++++++++++++++++++++++++++++--- 1 file changed, 146 insertions(+), 14 deletions(-) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-= svc.c index dbed404a71fc..c20afb666646 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include #include #include @@ -36,12 +38,24 @@ * FPGA_CONFIG_STATUS_TIMEOUT_SEC - poll the FPGA configuration status, * service layer will return error to FPGA manager when timeout occurs, * timeout is set to 30 seconds (30 * 1000) at Intel Stratix10 SoC. + * + * IOMMU_LIMIT_ADDR - Define the maximum addressable range that can be + * accessed by the Secure Device Manager(SDM). + * + * IOMMU_STARTING_ADDR - Define the starting address that can be accessed + * by the Secure Device Manager(SDM). + * + * AGILEX5_SDM_DMA_ADDR_OFFSET - Define the starting address of the DDR + * memory for Agilex5. */ #define SVC_NUM_DATA_IN_FIFO 32 #define SVC_NUM_CHANNEL 4 #define FPGA_CONFIG_DATA_CLAIM_TIMEOUT_MS 200 #define FPGA_CONFIG_STATUS_TIMEOUT_SEC 30 -#define BYTE_TO_WORD_SIZE 4 +#define BYTE_TO_WORD_SIZE 4 +#define IOMMU_LIMIT_ADDR 0x20000000 +#define IOMMU_STARTING_ADDR 0x0 +#define AGILEX5_SDM_DMA_ADDR_OFFSET 0x80000000 =20 /* stratix10 service layer clients */ #define STRATIX10_RSU "stratix10-rsu" @@ -258,6 +272,10 @@ struct stratix10_async_ctrl { * @invoke_fn: function to issue secure monitor call or hypervisor call * @svc: manages the list of client svc drivers * @actrl: async control structure + * @domain: IOMMU domain for service controller + * @is_smmu_enabled: Boolean flag IOMMU enablement + * @sdm_dma_addr_offset: Address offset sent to SDM for DMA ops + * @carveout: IOVA carveout for IOVA address allocation * * This struct is used to create communication channels for service client= s, to * handle secure monitor or hypervisor call. @@ -276,6 +294,14 @@ struct stratix10_svc_controller { svc_invoke_fn *invoke_fn; struct stratix10_svc *svc; struct stratix10_async_ctrl actrl; + struct iommu_domain *domain; + bool is_smmu_enabled; + dma_addr_t sdm_dma_addr_offset; + struct { + struct iova_domain domain; + unsigned long shift; + unsigned long limit; + } carveout; }; =20 /** @@ -1727,6 +1753,14 @@ int stratix10_svc_send(struct stratix10_svc_chan *ch= an, void *msg) if (p_mem->vaddr =3D=3D p_msg->payload) { p_data->paddr =3D p_mem->paddr; p_data->size =3D p_msg->payload_length; + /* ATF have addr range check for to ensure data is + * within actual physical address range of DDR. Adding + * offset which will be stripped off by ATF prior to + * sending to SDM. + */ + if (p_msg->command =3D=3D COMMAND_RECONFIG_DATA_SUBMIT && + chan->ctrl->is_smmu_enabled) + p_data->paddr +=3D chan->ctrl->sdm_dma_addr_offset; break; } if (p_msg->payload_output) { @@ -1796,25 +1830,62 @@ void *stratix10_svc_allocate_memory(struct stratix1= 0_svc_chan *chan, size_t size) { struct stratix10_svc_data_mem *pmem; - unsigned long va; + unsigned long va_gen_pool; phys_addr_t pa; struct gen_pool *genpool =3D chan->ctrl->genpool; - size_t s =3D roundup(size, 1 << genpool->min_alloc_order); + size_t s; + void *va; + int ret; + struct iova *alloc; + dma_addr_t dma_addr; =20 pmem =3D devm_kzalloc(chan->ctrl->dev, sizeof(*pmem), GFP_KERNEL); if (!pmem) return ERR_PTR(-ENOMEM); =20 guard(mutex)(&svc_mem_lock); - va =3D gen_pool_alloc(genpool, s); - if (!va) - return ERR_PTR(-ENOMEM); + if (chan->ctrl->is_smmu_enabled) { + s =3D PAGE_ALIGN(size); + va =3D (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO | __GFP_DMA, get= _order(s)); + if (!va) { + pr_debug("%s get_free_pages_failes\n", __func__); + return ERR_PTR(-ENOMEM); + } =20 - memset((void *)va, 0, s); - pa =3D gen_pool_virt_to_phys(genpool, va); + alloc =3D alloc_iova(&chan->ctrl->carveout.domain, + s >> chan->ctrl->carveout.shift, + chan->ctrl->carveout.limit >> chan->ctrl->carveout.shift, + true); + + dma_addr =3D iova_dma_addr(&chan->ctrl->carveout.domain, alloc); + + ret =3D iommu_map(chan->ctrl->domain, dma_addr, virt_to_phys(va), + s, IOMMU_READ | IOMMU_WRITE | IOMMU_MMIO | IOMMU_CACHE, + GFP_KERNEL); + if (ret < 0) { + pr_debug("%s IOMMU map failed\n", __func__); + free_iova(&chan->ctrl->carveout.domain, + iova_pfn(&chan->ctrl->carveout.domain, + dma_addr)); + free_pages((unsigned long)va, get_order(size)); + return ERR_PTR(-ENOMEM); + } + + pmem->paddr =3D dma_addr; + } else { + s =3D roundup(size, 1 << genpool->min_alloc_order); + va_gen_pool =3D gen_pool_alloc(genpool, s); + if (!va_gen_pool) + return ERR_PTR(-ENOMEM); + + va =3D (void *)va_gen_pool; + + memset((void *)va, 0, s); + pa =3D gen_pool_virt_to_phys(genpool, va_gen_pool); + pmem->paddr =3D pa; + } =20 - pmem->vaddr =3D (void *)va; - pmem->paddr =3D pa; + pmem->vaddr =3D va; pmem->size =3D s; list_add_tail(&pmem->node, &svc_data_mem); pr_debug("%s: va=3D%p, pa=3D0x%016x\n", __func__, @@ -1838,10 +1909,17 @@ void stratix10_svc_free_memory(struct stratix10_svc= _chan *chan, void *kaddr) =20 list_for_each_entry(pmem, &svc_data_mem, node) if (pmem->vaddr =3D=3D kaddr) { - gen_pool_free(chan->ctrl->genpool, - (unsigned long)kaddr, pmem->size); - pmem->vaddr =3D NULL; - list_del(&pmem->node); + if (chan->ctrl->is_smmu_enabled) { + iommu_unmap(chan->ctrl->domain, pmem->paddr, pmem->size); + free_iova(&chan->ctrl->carveout.domain, + iova_pfn(&chan->ctrl->carveout.domain, + pmem->paddr)); + free_pages((unsigned long)pmem->vaddr, get_order(pmem->size)); + } else { + gen_pool_free(chan->ctrl->genpool, + (unsigned long)kaddr, pmem->size); + pmem->vaddr =3D NULL; + } return; } =20 @@ -1852,6 +1930,7 @@ EXPORT_SYMBOL_GPL(stratix10_svc_free_memory); static const struct of_device_id stratix10_svc_drv_match[] =3D { {.compatible =3D "intel,stratix10-svc"}, {.compatible =3D "intel,agilex-svc"}, + {.compatible =3D "intel,agilex5-svc"}, {}, }; =20 @@ -1863,10 +1942,12 @@ static int stratix10_svc_drv_probe(struct platform_= device *pdev) struct gen_pool *genpool; struct stratix10_svc_sh_memory *sh_memory; struct stratix10_svc *svc; + struct device_node *node =3D pdev->dev.of_node; =20 svc_invoke_fn *invoke_fn; size_t fifo_size; int ret; + unsigned long order; =20 /* get SMC or HVC function */ invoke_fn =3D get_invoke_func(dev); @@ -1907,8 +1988,52 @@ static int stratix10_svc_drv_probe(struct platform_d= evice *pdev) controller->genpool =3D genpool; controller->task =3D NULL; controller->invoke_fn =3D invoke_fn; + controller->is_smmu_enabled =3D false; + controller->sdm_dma_addr_offset =3D 0x0; init_completion(&controller->complete_status); =20 + if (of_device_is_compatible(node, "intel,agilex5-svc")) { + if (device_iommu_mapped(&pdev->dev)) { + controller->is_smmu_enabled =3D true; + controller->sdm_dma_addr_offset =3D AGILEX5_SDM_DMA_ADDR_OFFSET; + pr_debug("Intel Service Layer Driver: IOMMU Present\n"); + controller->domain =3D iommu_get_dma_domain(dev); + + if (!controller->domain) { + pr_warn("Intel Service Layer Driver: Error IOMMU domain\n"); + ret =3D -ENODEV; + goto err_destroy_pool; + } else { + ret =3D iova_cache_get(); + if (ret < 0) { + pr_warn("Intel Service Layer Driver: IOVA cache failed\n"); + iommu_domain_free(controller->domain); + ret =3D -ENODEV; + goto err_destroy_pool; + } + ret =3D iommu_attach_device(controller->domain, dev); + if (ret) { + pr_warn("Intel Service Layer Driver: Error IOMMU attach failed\n"); + iova_cache_put(); + iommu_domain_free(controller->domain); + ret =3D -ENODEV; + goto err_destroy_pool; + } + } + + order =3D __ffs(controller->domain->pgsize_bitmap); + init_iova_domain(&controller->carveout.domain, 1UL << order, + IOMMU_STARTING_ADDR); + + controller->carveout.shift =3D iova_shift(&controller->carveout.domain); + controller->carveout.limit =3D IOMMU_LIMIT_ADDR - PAGE_SIZE; + } else { + pr_warn("Intel Service Layer Driver: IOMMU Not Present\n"); + ret =3D -ENODEV; + goto err_destroy_pool; + } + } + ret =3D stratix10_svc_async_init(controller); if (ret) { dev_dbg(dev, "Intel Service Layer Driver: Error on stratix10_svc_async_i= nit %d\n", @@ -2011,6 +2136,13 @@ static void stratix10_svc_drv_remove(struct platform= _device *pdev) =20 of_platform_depopulate(ctrl->dev); =20 + if (ctrl->domain) { + put_iova_domain(&ctrl->carveout.domain); + iova_cache_put(); + iommu_detach_device(ctrl->domain, &pdev->dev); + iommu_domain_free(ctrl->domain); + } + platform_device_unregister(svc->intel_svc_fcs); platform_device_unregister(svc->stratix10_svc_rsu); =20 --=20 2.49.GIT From nobody Thu Dec 18 23:28:19 2025 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010025.outbound.protection.outlook.com [52.101.46.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9973E2BEFE8; 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charset="utf-8" From: Adrian Ng Ho Yin Agilex5 platforms require SMMU translation for FPGA configuration buffers, but the Stratix10 FPGA manager previously assumed direct physical addressing, causing reconfiguration failures when SMMU was enabled. This patch adds SMMU-aware DMA mapping and unmapping of service-layer buffers and introduces a dma_addr field to track mapped addresses. Buffers are also allocated once at probe() instead of per transfer, reducing IOMMU overhead and avoiding timeout issues on Agilex5. These updates enable reliable configuration on Agilex5 while preserving behaviour on Stratix10 and Agilex7. Signed-off-by: Adrian Ng Ho Yin --- drivers/fpga/stratix10-soc.c | 67 +++++++++++++++++++++++++----------- 1 file changed, 46 insertions(+), 21 deletions(-) diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c index 0a295ccf1644..e5128ede8fa6 100644 --- a/drivers/fpga/stratix10-soc.c +++ b/drivers/fpga/stratix10-soc.c @@ -5,6 +5,7 @@ * Copyright (C) 2018 Intel Corporation */ #include +#include #include #include #include @@ -32,6 +33,7 @@ */ struct s10_svc_buf { char *buf; + dma_addr_t dma_addr; unsigned long lock; }; =20 @@ -41,6 +43,7 @@ struct s10_priv { struct completion status_return_completion; struct s10_svc_buf svc_bufs[NUM_SVC_BUFS]; unsigned long status; + bool is_smmu_enabled; }; =20 static int s10_svc_send_msg(struct s10_priv *priv, @@ -94,16 +97,16 @@ static bool s10_free_buffers(struct fpga_manager *mgr) } =20 /* - * Returns count of how many buffers are not in use. + * Returns count of how many buffers are not in locked state. */ -static uint s10_free_buffer_count(struct fpga_manager *mgr) +static uint s10_get_unlocked_buffer_count(struct fpga_manager *mgr) { struct s10_priv *priv =3D mgr->priv; uint num_free =3D 0; uint i; =20 for (i =3D 0; i < NUM_SVC_BUFS; i++) - if (!priv->svc_bufs[i].buf) + if (!priv->svc_bufs[i].lock) num_free++; =20 return num_free; @@ -126,6 +129,10 @@ static void s10_unlock_bufs(struct s10_priv *priv, voi= d *kaddr) =20 for (i =3D 0; i < NUM_SVC_BUFS; i++) if (priv->svc_bufs[i].buf =3D=3D kaddr) { + if (priv->is_smmu_enabled) + dma_unmap_single(priv->client.dev, + priv->svc_bufs[i].dma_addr, + SVC_BUF_SIZE, DMA_TO_DEVICE); clear_bit_unlock(SVC_BUF_LOCK, &priv->svc_bufs[i].lock); return; @@ -179,7 +186,6 @@ static int s10_ops_write_init(struct fpga_manager *mgr, struct s10_priv *priv =3D mgr->priv; struct device *dev =3D priv->client.dev; struct stratix10_svc_command_config_type ctype; - char *kbuf; uint i; int ret; =20 @@ -211,18 +217,9 @@ static int s10_ops_write_init(struct fpga_manager *mgr, goto init_done; } =20 - /* Allocate buffers from the service layer's pool. */ - for (i =3D 0; i < NUM_SVC_BUFS; i++) { - kbuf =3D stratix10_svc_allocate_memory(priv->chan, SVC_BUF_SIZE); - if (IS_ERR(kbuf)) { - s10_free_buffers(mgr); - ret =3D PTR_ERR(kbuf); - goto init_done; - } - - priv->svc_bufs[i].buf =3D kbuf; + /* Init buffer lock */ + for (i =3D 0; i < NUM_SVC_BUFS; i++) priv->svc_bufs[i].lock =3D 0; - } =20 init_done: stratix10_svc_done(priv->chan); @@ -259,6 +256,10 @@ static int s10_send_buf(struct fpga_manager *mgr, cons= t char *buf, size_t count) =20 svc_buf =3D priv->svc_bufs[i].buf; memcpy(svc_buf, buf, xfer_sz); + if (priv->is_smmu_enabled) + priv->svc_bufs[i].dma_addr =3D dma_map_single(dev, svc_buf, + SVC_BUF_SIZE, + DMA_TO_DEVICE); ret =3D s10_svc_send_msg(priv, COMMAND_RECONFIG_DATA_SUBMIT, svc_buf, xfer_sz); if (ret < 0) { @@ -288,7 +289,7 @@ static int s10_ops_write(struct fpga_manager *mgr, cons= t char *buf, * Loop waiting for buffers to be returned. When a buffer is returned, * reuse it to send more data or free if if all data has been sent. */ - while (count > 0 || s10_free_buffer_count(mgr) !=3D NUM_SVC_BUFS) { + while (true) { reinit_completion(&priv->status_return_completion); =20 if (count > 0) { @@ -299,7 +300,7 @@ static int s10_ops_write(struct fpga_manager *mgr, cons= t char *buf, count -=3D sent; buf +=3D sent; } else { - if (s10_free_buffers(mgr)) + if (s10_get_unlocked_buffer_count(mgr) =3D=3D NUM_SVC_BUFS) return 0; =20 ret =3D s10_svc_send_msg( @@ -339,9 +340,6 @@ static int s10_ops_write(struct fpga_manager *mgr, cons= t char *buf, } } =20 - if (!s10_free_buffers(mgr)) - dev_err(dev, "%s not all buffers were freed\n", __func__); - return ret; } =20 @@ -400,7 +398,9 @@ static int s10_probe(struct platform_device *pdev) struct device *dev =3D &pdev->dev; struct s10_priv *priv; struct fpga_manager *mgr; - int ret; + int ret, i; + struct device_node *node =3D pdev->dev.of_node; + char *kbuf; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -409,6 +409,10 @@ static int s10_probe(struct platform_device *pdev) priv->client.dev =3D dev; priv->client.receive_cb =3D s10_receive_callback; priv->client.priv =3D priv; + priv->is_smmu_enabled =3D false; + + if (of_device_is_compatible(node, "intel,agilex5-soc-fpga-mgr")) + priv->is_smmu_enabled =3D true; =20 priv->chan =3D stratix10_svc_request_channel_byname(&priv->client, SVC_CLIENT_FPGA); @@ -428,6 +432,19 @@ static int s10_probe(struct platform_device *pdev) goto probe_err; } =20 + /* Allocate buffers from the service layer's pool. */ + for (i =3D 0; i < NUM_SVC_BUFS; i++) { + kbuf =3D stratix10_svc_allocate_memory(priv->chan, SVC_BUF_SIZE); + if (IS_ERR(kbuf)) { + s10_free_buffers(mgr); + ret =3D PTR_ERR(kbuf); + goto probe_err; + } + + priv->svc_bufs[i].buf =3D kbuf; + priv->svc_bufs[i].lock =3D 0; + } + platform_set_drvdata(pdev, mgr); return 0; =20 @@ -440,6 +457,13 @@ static void s10_remove(struct platform_device *pdev) { struct fpga_manager *mgr =3D platform_get_drvdata(pdev); struct s10_priv *priv =3D mgr->priv; + int i; + + for (i =3D 0; i < NUM_SVC_BUFS; i++) { + if (priv->svc_bufs[i].buf) + stratix10_svc_free_memory(priv->chan, + priv->svc_bufs[i].buf); + } =20 fpga_mgr_unregister(mgr); stratix10_svc_free_channel(priv->chan); @@ -448,6 +472,7 @@ static void s10_remove(struct platform_device *pdev) static const struct of_device_id s10_of_match[] =3D { {.compatible =3D "intel,stratix10-soc-fpga-mgr"}, {.compatible =3D "intel,agilex-soc-fpga-mgr"}, + {.compatible =3D "intel,agilex5-soc-fpga-mgr"}, {}, }; =20 --=20 2.49.GIT