From nobody Thu Dec 18 23:21:29 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38ECE1A239A; Wed, 17 Dec 2025 00:23:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765931030; cv=none; b=ZsVhC8uPV+jR/Wf2o6+e877JnLrnb//nJyhs2oQDi/5v1BaGlT0BRc4fHD9C4XudtznGOfuFsTi7TTRTaEVGK0C4/hn9/7kKtQcBTLM6eduDfbM/+90/JvRUMVCv3QzQEuukooq6zlcpGsKFUOJlUI0zapfq6YIoQZdeQpH6ByM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765931030; c=relaxed/simple; bh=fwT3FfJe5cZVbh12Zu6qCiTMEbUhXFs2R7qaaACn0v0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=E2KvRIm+cN9/OIT8Fq5k9loRJ21zeinNzX65zGU4hN1TP8VhXnJM+AMzpjcMy2jBBxj05o2YwYe7NGLaRGQm82b59LqvwZpTYfNVOC2royTtGSZfGl2LIFr2IPGKVHDVT5Ko4iuDkfOyivI0fwFsFSjuLAIXtIKLTzqNpEr1DPA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hIHSh90J; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hIHSh90J" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765931028; x=1797467028; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=fwT3FfJe5cZVbh12Zu6qCiTMEbUhXFs2R7qaaACn0v0=; b=hIHSh90JcH1JA6m8H5SD9/UOW2QqTm3pmKjNZJdy8QveJqhWznqXaAB8 3VEKpadlWOzed2+d6pY49yWZFMQ0tYqIEbyoxtcSrQpeRf1cDfbSdoEll 1hpGho+tnsjOQWRfMcMG+V1/tM53OIvoEYybe1UttEM6x9cptB/+272/L 1hrzIW6md5v/0E/n06PX5jVJRgAX0qxY9vl2brGftPitnwHOWzZfIz14V tSbkfg/xVjU/BmnQ3JGMshC0eIHJhcaac4GbjXmcthCetUhviz1HPBT05 Uf1/h5acwbPDzfs8C9nSzvzcZMlGzrABkHGhfMX0Ioybo7/gH+J1VuzoJ Q==; X-CSE-ConnectionGUID: kmWUneiESvG6R2RaPfJ/gw== X-CSE-MsgGUID: 9HmW45Q0Qg+0nJBmVLvi8w== X-IronPort-AV: E=McAfee;i="6800,10657,11644"; a="79228267" X-IronPort-AV: E=Sophos;i="6.21,154,1763452800"; d="scan'208";a="79228267" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2025 16:23:47 -0800 X-CSE-ConnectionGUID: i/xaGfCPQPKtKzyacYqVbw== X-CSE-MsgGUID: VL0Onb8PS2uklqLtuucRfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,154,1763452800"; d="scan'208";a="228858106" Received: from sghuge-mobl2.amr.corp.intel.com (HELO xpardee-desk.lan) ([10.125.110.225]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2025 16:23:47 -0800 From: Xi Pardee To: xi.pardee@linux.intel.com, irenic.rajneesh@gmail.com, david.e.box@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 1/3] platform/x86/intel/pmc: Change LPM mode fields to u8 Date: Tue, 16 Dec 2025 16:23:38 -0800 Message-ID: <20251217002343.2289577-2-xi.pardee@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251217002343.2289577-1-xi.pardee@linux.intel.com> References: <20251217002343.2289577-1-xi.pardee@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Change the datatypes pf num_lpm_modes and lpm_en_modes[] from int to u8. The u8 type is more appropriate and improves the readability and maintainability of the code. Signed-off-by: Xi Pardee --- drivers/platform/x86/intel/pmc/core.c | 18 ++++++++++-------- drivers/platform/x86/intel/pmc/core.h | 4 ++-- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/i= ntel/pmc/core.c index 7d7ae8a40b0ec..3e916228e7ed2 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -779,7 +779,7 @@ static int pmc_core_substate_res_show(struct seq_file *= s, void *unused) struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; const int lpm_adj_x2 =3D pmc->map->lpm_res_counter_step_x2; u32 offset =3D pmc->map->lpm_residency_offset; - int mode; + u8 mode; =20 seq_printf(s, "%-10s %-15s\n", "Substate", "Residency"); =20 @@ -838,7 +838,7 @@ static void pmc_core_substate_req_header_show(struct se= q_file *s, int pmc_index, enum header_type type) { struct pmc_dev *pmcdev =3D s->private; - int mode; + u8 mode; =20 seq_printf(s, "%40s |", "Element"); pmc_for_each_mode(mode, pmcdev) @@ -880,7 +880,7 @@ static int pmc_core_substate_blk_req_show(struct seq_fi= le *s, void *unused) const struct pmc_bit_map *map; =20 for (map =3D maps[r_idx]; map->name; map++) { - int mode; + u8 mode; =20 if (!map->blk) continue; @@ -953,7 +953,8 @@ static int pmc_core_substate_req_regs_show(struct seq_f= ile *s, void *unused) u32 lpm_status; u32 lpm_status_live; const struct pmc_bit_map *map; - int mode, i, len =3D 32; + int i, len =3D 32; + u8 mode; =20 /* * Capture the requirements and create a mask so that we only @@ -1065,7 +1066,7 @@ static int pmc_core_lpm_latch_mode_show(struct seq_fi= le *s, void *unused) struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; bool c10; u32 reg; - int mode; + u8 mode; =20 reg =3D pmc_core_reg_read(pmc, pmc->map->lpm_sts_latch_en_offset); if (reg & LPM_STS_LATCH_MODE) { @@ -1097,8 +1098,9 @@ static ssize_t pmc_core_lpm_latch_mode_write(struct f= ile *file, struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; bool clear =3D false, c10 =3D false; unsigned char buf[8]; - int m, mode; + int mode; u32 reg; + u8 m; =20 if (count > sizeof(buf) - 1) return -EINVAL; @@ -1490,8 +1492,8 @@ int pmc_core_pmt_get_lpm_req(struct pmc_dev *pmcdev, = struct pmc *pmc, struct tel { const u8 *lpm_indices; int num_maps, mode_offset =3D 0; - int ret, mode; - int lpm_size; + int ret, lpm_size; + u8 mode; =20 lpm_indices =3D pmc->map->lpm_reg_index; num_maps =3D pmc->map->lpm_num_maps; diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/i= ntel/pmc/core.h index 272fb4f57f346..ead2f33ed3ed5 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -462,8 +462,8 @@ struct pmc_dev { struct mutex lock; /* generic mutex lock for PMC Core */ =20 u64 s0ix_counter; - int num_lpm_modes; - int lpm_en_modes[LPM_MAX_NUM_MODES]; + u8 num_lpm_modes; + u8 lpm_en_modes[LPM_MAX_NUM_MODES]; void (*suspend)(struct pmc_dev *pmcdev); int (*resume)(struct pmc_dev *pmcdev); =20 --=20 2.43.0 From nobody Thu Dec 18 23:21:29 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BCBC1C3C1F; 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a="79228271" X-IronPort-AV: E=Sophos;i="6.21,154,1763452800"; d="scan'208";a="79228271" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2025 16:23:47 -0800 X-CSE-ConnectionGUID: c0J2OKwnR2+uB+171nS1ZQ== X-CSE-MsgGUID: d763PR6GQi604ItwKIRnWA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,154,1763452800"; d="scan'208";a="228858108" Received: from sghuge-mobl2.amr.corp.intel.com (HELO xpardee-desk.lan) ([10.125.110.225]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2025 16:23:47 -0800 From: Xi Pardee To: xi.pardee@linux.intel.com, irenic.rajneesh@gmail.com, david.e.box@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 2/3] platform/x86/intel/pmc: Move LPM mode attributes to PMC Date: Tue, 16 Dec 2025 16:23:39 -0800 Message-ID: <20251217002343.2289577-3-xi.pardee@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251217002343.2289577-1-xi.pardee@linux.intel.com> References: <20251217002343.2289577-1-xi.pardee@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move LPM modes attributes from the pmc_dev to the pmc structure. LPM modes are PMC-specific and should be stored within the pmc structure. After the change, LPM mode information will be retrieved and stored per PMC. The substate_requirements attribute in debugfs will display the requirements for each enabled LPM substate. Signed-off-by: Xi Pardee --- drivers/platform/x86/intel/pmc/core.c | 39 ++++++++++++++++++--------- drivers/platform/x86/intel/pmc/core.h | 15 +++++------ 2 files changed, 34 insertions(+), 20 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/i= ntel/pmc/core.c index 3e916228e7ed2..25f77a9dc42c5 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -783,7 +783,7 @@ static int pmc_core_substate_res_show(struct seq_file *= s, void *unused) =20 seq_printf(s, "%-10s %-15s\n", "Substate", "Residency"); =20 - pmc_for_each_mode(mode, pmcdev) { + pmc_for_each_mode(mode, pmc) { seq_printf(s, "%-10s %-15llu\n", pmc_lpm_modes[mode], adjust_lpm_residency(pmc, offset + (4 * mode), lpm_adj_x2)); } @@ -838,10 +838,11 @@ static void pmc_core_substate_req_header_show(struct = seq_file *s, int pmc_index, enum header_type type) { struct pmc_dev *pmcdev =3D s->private; + struct pmc *pmc =3D pmcdev->pmcs[pmc_index]; u8 mode; =20 seq_printf(s, "%40s |", "Element"); - pmc_for_each_mode(mode, pmcdev) + pmc_for_each_mode(mode, pmc) seq_printf(s, " %9s |", pmc_lpm_modes[mode]); =20 if (type =3D=3D HEADER_STATUS) { @@ -887,7 +888,7 @@ static int pmc_core_substate_blk_req_show(struct seq_fi= le *s, void *unused) =20 counter =3D pmc_core_reg_read(pmc, offset); seq_printf(s, "pmc%u: %34s |", pmc_idx, map->name); - pmc_for_each_mode(mode, pmcdev) { + pmc_for_each_mode(mode, pmc) { bool required =3D *lpm_req_regs & BIT(mode); =20 seq_printf(s, " %9s |", required ? "Required" : " "); @@ -961,7 +962,7 @@ static int pmc_core_substate_req_regs_show(struct seq_f= ile *s, void *unused) * show an element if it's required for at least one of the * enabled low power modes */ - pmc_for_each_mode(mode, pmcdev) + pmc_for_each_mode(mode, pmc) req_mask |=3D lpm_req_regs[mp + (mode * num_maps)]; =20 /* Get the last latched status for this map */ @@ -987,7 +988,7 @@ static int pmc_core_substate_req_regs_show(struct seq_f= ile *s, void *unused) seq_printf(s, "pmc%d: %34s |", pmc_idx, map[i].name); =20 /* Loop over the enabled states and display if required */ - pmc_for_each_mode(mode, pmcdev) { + pmc_for_each_mode(mode, pmc) { bool required =3D lpm_req_regs[mp + (mode * num_maps)] & bit_mask; seq_printf(s, " %9s |", required ? "Required" : " "); @@ -1077,7 +1078,7 @@ static int pmc_core_lpm_latch_mode_show(struct seq_fi= le *s, void *unused) c10 =3D true; } =20 - pmc_for_each_mode(mode, pmcdev) { + pmc_for_each_mode(mode, pmc) { if ((BIT(mode) & reg) && !c10) seq_printf(s, " [%s]", pmc_lpm_modes[mode]); else @@ -1117,7 +1118,7 @@ static ssize_t pmc_core_lpm_latch_mode_write(struct f= ile *file, mode =3D sysfs_match_string(pmc_lpm_modes, buf); =20 /* Check string matches enabled mode */ - pmc_for_each_mode(m, pmcdev) + pmc_for_each_mode(m, pmc) if (mode =3D=3D m) break; =20 @@ -1213,9 +1214,8 @@ static bool pmc_core_pri_verify(u32 lpm_pri, u8 *mode= _order) return true; } =20 -void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev) +static void pmc_core_pmc_get_low_power_modes(struct pmc_dev *pmcdev, struc= t pmc *pmc) { - struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; u8 pri_order[LPM_MAX_NUM_MODES] =3D LPM_DEFAULT_PRI; u8 mode_order[LPM_MAX_NUM_MODES]; u32 lpm_pri; @@ -1232,7 +1232,7 @@ void pmc_core_get_low_power_modes(struct pmc_dev *pmc= dev) * Lower byte is enough to cover the number of lpm modes for all * platforms and hence mask the upper 3 bytes. */ - pmcdev->num_lpm_modes =3D hweight32(lpm_en & 0xFF); + pmc->num_lpm_modes =3D hweight32(lpm_en & 0xFF); =20 /* Read 32 bit LPM_PRI register */ lpm_pri =3D pmc_core_reg_read(pmc, pmc->map->lpm_priority_offset); @@ -1261,7 +1261,22 @@ void pmc_core_get_low_power_modes(struct pmc_dev *pm= cdev) if (!(BIT(mode) & lpm_en)) continue; =20 - pmcdev->lpm_en_modes[i++] =3D mode; + pmc->lpm_en_modes[i++] =3D mode; + } +} + +static void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev) +{ + unsigned int pmc_idx; + + for (pmc_idx =3D 0; pmc_idx < ARRAY_SIZE(pmcdev->pmcs); ++pmc_idx) { + struct pmc *pmc; + + pmc =3D pmcdev->pmcs[pmc_idx]; + if (!pmc) + continue; + + pmc_core_pmc_get_low_power_modes(pmcdev, pmc); } } =20 @@ -1506,7 +1521,7 @@ int pmc_core_pmt_get_lpm_req(struct pmc_dev *pmcdev, = struct pmc *pmc, struct tel return -ENOMEM; =20 mode_offset =3D LPM_HEADER_OFFSET + LPM_MODE_OFFSET; - pmc_for_each_mode(mode, pmcdev) { + pmc_for_each_mode(mode, pmc) { u32 *req_offset =3D pmc->lpm_req_regs + (mode * num_maps); int m; =20 diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/i= ntel/pmc/core.h index ead2f33ed3ed5..118c8740ad3aa 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -423,6 +423,8 @@ struct pmc_info { * specific attributes * @lpm_req_regs: List of substate requirements * @ltr_ign: Holds LTR ignore data while suspended + * @num_lpm_modes: Count of enabled modes + * @lpm_en_modes: Array of enabled modes from lowest to highest priority * * pmc contains info about one power management controller device. */ @@ -432,6 +434,8 @@ struct pmc { const struct pmc_reg_map *map; u32 *lpm_req_regs; u32 ltr_ign; + u8 num_lpm_modes; + u8 lpm_en_modes[LPM_MAX_NUM_MODES]; }; =20 /** @@ -446,8 +450,6 @@ struct pmc { * @pkgc_res_cnt: Array of PKGC residency counters * @num_of_pkgc: Number of PKGC * @s0ix_counter: S0ix residency (step adjusted) - * @num_lpm_modes: Count of enabled modes - * @lpm_en_modes: Array of enabled modes from lowest to highest priority * @suspend: Function to perform platform specific suspend * @resume: Function to perform platform specific resume * @@ -462,8 +464,6 @@ struct pmc_dev { struct mutex lock; /* generic mutex lock for PMC Core */ =20 u64 s0ix_counter; - u8 num_lpm_modes; - u8 lpm_en_modes[LPM_MAX_NUM_MODES]; void (*suspend)(struct pmc_dev *pmcdev); int (*resume)(struct pmc_dev *pmcdev); =20 @@ -535,7 +535,6 @@ int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u3= 2 value, int ignore); =20 int pmc_core_resume_common(struct pmc_dev *pmcdev); int get_primary_reg_base(struct pmc *pmc); -void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev); void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 *guids); void pmc_core_set_device_d3(unsigned int device); =20 @@ -563,10 +562,10 @@ int pmc_core_pmt_get_blk_sub_req(struct pmc_dev *pmcd= ev, struct pmc *pmc, extern const struct file_operations pmc_core_substate_req_regs_fops; extern const struct file_operations pmc_core_substate_blk_req_fops; =20 -#define pmc_for_each_mode(mode, pmcdev) \ +#define pmc_for_each_mode(mode, pmc) \ for (unsigned int __i =3D 0, __cond; \ - __cond =3D __i < (pmcdev)->num_lpm_modes, \ - __cond && ((mode) =3D (pmcdev)->lpm_en_modes[__i]), \ + __cond =3D __i < (pmc)->num_lpm_modes, \ + __cond && ((mode) =3D (pmc)->lpm_en_modes[__i]), \ __cond; \ __i++) =20 --=20 2.43.0 From nobody Thu Dec 18 23:21:29 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD99C1C84DC; Wed, 17 Dec 2025 00:23:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="79228274" X-IronPort-AV: E=Sophos;i="6.21,154,1763452800"; d="scan'208";a="79228274" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2025 16:23:48 -0800 X-CSE-ConnectionGUID: sOAJaPA3T3KK+tkO8tDtog== X-CSE-MsgGUID: x3MAgS5NTk+FvHkJokSWwg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,154,1763452800"; d="scan'208";a="228858110" Received: from sghuge-mobl2.amr.corp.intel.com (HELO xpardee-desk.lan) ([10.125.110.225]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2025 16:23:48 -0800 From: Xi Pardee To: xi.pardee@linux.intel.com, irenic.rajneesh@gmail.com, david.e.box@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 3/3] platform/x86/intel/pmc: Enable substate residencies for multiple PMCs Date: Tue, 16 Dec 2025 16:23:40 -0800 Message-ID: <20251217002343.2289577-4-xi.pardee@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251217002343.2289577-1-xi.pardee@linux.intel.com> References: <20251217002343.2289577-1-xi.pardee@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable substate residencies support for multiple PMCs. Previously substate residencies were shown only for the primary PMC. This change enables substate residencies for all available PMCs. Signed-off-by: Xi Pardee --- drivers/platform/x86/intel/pmc/core.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/i= ntel/pmc/core.c index 25f77a9dc42c5..1f84d5ef47458 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -776,16 +776,26 @@ static inline u64 adjust_lpm_residency(struct pmc *pm= c, u32 offset, static int pmc_core_substate_res_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev =3D s->private; - struct pmc *pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; - const int lpm_adj_x2 =3D pmc->map->lpm_res_counter_step_x2; - u32 offset =3D pmc->map->lpm_residency_offset; - u8 mode; + unsigned int pmc_idx; + + for (pmc_idx =3D 0; pmc_idx < ARRAY_SIZE(pmcdev->pmcs); ++pmc_idx) { + int lpm_adj_x2; + struct pmc *pmc; + u32 offset; + u8 mode; =20 - seq_printf(s, "%-10s %-15s\n", "Substate", "Residency"); + pmc =3D pmcdev->pmcs[pmc_idx]; + if (!pmc) + continue; =20 - pmc_for_each_mode(mode, pmc) { - seq_printf(s, "%-10s %-15llu\n", pmc_lpm_modes[mode], - adjust_lpm_residency(pmc, offset + (4 * mode), lpm_adj_x2)); + lpm_adj_x2 =3D pmc->map->lpm_res_counter_step_x2; + offset =3D pmc->map->lpm_residency_offset; + + seq_printf(s, "pmc%u %10s %15s\n", pmc_idx, "Substate", "Residency"); + pmc_for_each_mode(mode, pmc) { + seq_printf(s, "%15s %15llu\n", pmc_lpm_modes[mode], + adjust_lpm_residency(pmc, offset + (4 * mode), lpm_adj_x2)); + } } =20 return 0; --=20 2.43.0