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Wed, 17 Dec 2025 06:34:42 -0800 (PST) Received: from hu-spratap-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34cfce5eb5csm2615529a91.0.2025.12.17.06.34.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Dec 2025 06:34:42 -0800 (PST) From: Shivendra Pratap Date: Wed, 17 Dec 2025 20:04:19 +0530 Subject: [PATCH v11 1/3] firmware: qcom_scm: Add API to get waitqueue IRQ info Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-multi_waitq_scm-v11-1-f21e50e792b8@oss.qualcomm.com> References: <20251217-multi_waitq_scm-v11-0-f21e50e792b8@oss.qualcomm.com> In-Reply-To: <20251217-multi_waitq_scm-v11-0-f21e50e792b8@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio Cc: Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Unnathi Chalicheemala , Shivendra Pratap , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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However, DeviceTree uses node name "scm" and this mismatch prevents firmware from correctly identifying waitqueue IRQ information. Waitqueue IRQ is used for signaling between secure and non-secure worlds. To resolve this, introduce qcom_scm_get_waitq_irq() that'll get the hardware IRQ number to be used from firmware instead of relying on data provided by devicetree, thereby bypassing the DeviceTree node name mismatch. This hardware IRQ number is converted to a Linux IRQ number using newly qcom_scm_fill_irq_fwspec_params(). This Linux IRQ number is then supplied to the threaded_irq call. Reviewed-by: Bartosz Golaszewski Signed-off-by: Unnathi Chalicheemala Signed-off-by: Shivendra Pratap Reviewed-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 62 ++++++++++++++++++++++++++++++++++++= +++- drivers/firmware/qcom/qcom_scm.h | 1 + 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 1a6f85e463e06a12814614cea20719c90a371b69..f45dbe5f49ed65f4fffd0748c2e= 3c704dbb9ee0a 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -30,11 +30,18 @@ #include #include =20 +#include + #include "qcom_scm.h" #include "qcom_tzmem.h" =20 static u32 download_mode; =20 +#define GIC_SPI_BASE 32 +#define GIC_MAX_SPI 1019 // SPIs in GICv3 spec range from 32..1019 +#define GIC_ESPI_BASE 4096 +#define GIC_MAX_ESPI 5119 // ESPIs in GICv3 spec range from 4096..5119 + struct qcom_scm { struct device *dev; struct clk *core_clk; @@ -2208,6 +2215,56 @@ bool qcom_scm_is_available(void) } EXPORT_SYMBOL_GPL(qcom_scm_is_available); =20 +static int qcom_scm_fill_irq_fwspec_params(struct irq_fwspec *fwspec, u32 = hwirq) +{ + if (hwirq >=3D GIC_SPI_BASE && hwirq <=3D GIC_MAX_SPI) { + fwspec->param[0] =3D GIC_SPI; + fwspec->param[1] =3D hwirq - GIC_SPI_BASE; + } else if (hwirq >=3D GIC_ESPI_BASE && hwirq <=3D GIC_MAX_ESPI) { + fwspec->param[0] =3D GIC_ESPI; + fwspec->param[1] =3D hwirq - GIC_ESPI_BASE; + } else { + WARN(1, "Unexpected hwirq: %d\n", hwirq); + return -ENXIO; + } + + fwspec->param[2] =3D IRQ_TYPE_EDGE_RISING; + fwspec->param_count =3D 3; + + return 0; +} + +static int qcom_scm_get_waitq_irq(struct qcom_scm *scm) +{ + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_WAITQ, + .cmd =3D QCOM_SCM_WAITQ_GET_INFO, + .owner =3D ARM_SMCCC_OWNER_SIP + }; + struct device_node *parent_irq_node; + struct irq_fwspec fwspec; + struct qcom_scm_res res; + u32 hwirq; + int ret; + + ret =3D qcom_scm_call_atomic(scm->dev, &desc, &res); + if (ret) + return ret; + + hwirq =3D res.result[1] & GENMASK(15, 0); + ret =3D qcom_scm_fill_irq_fwspec_params(&fwspec, hwirq); + if (ret) + return ret; + + parent_irq_node =3D of_irq_find_parent(scm->dev->of_node); + if (!parent_irq_node) + return -ENODEV; + + fwspec.fwnode =3D of_fwnode_handle(parent_irq_node); + + return irq_create_fwspec_mapping(&fwspec); +} + static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) { /* FW currently only supports a single wq_ctx (zero). @@ -2381,7 +2438,10 @@ static int qcom_scm_probe(struct platform_device *pd= ev) return dev_err_probe(scm->dev, PTR_ERR(scm->mempool), "Failed to create the SCM memory pool\n"); =20 - irq =3D platform_get_irq_optional(pdev, 0); + irq =3D qcom_scm_get_waitq_irq(scm); + if (irq < 0) + irq =3D platform_get_irq_optional(pdev, 0); + if (irq < 0) { if (irq !=3D -ENXIO) return irq; diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_= scm.h index a56c8212cc0c41021e5a067d52b7d5dcc49107ea..8b1e2ea18a59ac143907a381b73= 236148bace189 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -152,6 +152,7 @@ int qcom_scm_shm_bridge_enable(struct device *scm_dev); #define QCOM_SCM_SVC_WAITQ 0x24 #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 +#define QCOM_SCM_WAITQ_GET_INFO 0x04 =20 #define QCOM_SCM_SVC_GPU 0x28 #define QCOM_SCM_SVC_GPU_INIT_REGS 0x01 --=20 2.34.1