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Wed, 17 Dec 2025 06:34:42 -0800 (PST) Received: from hu-spratap-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34cfce5eb5csm2615529a91.0.2025.12.17.06.34.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Dec 2025 06:34:42 -0800 (PST) From: Shivendra Pratap Date: Wed, 17 Dec 2025 20:04:19 +0530 Subject: [PATCH v11 1/3] firmware: qcom_scm: Add API to get waitqueue IRQ info Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-multi_waitq_scm-v11-1-f21e50e792b8@oss.qualcomm.com> References: <20251217-multi_waitq_scm-v11-0-f21e50e792b8@oss.qualcomm.com> In-Reply-To: <20251217-multi_waitq_scm-v11-0-f21e50e792b8@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio Cc: Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Unnathi Chalicheemala , Shivendra Pratap , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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However, DeviceTree uses node name "scm" and this mismatch prevents firmware from correctly identifying waitqueue IRQ information. Waitqueue IRQ is used for signaling between secure and non-secure worlds. To resolve this, introduce qcom_scm_get_waitq_irq() that'll get the hardware IRQ number to be used from firmware instead of relying on data provided by devicetree, thereby bypassing the DeviceTree node name mismatch. This hardware IRQ number is converted to a Linux IRQ number using newly qcom_scm_fill_irq_fwspec_params(). This Linux IRQ number is then supplied to the threaded_irq call. Reviewed-by: Bartosz Golaszewski Signed-off-by: Unnathi Chalicheemala Signed-off-by: Shivendra Pratap Reviewed-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 62 ++++++++++++++++++++++++++++++++++++= +++- drivers/firmware/qcom/qcom_scm.h | 1 + 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 1a6f85e463e06a12814614cea20719c90a371b69..f45dbe5f49ed65f4fffd0748c2e= 3c704dbb9ee0a 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -30,11 +30,18 @@ #include #include =20 +#include + #include "qcom_scm.h" #include "qcom_tzmem.h" =20 static u32 download_mode; =20 +#define GIC_SPI_BASE 32 +#define GIC_MAX_SPI 1019 // SPIs in GICv3 spec range from 32..1019 +#define GIC_ESPI_BASE 4096 +#define GIC_MAX_ESPI 5119 // ESPIs in GICv3 spec range from 4096..5119 + struct qcom_scm { struct device *dev; struct clk *core_clk; @@ -2208,6 +2215,56 @@ bool qcom_scm_is_available(void) } EXPORT_SYMBOL_GPL(qcom_scm_is_available); =20 +static int qcom_scm_fill_irq_fwspec_params(struct irq_fwspec *fwspec, u32 = hwirq) +{ + if (hwirq >=3D GIC_SPI_BASE && hwirq <=3D GIC_MAX_SPI) { + fwspec->param[0] =3D GIC_SPI; + fwspec->param[1] =3D hwirq - GIC_SPI_BASE; + } else if (hwirq >=3D GIC_ESPI_BASE && hwirq <=3D GIC_MAX_ESPI) { + fwspec->param[0] =3D GIC_ESPI; + fwspec->param[1] =3D hwirq - GIC_ESPI_BASE; + } else { + WARN(1, "Unexpected hwirq: %d\n", hwirq); + return -ENXIO; + } + + fwspec->param[2] =3D IRQ_TYPE_EDGE_RISING; + fwspec->param_count =3D 3; + + return 0; +} + +static int qcom_scm_get_waitq_irq(struct qcom_scm *scm) +{ + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_WAITQ, + .cmd =3D QCOM_SCM_WAITQ_GET_INFO, + .owner =3D ARM_SMCCC_OWNER_SIP + }; + struct device_node *parent_irq_node; + struct irq_fwspec fwspec; + struct qcom_scm_res res; + u32 hwirq; + int ret; + + ret =3D qcom_scm_call_atomic(scm->dev, &desc, &res); + if (ret) + return ret; + + hwirq =3D res.result[1] & GENMASK(15, 0); + ret =3D qcom_scm_fill_irq_fwspec_params(&fwspec, hwirq); + if (ret) + return ret; + + parent_irq_node =3D of_irq_find_parent(scm->dev->of_node); + if (!parent_irq_node) + return -ENODEV; + + fwspec.fwnode =3D of_fwnode_handle(parent_irq_node); + + return irq_create_fwspec_mapping(&fwspec); +} + static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) { /* FW currently only supports a single wq_ctx (zero). @@ -2381,7 +2438,10 @@ static int qcom_scm_probe(struct platform_device *pd= ev) return dev_err_probe(scm->dev, PTR_ERR(scm->mempool), "Failed to create the SCM memory pool\n"); =20 - irq =3D platform_get_irq_optional(pdev, 0); + irq =3D qcom_scm_get_waitq_irq(scm); + if (irq < 0) + irq =3D platform_get_irq_optional(pdev, 0); + if (irq < 0) { if (irq !=3D -ENXIO) return irq; diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_= scm.h index a56c8212cc0c41021e5a067d52b7d5dcc49107ea..8b1e2ea18a59ac143907a381b73= 236148bace189 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -152,6 +152,7 @@ int qcom_scm_shm_bridge_enable(struct device *scm_dev); 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Multi-waitqueue mechanism is added in firmware to support the case, when multiple VMs make SMC calls or single VM making multiple calls on same CPU. Enhance the driver to support multiple waitqueue when support is present in the firmware. When VMs make a SMC call, firmware allocates a waitqueue context, assuming the SMC call to be a blocking call. The SMC calls that cannot acquire resources, while execution in firmware, are returned to sleep in the calling VM. When the resource becomes available in the firmware, the VM gets notified to wake the sleeping thread and resume SMC call. The current qcom_scm driver supports single waitqueue as the old firmwares support only single waitqueue with waitqueue id zero. Multi-waitqueue mechanism is added in firmware starting SM8650 to support the case when multiple VMs make SMC calls or single VM making multiple calls on same CPU. To enable this support in qcom_scm driver, add support for handling multiple waitqueues. For instance, SM8650 firmware can allocate two such waitq contexts, so the driver needs to implement two waitqueue contexts. For a generalized approach, the number of supported waitqueues can be queried from the firmware using a SMC call. Introduce qcom_scm_query_waitq_count to get the number of waitqueue contexts supported by the firmware and allocate =E2=80=9CN=E2=80=9D unique = waitqueue contexts with a dynamic sized array where each unique wq_ctx is associated with a struct completion variable for easy lookup. Older targets which support only a single waitqueue, may return an error for qcom_scm_query_waitq_count, set the wq_cnt to one for such failures. Reviewed-by: Bartosz Golaszewski Signed-off-by: Unnathi Chalicheemala Signed-off-by: Shivendra Pratap Reviewed-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 72 ++++++++++++++++++++++++++++--------= ---- 1 file changed, 50 insertions(+), 22 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index f45dbe5f49ed65f4fffd0748c2e3c704dbb9ee0a..e16dbf18f731be9b0098dd683f4= 78c8c8fdeaf20 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -48,7 +48,7 @@ struct qcom_scm { struct clk *iface_clk; struct clk *bus_clk; struct icc_path *path; - struct completion waitq_comp; + struct completion *waitq_comps; struct reset_controller_dev reset; =20 /* control access to the interconnect path */ @@ -58,6 +58,7 @@ struct qcom_scm { u64 dload_mode_addr; =20 struct qcom_tzmem_pool *mempool; + unsigned int wq_cnt; }; =20 struct qcom_scm_current_perm_info { @@ -137,6 +138,8 @@ static const u8 qcom_scm_cpu_warm_bits[QCOM_SCM_BOOT_MA= X_CPUS] =3D { #define QCOM_DLOAD_MINIDUMP 2 #define QCOM_DLOAD_BOTHDUMP 3 =20 +#define QCOM_SCM_DEFAULT_WAITQ_COUNT 1 + static const char * const qcom_scm_convention_names[] =3D { [SMC_CONVENTION_UNKNOWN] =3D "unknown", [SMC_CONVENTION_ARM_32] =3D "smc arm 32", @@ -2234,6 +2237,23 @@ static int qcom_scm_fill_irq_fwspec_params(struct ir= q_fwspec *fwspec, u32 hwirq) return 0; } =20 +static int qcom_scm_query_waitq_count(struct qcom_scm *scm) +{ + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_WAITQ, + .cmd =3D QCOM_SCM_WAITQ_GET_INFO, + .owner =3D ARM_SMCCC_OWNER_SIP + }; + struct qcom_scm_res res; + int ret; + + ret =3D qcom_scm_call_atomic(scm->dev, &desc, &res); + if (ret) + return ret; + + return res.result[0] & GENMASK(7, 0); +} + static int qcom_scm_get_waitq_irq(struct qcom_scm *scm) { struct qcom_scm_desc desc =3D { @@ -2265,42 +2285,40 @@ static int qcom_scm_get_waitq_irq(struct qcom_scm *= scm) return irq_create_fwspec_mapping(&fwspec); } =20 -static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) +static struct completion *qcom_scm_get_completion(u32 wq_ctx) { - /* FW currently only supports a single wq_ctx (zero). - * TODO: Update this logic to include dynamic allocation and lookup of - * completion structs when FW supports more wq_ctx values. - */ - if (wq_ctx !=3D 0) { - dev_err(__scm->dev, "Firmware unexpectedly passed non-zero wq_ctx\n"); - return -EINVAL; - } + struct completion *wq; =20 - return 0; + if (WARN_ON_ONCE(wq_ctx >=3D __scm->wq_cnt)) + return ERR_PTR(-EINVAL); + + wq =3D &__scm->waitq_comps[wq_ctx]; + + return wq; } =20 int qcom_scm_wait_for_wq_completion(u32 wq_ctx) { - int ret; + struct completion *wq; =20 - ret =3D qcom_scm_assert_valid_wq_ctx(wq_ctx); - if (ret) - return ret; + wq =3D qcom_scm_get_completion(wq_ctx); + if (IS_ERR(wq)) + return PTR_ERR(wq); =20 - wait_for_completion(&__scm->waitq_comp); + wait_for_completion(wq); =20 return 0; } =20 static int qcom_scm_waitq_wakeup(unsigned int wq_ctx) { - int ret; + struct completion *wq; =20 - ret =3D qcom_scm_assert_valid_wq_ctx(wq_ctx); - if (ret) - return ret; + wq =3D qcom_scm_get_completion(wq_ctx); + if (IS_ERR(wq)) + return PTR_ERR(wq); =20 - complete(&__scm->waitq_comp); + complete(wq); =20 return 0; } @@ -2376,6 +2394,7 @@ static int qcom_scm_probe(struct platform_device *pde= v) struct qcom_tzmem_pool_config pool_config; struct qcom_scm *scm; int irq, ret; + int i; =20 scm =3D devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL); if (!scm) @@ -2386,7 +2405,6 @@ static int qcom_scm_probe(struct platform_device *pde= v) if (ret < 0) return ret; =20 - init_completion(&scm->waitq_comp); mutex_init(&scm->scm_bw_lock); =20 scm->path =3D devm_of_icc_get(&pdev->dev, NULL); @@ -2438,6 +2456,16 @@ static int qcom_scm_probe(struct platform_device *pd= ev) return dev_err_probe(scm->dev, PTR_ERR(scm->mempool), "Failed to create the SCM memory pool\n"); =20 + ret =3D qcom_scm_query_waitq_count(scm); + scm->wq_cnt =3D ret < 0 ? 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In case of an extended wait request by the firmware, any device suspend request, cannot proceed because of the thread stuck in D state. This blocks the device suspend. Replace wait_for_completion() with wait_for_completion_state(..., TASK_IDLE), so that the waiting thread, show up in TASK_IDLE state, instead of TASK_UNINTERRUPTIBLE (D state). This allows the thread to block until completion, without blocking the device suspend. Reviewed-by: Mukesh Ojha Reviewed-by: Bartosz Golaszewski Signed-off-by: Unnathi Chalicheemala Signed-off-by: Shivendra Pratap --- drivers/firmware/qcom/qcom_scm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index e16dbf18f731be9b0098dd683f478c8c8fdeaf20..3d8eee354cad55773d9b827ee8e= 32aab1f192510 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -2305,7 +2305,7 @@ int qcom_scm_wait_for_wq_completion(u32 wq_ctx) if (IS_ERR(wq)) return PTR_ERR(wq); =20 - wait_for_completion(wq); + wait_for_completion_state(wq, TASK_IDLE); =20 return 0; } --=20 2.34.1