From nobody Fri Dec 19 20:11:15 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A69633A9E3; Wed, 17 Dec 2025 17:04:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765991066; cv=pass; b=OdvSNVFZ4tcBo4zXmUujgFm8cBfCx+SZMCRswt7WjUurc5thoPnJWsDK6rqX8SNrW6vp5zMQGzOvrwchVNv1/83W6IMORVE7xIMoE4eG1WlY3mE7ZkVj9tVsBgyj2u0rEuid594eqoW8Xs1MnsjK9BTDNQjmU60TMVTjHYSr7c8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765991066; c=relaxed/simple; bh=4sq6E36JCBJ2UveeXTFD78ZCyLlw2rbM4xzZTTVHbHk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=anUC6Tj4ruIKraGf0QQ6HWRhNISveBq3eLv163pJ/hSdVkHJRZXK0/zObp8wAOVauZFz4YGaDbHEjB0CfYc90NjcziSC34fP4gjwQRRUGuRrABGcr0urrh9smqq63Qr46W7686so2XlyM9qINkYhZaq4CMr0QpDtCIbGQDbKhZ0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=TYF0e3zq; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="TYF0e3zq" ARC-Seal: i=1; a=rsa-sha256; t=1765991046; cv=none; d=zohomail.com; s=zohoarc; b=RdZEoObAi69A7BXQH+VVF3hMq4oOW5uPwfCNNqxQkVqeekoWEPWPh/G8o/j18RjeYm2ATJ/8n8QqzPOUhVlrg0hiypKPSBxMXemRLNNPwP0aXjCVVKUYZmbqKfqY3hGrjENjrNWssv5219GNgnNjygnbkwm1ZAN5mxdiLrxijd8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765991046; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=J0hm26JZwx6v0Ry2T0SEUpthc+tXhioEHL+8VAV//SU=; b=msX9GsQspDMB1LSW9AKbYEUdb5PR35fIDUO23uHN7p6vUQRG0r+RpaxgpjsUjf7nUPClpM5cFi5wp3zN1GApfMvYXwDQDBtUlYerTzSmOEKKBukBgEpKJG6Dj9JaFuwTKqIkdTcdS/zajgWrYsD2e4JRWyI6/LWBWq+FhNpxTDA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1765991046; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=J0hm26JZwx6v0Ry2T0SEUpthc+tXhioEHL+8VAV//SU=; b=TYF0e3zqs2OyQJdTA5j8qvuLHjvvlb07BeVcVQWey27yJ4sB2r3uAXdujYuAeZJF pOFIeXuXOQvDDZ4kAJu2E40hTK++vSvcqqaMJyw8Ac8nLL0CbehQSCnovc7ud/SNAuM 5gPhibIl37GtM9bp+JwNupALEiY6YzI/n7Ft5dzQ= Received: by mx.zohomail.com with SMTPS id 1765991044199539.6895741631515; Wed, 17 Dec 2025 09:04:04 -0800 (PST) From: Nicolas Frattaroli Date: Wed, 17 Dec 2025 18:03:27 +0100 Subject: [PATCH 1/4] dt-bindings: gpu: mali-valhall-csf: Add shader-present nvmem cell Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-mt8196-shader-present-v1-1-f6f8f3aa1e93@collabora.com> References: <20251217-mt8196-shader-present-v1-0-f6f8f3aa1e93@collabora.com> In-Reply-To: <20251217-mt8196-shader-present-v1-0-f6f8f3aa1e93@collabora.com> To: Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson Cc: Chen-Yu Tsai , Chia-I Wu , kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 On the MediaTek MT8196 SoC, the bitmask for which shader cores are present and functional is not the one in the Mali GPU's registers, but in an external efuse. Add the nvmem cell properties to describe such a setup, and make them required on MT8196. Signed-off-by: Nicolas Frattaroli --- .../devicetree/bindings/gpu/arm,mali-valhall-csf.yaml | 14 ++++++++++= ++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yam= l b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml index bee9faf1d3f8..8eccd4338a2b 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml @@ -51,6 +51,14 @@ properties: - stacks - const: stacks =20 + nvmem-cells: + items: + - description: bitmask of functional shader cores + + nvmem-cell-names: + items: + - const: shader-present + mali-supply: true =20 operating-points-v2: true @@ -108,6 +116,8 @@ allOf: properties: clocks: minItems: 3 + nvmem-cells: false + nvmem-cell-names: false power-domains: maxItems: 1 power-domain-names: false @@ -133,6 +143,8 @@ allOf: - const: core - const: stacks required: + - nvmem-cells + - nvmem-cell-names - power-domains =20 examples: @@ -179,6 +191,8 @@ examples: , ; interrupt-names =3D "job", "mmu", "gpu"; + nvmem-cells =3D <&shader_present>; + nvmem-cell-names =3D "shader-present"; power-domains =3D <&gpufreq>; }; =20 --=20 2.52.0 From nobody Fri Dec 19 20:11:15 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CAA033A9E3; Wed, 17 Dec 2025 17:04:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765991070; cv=pass; b=gVzXTrAkEik53dpE4w920NSq8jibVcYpdyaoVqR8pC2fjLN6zqEEYc+kfOHsl3GBmpUHgRbm8rznZFNC1D2Ul4pLtLKCaLVVXyFNi+w9B0TDNcqXU61EfQpFrlidb3HgAbt2bIBzofLzgV3OXd6Llxp2XnJp6AkCzVHjRL3kzv8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765991070; c=relaxed/simple; bh=hS/tFjlywumLE5gZvRsnkXZzp5owwt5n7i6XqnXtn8M=; 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Wed, 17 Dec 2025 09:04:09 -0800 (PST) From: Nicolas Frattaroli Date: Wed, 17 Dec 2025 18:03:28 +0100 Subject: [PATCH 2/4] dt-bindings: power: mt8196-gpufreq: Describe nvmem provider ability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-mt8196-shader-present-v1-2-f6f8f3aa1e93@collabora.com> References: <20251217-mt8196-shader-present-v1-0-f6f8f3aa1e93@collabora.com> In-Reply-To: <20251217-mt8196-shader-present-v1-0-f6f8f3aa1e93@collabora.com> To: Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson Cc: Chen-Yu Tsai , Chia-I Wu , kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 On the MediaTek MT8196 SoC, the Mali GPU's "shader_present" hardware register may also include a non-functional shader core, along with the present shader cores. An efuse elsewhere in the SoC provides the shader_present mask with the fused off core omitted. However, the efuse address is not publicly disclosed. What is known though is that the GPUEB MCU reads this efuse, and exposes its contents in the memory it shares with the application processor. We can therefore describe the mediatek,mt8196-gpufreq device as being an nvmem provider for this purpose, as it does provide nvmem access in an indirect way. The shader-present child node is left out of the list of required properties as we may one day be able to describe the actual efuse region this value comes from, so the gpufreq device isn't necessarily the only device that can provide this cell, and implementations shouldn't need to implement this functionality once this is the case. Signed-off-by: Nicolas Frattaroli --- .../devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml | 13 +++++++++= ++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/power/mediatek,mt8196-gpufre= q.yaml b/Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.ya= ml index b9e43abaf8a4..66fc59b3c8b4 100644 --- a/Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml @@ -74,9 +74,18 @@ properties: "#clock-cells": const: 1 =20 + "#nvmem-cell-cells": + const: 0 + "#power-domain-cells": const: 0 =20 + shader-present: + type: object + +dependencies: + shader-present: [ "#nvmem-cell-cells" ] + required: - compatible - reg @@ -113,5 +122,9 @@ examples: "ccf", "fast-dvfs"; memory-region =3D <&gpueb_shared_memory>; #clock-cells =3D <1>; + #nvmem-cell-cells =3D <0>; #power-domain-cells =3D <0>; + + shader-present { + }; }; --=20 2.52.0 From nobody Fri Dec 19 20:11:15 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03D00345CD3; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-mt8196-shader-present-v1-3-f6f8f3aa1e93@collabora.com> References: <20251217-mt8196-shader-present-v1-0-f6f8f3aa1e93@collabora.com> In-Reply-To: <20251217-mt8196-shader-present-v1-0-f6f8f3aa1e93@collabora.com> To: Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson Cc: Chen-Yu Tsai , Chia-I Wu , kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 On some platforms, notably MediaTek MT8196, the shader_present bitmask in the Mali GPU register for it has cores enabled that may be faulty. The true shader_present bitmask is found in an efuse instead. Implement reading shader_present from an nvmem cell if one is present, falling back to the Mali register if it's absent. The error codes are trickled up through to the probe function so that probe deferral works. Signed-off-by: Nicolas Frattaroli Reviewed-by: Boris Brezillon Reviewed-by: Steven Price --- drivers/gpu/drm/panthor/panthor_hw.c | 63 ++++++++++++++++++++++++++++++++= ---- 1 file changed, 57 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor= /panthor_hw.c index 87ebb7ae42c4..eb44c8b108aa 100644 --- a/drivers/gpu/drm/panthor/panthor_hw.c +++ b/drivers/gpu/drm/panthor/panthor_hw.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 or MIT /* Copyright 2025 ARM Limited. All rights reserved. */ =20 +#include #include =20 #include "panthor_device.h" @@ -109,7 +110,52 @@ static char *get_gpu_model_name(struct panthor_device = *ptdev) return "(Unknown Mali GPU)"; } =20 -static void panthor_gpu_info_init(struct panthor_device *ptdev) +static int overload_shader_present(struct panthor_device *ptdev) +{ + struct device *dev =3D ptdev->base.dev; + struct nvmem_cell *cell =3D nvmem_cell_get(dev, "shader-present"); + ssize_t len; + void *buf; + int ret; + + if (IS_ERR(cell)) { + /* On platforms without this cell, use the Mali register */ + if (PTR_ERR(cell) =3D=3D -ENOENT) + return 0; + + return dev_err_probe(dev, PTR_ERR(cell), + "Failed to get shader-present nvmem cell\n"); + } + + buf =3D nvmem_cell_read(cell, &len); + if (IS_ERR(buf)) { + ret =3D dev_err_probe(dev, PTR_ERR(buf), + "Failed to read shader-present nvmem cell\n"); + goto err_put_cell; + } + + if (!len || len > 8) { + ret =3D dev_err_probe(dev, -EINVAL, "shader-present cell can't be length= %ld\n", + len); + goto err_free; + } + + memcpy(&ptdev->gpu_info.shader_present, buf, len); + + kfree(buf); + nvmem_cell_put(cell); + + return 0; + +err_free: + kfree(buf); +err_put_cell: + nvmem_cell_put(cell); + + return ret; +} + +static int panthor_gpu_info_init(struct panthor_device *ptdev) { unsigned int i; =20 @@ -143,13 +189,18 @@ static void panthor_gpu_info_init(struct panthor_devi= ce *ptdev) ptdev->gpu_info.tiler_present =3D gpu_read64(ptdev, GPU_TILER_PRESENT); ptdev->gpu_info.l2_present =3D gpu_read64(ptdev, GPU_L2_PRESENT); } + + return overload_shader_present(ptdev); } =20 -static void panthor_hw_info_init(struct panthor_device *ptdev) +static int panthor_hw_info_init(struct panthor_device *ptdev) { u32 major, minor, status; + int ret; =20 - panthor_gpu_info_init(ptdev); + ret =3D panthor_gpu_info_init(ptdev); + if (ret) + return ret; =20 major =3D GPU_VER_MAJOR(ptdev->gpu_info.gpu_id); minor =3D GPU_VER_MINOR(ptdev->gpu_info.gpu_id); @@ -172,6 +223,8 @@ static void panthor_hw_info_init(struct panthor_device = *ptdev) "shader_present=3D0x%0llx l2_present=3D0x%0llx tiler_present=3D0x%0llx", ptdev->gpu_info.shader_present, ptdev->gpu_info.l2_present, ptdev->gpu_info.tiler_present); + + return 0; } =20 static int panthor_hw_bind_device(struct panthor_device *ptdev) @@ -218,7 +271,5 @@ int panthor_hw_init(struct panthor_device *ptdev) if (ret) return ret; =20 - panthor_hw_info_init(ptdev); - - return 0; + return panthor_hw_info_init(ptdev); } --=20 2.52.0 From nobody Fri Dec 19 20:11:15 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC670346771; Wed, 17 Dec 2025 17:04:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765991080; cv=pass; b=PgiygFKEdhuJXupRX2CngA32srIQUyJO5VcpTuvuuY1tsw6eONqWlMN9oV5V17V+HXJu1ljoCBjxlC13gu+Ad9r93nebWfWoD4+V2ACtFhKHBmOdnhfQQydTOFVfD5aR66qqEgkF3dRMfxvYuiO6c5Li7dX6EqdEhF6ZDkfq/Cc= ARC-Message-Signature: i=2; a=rsa-sha256; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=Cn+wN94dsn6CdLIbCexrwAhvW7xHuDrjgU73wpCpToc=; b=T96gd2KpGXUegdL47pBQjjHHEC1I1xbohrmvj5VPMcTsQwJDmoqRJkph4QxvPssg vihjm/SjXUFHSje5VH3KrKs2ubg5S/m+ywWm1c54bLMhdWdAWfgfrZ/uJl/rIxk6UAC RcQTz79rSYxSWuqZf+HkGbbQVh1dRDluYQVLzVqs= Received: by mx.zohomail.com with SMTPS id 1765991061155339.44972850183456; Wed, 17 Dec 2025 09:04:21 -0800 (PST) From: Nicolas Frattaroli Date: Wed, 17 Dec 2025 18:03:30 +0100 Subject: [PATCH 4/4] pmdomain: mediatek: mtk-mfg: Expose shader_present as nvmem cell Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-mt8196-shader-present-v1-4-f6f8f3aa1e93@collabora.com> References: <20251217-mt8196-shader-present-v1-0-f6f8f3aa1e93@collabora.com> In-Reply-To: <20251217-mt8196-shader-present-v1-0-f6f8f3aa1e93@collabora.com> To: Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson Cc: Chen-Yu Tsai , Chia-I Wu , kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Implement nvmem-provider functionality in mtk-mfg-pmdomain, such that it can expose its GF_REG_SHADER_PRESENT value in the shared memory as an nvmem cell for panthor. Signed-off-by: Nicolas Frattaroli --- drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c | 57 ++++++++++++++++++++++++= ++++ 1 file changed, 57 insertions(+) diff --git a/drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c b/drivers/pmdomai= n/mediatek/mtk-mfg-pmdomain.c index 9bad577b3ae4..725ebc678f1b 100644 --- a/drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c +++ b/drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -872,6 +873,58 @@ static int mtk_mfg_init_clk_provider(struct mtk_mfg *m= fg) return 0; } =20 +static int mtk_mfg_read_nvmem(void *priv, unsigned int offset, void *val, = size_t bytes) +{ + struct mtk_mfg *mfg =3D priv; + u32 *buf =3D val; + + if (bytes !=3D 4) + return -EINVAL; + + if (!mfg->shared_mem) + return -ENODEV; + + if (offset + bytes >=3D mfg->shared_mem_size) + return -EINVAL; + + *buf =3D readl(mfg->shared_mem + offset); + + return 0; +} + +static int mtk_mfg_init_nvmem_provider(struct mtk_mfg *mfg) +{ + struct device *dev =3D &mfg->pdev->dev; + struct nvmem_cell_info cell =3D {}; + struct nvmem_config config =3D {}; + struct nvmem_device *nvdev; + int ret; + + config.reg_read =3D mtk_mfg_read_nvmem; + config.dev =3D dev; + config.read_only =3D true; + config.priv =3D mfg; + config.size =3D 4; + config.word_size =3D 4; + + nvdev =3D devm_nvmem_register(dev, &config); + of_node_put(config.of_node); + if (IS_ERR(nvdev)) + return dev_err_probe(dev, PTR_ERR(nvdev), "Couldn't register nvmem provi= der\n"); + + cell.name =3D "shader-present"; + cell.offset =3D GF_REG_SHADER_PRESENT; + cell.bytes =3D 4; + cell.np =3D of_get_child_by_name(dev->of_node, cell.name); + + ret =3D nvmem_add_one_cell(nvdev, &cell); + /* cell.np purposefully not put as nvmem_add_one_cell does not increase r= efcount */ + if (ret) + return dev_err_probe(dev, ret, "Couldn't add cell %s\n", cell.name); + + return 0; +} + static int mtk_mfg_probe(struct platform_device *pdev) { struct mtk_mfg *mfg; @@ -984,6 +1037,10 @@ static int mtk_mfg_probe(struct platform_device *pdev) if (ret) goto err_power_off; =20 + ret =3D mtk_mfg_init_nvmem_provider(mfg); + if (ret) + goto err_power_off; + ret =3D of_genpd_add_provider_simple(dev->of_node, &mfg->pd); if (ret) { dev_err_probe(dev, ret, "Failed to add pmdomain provider\n"); --=20 2.52.0