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Wed, 17 Dec 2025 02:13:06 -0800 (PST) Received: from hu-msarkar-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7fcbb11ee42sm2290347b3a.43.2025.12.17.02.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Dec 2025 02:13:05 -0800 (PST) From: Mrinmay Sarkar Date: Wed, 17 Dec 2025 15:42:46 +0530 Subject: [PATCH v3 2/2] PCI: qcom-ep: Add support for firmware-managed PCIe Endpoint Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-firmware_managed_ep-v3-2-ff871ba688fb@oss.qualcomm.com> References: <20251217-firmware_managed_ep-v3-0-ff871ba688fb@oss.qualcomm.com> In-Reply-To: <20251217-firmware_managed_ep-v3-0-ff871ba688fb@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Krishna Chaitanya Chundru , quic_vbadigan@quicinc.com, quic_shazhuss@quicinc.com, konrad.dybcio@oss.qualcomm.com, Mrinmay sarkar , Rama Krishna , Ayiluri Naga Rashmi , Nitesh Gupta X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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In these cases, the Linux driver should not perform resource enable or disable operations directly. Additionally, runtime PM support has been enabled to ensure proper power state transitions. This commit introduces a `firmware_managed` flag in the Endpoint configuration structure. When set, the driver skips resource handling and uses generic runtime PM calls to let firmware do resource management. A new compatible string is added for SA8255P platforms where firmware manages resources. Signed-off-by: Mrinmay Sarkar --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 82 +++++++++++++++++++++++----= ---- 1 file changed, 62 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index f1bc0ac81a928b928ab3f8cc7bf82558fc430474..2de8b48511169a9c836828c2286= 0dba45f6c9db8 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -168,11 +168,13 @@ enum qcom_pcie_ep_link_status { * @hdma_support: HDMA support on this SoC * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache = snooping * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check + * @firmware_managed: Set if the Endpoint controller is firmware managed */ struct qcom_pcie_ep_cfg { bool hdma_support; bool override_no_snoop; bool disable_mhi_ram_parity_check; + bool firmware_managed; }; =20 /** @@ -377,10 +379,17 @@ static int qcom_pcie_enable_resources(struct qcom_pci= e_ep *pcie_ep) =20 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) { - icc_set_bw(pcie_ep->icc_mem, 0, 0); - phy_power_off(pcie_ep->phy); - phy_exit(pcie_ep->phy); - clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); + struct device *dev =3D pcie_ep->pci.dev; + int ret; + + pm_runtime_put(dev); + + if (!(pcie_ep->cfg && pcie_ep->cfg->firmware_managed)) { + icc_set_bw(pcie_ep->icc_mem, 0, 0); + phy_power_off(pcie_ep->phy); + phy_exit(pcie_ep->phy); + clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); + } } =20 static int qcom_pcie_perst_deassert(struct dw_pcie *pci) @@ -390,12 +399,22 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *p= ci) u32 val, offset; int ret; =20 - ret =3D qcom_pcie_enable_resources(pcie_ep); - if (ret) { - dev_err(dev, "Failed to enable resources: %d\n", ret); + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable endpoint device: %d\n", ret); return ret; } =20 + /* Enable resources if Endpoint controller is not firmware-managed */ + if (!(pcie_ep->cfg && pcie_ep->cfg->firmware_managed)) { + ret =3D qcom_pcie_enable_resources(pcie_ep); + if (ret) { + dev_err(dev, "Failed to enable resources: %d\n", ret); + pm_runtime_put(dev); + return ret; + } + } + /* Perform cleanup that requires refclk */ pci_epc_deinit_notify(pci->ep.epc); dw_pcie_ep_cleanup(&pci->ep); @@ -630,16 +649,6 @@ static int qcom_pcie_ep_get_resources(struct platform_= device *pdev, return ret; } =20 - pcie_ep->num_clks =3D devm_clk_bulk_get_all(dev, &pcie_ep->clks); - if (pcie_ep->num_clks < 0) { - dev_err(dev, "Failed to get clocks\n"); - return pcie_ep->num_clks; - } - - pcie_ep->core_reset =3D devm_reset_control_get_exclusive(dev, "core"); - if (IS_ERR(pcie_ep->core_reset)) - return PTR_ERR(pcie_ep->core_reset); - pcie_ep->reset =3D devm_gpiod_get(dev, "reset", GPIOD_IN); if (IS_ERR(pcie_ep->reset)) return PTR_ERR(pcie_ep->reset); @@ -652,9 +661,22 @@ static int qcom_pcie_ep_get_resources(struct platform_= device *pdev, if (IS_ERR(pcie_ep->phy)) ret =3D PTR_ERR(pcie_ep->phy); =20 - pcie_ep->icc_mem =3D devm_of_icc_get(dev, "pcie-mem"); - if (IS_ERR(pcie_ep->icc_mem)) - ret =3D PTR_ERR(pcie_ep->icc_mem); + /* Populate resources if Endpoint controller is not firmware-managed */ + if (!(pcie_ep->cfg && pcie_ep->cfg->firmware_managed)) { + pcie_ep->num_clks =3D devm_clk_bulk_get_all(dev, &pcie_ep->clks); + if (pcie_ep->num_clks < 0) { + dev_err(dev, "Failed to get clocks\n"); + return pcie_ep->num_clks; + } + + pcie_ep->core_reset =3D devm_reset_control_get_exclusive(dev, "core"); + if (IS_ERR(pcie_ep->core_reset)) + return PTR_ERR(pcie_ep->core_reset); + + pcie_ep->icc_mem =3D devm_of_icc_get(dev, "pcie-mem"); + if (IS_ERR(pcie_ep->icc_mem)) + ret =3D PTR_ERR(pcie_ep->icc_mem); + } =20 return ret; } @@ -874,6 +896,12 @@ static int qcom_pcie_ep_probe(struct platform_device *= pdev) =20 platform_set_drvdata(pdev, pcie_ep); =20 + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + ret =3D qcom_pcie_ep_get_resources(pdev, pcie_ep); if (ret) return ret; @@ -894,6 +922,12 @@ static int qcom_pcie_ep_probe(struct platform_device *= pdev) goto err_disable_irqs; } =20 + ret =3D pm_runtime_put_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to disable endpoint device: %d\n", ret); + goto err_disable_irqs; + } + pcie_ep->debugfs =3D debugfs_create_dir(name, NULL); qcom_pcie_ep_init_debugfs(pcie_ep); =20 @@ -930,7 +964,15 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 =3D { .disable_mhi_ram_parity_check =3D true, }; =20 +static const struct qcom_pcie_ep_cfg cfg_1_34_0_fw_managed =3D { + .hdma_support =3D true, + .override_no_snoop =3D true, + .disable_mhi_ram_parity_check =3D true, + .firmware_managed =3D true, +}; + static const struct of_device_id qcom_pcie_ep_match[] =3D { + { .compatible =3D "qcom,pcie-ep-sa8255p", .data =3D &cfg_1_34_0_fw_manage= d}, { .compatible =3D "qcom,sa8775p-pcie-ep", .data =3D &cfg_1_34_0}, { .compatible =3D "qcom,sdx55-pcie-ep", }, { .compatible =3D "qcom,sm8450-pcie-ep", }, --=20 2.25.1