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Wed, 17 Dec 2025 02:12:59 -0800 (PST) Received: from hu-msarkar-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7fcbb11ee42sm2290347b3a.43.2025.12.17.02.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Dec 2025 02:12:59 -0800 (PST) From: Mrinmay Sarkar Date: Wed, 17 Dec 2025 15:42:45 +0530 Subject: [PATCH v3 1/2] dt-bindings: PCI: qcom,pcie-ep-sa8255p: Document firmware managed PCIe endpoint Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-firmware_managed_ep-v3-1-ff871ba688fb@oss.qualcomm.com> References: <20251217-firmware_managed_ep-v3-0-ff871ba688fb@oss.qualcomm.com> In-Reply-To: <20251217-firmware_managed_ep-v3-0-ff871ba688fb@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Krishna Chaitanya Chundru , quic_vbadigan@quicinc.com, quic_shazhuss@quicinc.com, konrad.dybcio@oss.qualcomm.com, Mrinmay sarkar , Rama Krishna , Ayiluri Naga Rashmi , Nitesh Gupta X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Mrinmay Sarkar --- .../bindings/pci/qcom,pcie-ep-sa8255p.yaml | 110 +++++++++++++++++= ++++ 1 file changed, 110 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yam= l b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml new file mode 100644 index 0000000000000000000000000000000000000000..395cd23861ec26c00d51299829f= 1c60116293cae --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-ep-sa8255p.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm firmware managed PCIe Endpoint Controller + +description: + Qualcomm SA8255p SoC PCIe endpoint controller is based on the Synopsys + DesignWare PCIe IP which is managed by firmware. + +maintainers: + - Manivannan Sadhasivam + +properties: + compatible: + const: qcom,pcie-ep-sa8255p + + reg: + items: + - description: Qualcomm-specific PARF configuration registers + - description: DesignWare PCIe registers + - description: External local bus interface registers + - description: Address Translation Unit (ATU) registers + - description: Memory region used to map remote RC address space + - description: BAR memory region + - description: DMA register space + + reg-names: + items: + - const: parf + - const: dbi + - const: elbi + - const: atu + - const: addr_space + - const: mmio + - const: dma + + interrupts: + items: + - description: PCIe Global interrupt + - description: PCIe Doorbell interrupt + - description: DMA interrupt + + interrupt-names: + items: + - const: global + - const: doorbell + - const: dma + + iommus: + maxItems: 1 + + reset-gpios: + description: GPIO used as PERST# input signal + maxItems: 1 + + wake-gpios: + description: GPIO used as WAKE# output signal + maxItems: 1 + + power-domains: + maxItems: 1 + + dma-coherent: true + + num-lanes: + default: 2 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - reset-gpios + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + pcie1_ep: pcie-ep@1c10000 { + compatible =3D "qcom,pcie-ep-sa8255p"; + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60200000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>, + <0x0 0x60005000 0x0 0x2000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", "mmi= o", "dma"; + interrupts =3D , + , + ; + interrupt-names =3D "global", "doorbell", "dma"; + reset-gpios =3D <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 5 GPIO_ACTIVE_LOW>; + dma-coherent; + iommus =3D <&pcie_smmu 0x80 0x7f>; + power-domains =3D <&scmi6_pd 1>; + num-lanes =3D <4>; + }; + }; --=20 2.25.1