From nobody Thu Dec 18 01:04:28 2025 Received: from mta-64-227.siemens.flowmailer.net (mta-64-227.siemens.flowmailer.net [185.136.64.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7863236BCC3 for ; Tue, 16 Dec 2025 12:17:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.227 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765887438; cv=none; b=a8PCDdSc4jKi0cKMciZOYeU/3zU7WIDoyPSNHN7mExqBnFjvVgX82SGr5pp5sNSu7oykc7o6BDhiG8CBJF+TRDiNhnICMrecJMIfsSgc7co/tjG63MHIRWoKoaiHg8vKjVauJhJ5+jT+gFEZvVIHc0IAXbDII6zwmkuWs0Kk3Lk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765887438; c=relaxed/simple; bh=kclCNooV2IeTtW1J601jrIu2Ap7xvTdl1NfcpY678jw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=THzGFj2NLSpnWR+x0IOldzxAIqXsUbx2dEn2WXMiOYZL8zsZcBldpuQ516td94SGXVEglk45HZAm31sCCV0mSGM87DcJaCkwffyKxwhcyAUaNt+go4DlgrrbtGLm3wlgazHVrrLqk8durIa/x4z9rKygSKuCDgFkYn97ACX0QK4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=fail (0-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b=fkuSg7Ou reason="key not found in DNS"; arc=none smtp.client-ip=185.136.64.227 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b="fkuSg7Ou" Received: by mta-64-227.siemens.flowmailer.net with ESMTPSA id 202512161217088ebbdcd760000207cd for ; Tue, 16 Dec 2025 13:17:08 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm2; d=siemens.com; i=alexander.sverdlin@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=YawCl9Wk1TLgtNf/koT/2Vf52sv24n9OKnGfZ29QnOQ=; b=fkuSg7OusEFr788aBbXDkpN900oAljvj5B67L2iub/MFPMe509Jsi5vsjtA1kzlrXA2D4K FLcIfnZHuhr+9iq3DVd87ZfLVAEy679J/65XqIuDdt0niXXN6DRPZ6GcHN49At8ocoXLv+iX RGMuWlPvZBLVto0vhwwUKQ3gYR8q35pR0FV6Tm/mp7kr1/iWtjKkdBMpvDjEZVtr3kw5MkYh uJz8FQ8eMhUBpmUiHOJNVjAZPy+lg/+fMoaDiuOWp+/b5MVtKw+s0KU1l9I/lboQ6P2RNHcg dHhPw7ih2AOhSTCWgeaMFAo02tlUP3sxAiOoh4kmO2b5LqpuEjSnNMsA==; From: "A. Sverdlin" To: netdev@vger.kernel.org Cc: Alexander Sverdlin , Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Golle Subject: [PATCH net-next v2 1/2] dt-bindings: net: dsa: lantiq,gswip: add MaxLinear R(G)MII slew rate Date: Tue, 16 Dec 2025 13:17:00 +0100 Message-ID: <20251216121705.65156-2-alexander.sverdlin@siemens.com> In-Reply-To: <20251216121705.65156-1-alexander.sverdlin@siemens.com> References: <20251216121705.65156-1-alexander.sverdlin@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-456497:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Add new maxlinear,mii-slew-rate-slow boolean property. This property is only applicable for ports in R(G)MII mode and allows for slew rate reduction in comparison to "normal" default configuration with the purpose to reduce radiated emissions. Signed-off-by: Alexander Sverdlin --- Changelog: v2: - unchanged Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml b/= Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml index 205b683849a53..6cd5c6152c9e9 100644 --- a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +++ b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml @@ -106,6 +106,11 @@ patternProperties: unevaluatedProperties: false =20 properties: + maxlinear,mii-slew-rate-slow: + type: boolean + description: + Configure R(G)MII TXD/TXC pads' slew rate to "slow" instead + of "normal" to reduce radiated emissions. maxlinear,rmii-refclk-out: type: boolean description: --=20 2.52.0 From nobody Thu Dec 18 01:04:28 2025 Received: from mta-65-226.siemens.flowmailer.net (mta-65-226.siemens.flowmailer.net [185.136.65.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4EE136BCC2 for ; Tue, 16 Dec 2025 12:17:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.65.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765887439; cv=none; b=iY9kPTuYLbTfdfG4hEvStr/KpyRekQCKMaU5f5x+gxs0jTwdY9jHbs9ZRqxwpVt1OvimShsM0VbKz6Acs5bn0bfhJzme120gdYyKQpJtFP2CNVwn5B6yDPc5LOhWE0XocoBt91FwgUrZpmOgL0CqICAFJ6wKHfe5yyCKgSJRuxM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765887439; c=relaxed/simple; bh=vuq4eF9sjeQ4XhtBW4fUIOK6VBkbSp52r/WJd8GvaRY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ElGl41DrDBWv6Ve6watrbb94phdW+M45nv6nnaNJQvGwnDSrVU9ZpUnFK6l9rd+Usx6gsF8ahhV1tftCxhmUI1CGEk4257mbT4X/EPnogd5R9ORl1oZJZWV3VcbXMmNbZDkasKu2jLNNmguVxx/TU2fDYB/wTntTbYiJZhbSjqI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b=Adaifra/; arc=none smtp.client-ip=185.136.65.226 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b="Adaifra/" Received: by mta-65-226.siemens.flowmailer.net with ESMTPSA id 20251216121708b0be98801600020748 for ; Tue, 16 Dec 2025 13:17:08 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm2; d=siemens.com; i=alexander.sverdlin@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=kxa/wxHoMM+iUpsXVC+Um989vKgYKN1K4z4nEt1mwcw=; b=Adaifra/dnRGT2aB00yBGbiYl1y4bux9DmxCMjp+D3YpK1mqiO/zJstTC6ZlX1xWMNymKN 32SKBiP84d6ULdp+S6OQfyDKtYGzwzXYLDFpLBGX14Kc6ETBypf1g72LHNDDnBCn5fK7smoF s/OWWSFRfmcxLmqyDgXqRls0kEG/YeORmVVHhRZHOWyIkDbeeyKgP8B3DvrTQ+OMwpZqGau9 c+sAujJBh85QlBeUUD9AKuY9Je0oixNFBiYwsnHH0M/B5oLRW+Ni0G4H3iOo9F/qBEVC5d6n KXK3q7QPrQR9qHcHRwZlDVeAvwXC6wqlhHX9XlJ29cje+JEtg9KmJjpw==; From: "A. Sverdlin" To: netdev@vger.kernel.org Cc: Alexander Sverdlin , Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Golle Subject: [PATCH net-next v2 2/2] net: dsa: mxl-gsw1xx: Support R(G)MII slew rate configuration Date: Tue, 16 Dec 2025 13:17:01 +0100 Message-ID: <20251216121705.65156-3-alexander.sverdlin@siemens.com> In-Reply-To: <20251216121705.65156-1-alexander.sverdlin@siemens.com> References: <20251216121705.65156-1-alexander.sverdlin@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-456497:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Support newly introduced maxlinear,mii-slew-rate-slow device tree property to configure R(G)MII interface pins slew rate into "slow" mode. It might be used to reduce the radiated emissions. Signed-off-by: Alexander Sverdlin Reviewed-by: Daniel Golle --- Changelog: v2: - do not hijack gsw1xx_phylink_mac_select_pcs() for configuring the port, introduce struct gswip_hw_info::port_setup callback - actively configure "normal" slew rate (if the new DT property is missing) - properly use regmap_set_bits() (v1 had reg and value mixed up) drivers/net/dsa/lantiq/lantiq_gswip.h | 1 + drivers/net/dsa/lantiq/lantiq_gswip_common.c | 6 +++++ drivers/net/dsa/lantiq/mxl-gsw1xx.c | 26 ++++++++++++++++++++ drivers/net/dsa/lantiq/mxl-gsw1xx.h | 2 ++ 4 files changed, 35 insertions(+) diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.h b/drivers/net/dsa/lantiq= /lantiq_gswip.h index 9c38e51a75e80..3dc6c232a2e7b 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.h +++ b/drivers/net/dsa/lantiq/lantiq_gswip.h @@ -263,6 +263,7 @@ struct gswip_hw_info { struct phylink_config *config); struct phylink_pcs *(*mac_select_pcs)(struct phylink_config *config, phy_interface_t interface); + int (*port_setup)(struct dsa_switch *ds, int port); }; =20 struct gswip_gphy_fw { diff --git a/drivers/net/dsa/lantiq/lantiq_gswip_common.c b/drivers/net/dsa= /lantiq/lantiq_gswip_common.c index 9da39edf8f574..efa7526609a41 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip_common.c +++ b/drivers/net/dsa/lantiq/lantiq_gswip_common.c @@ -425,6 +425,12 @@ static int gswip_port_setup(struct dsa_switch *ds, int= port) struct gswip_priv *priv =3D ds->priv; int err; =20 + if (priv->hw_info->port_setup) { + err =3D priv->hw_info->port_setup(ds, port); + if (err) + return err; + } + if (!dsa_is_cpu_port(ds, port)) { err =3D gswip_add_single_port_br(priv, port, true); if (err) diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/m= xl-gsw1xx.c index 0816c61a47f12..cf35d5a00b7c8 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c @@ -531,6 +531,29 @@ static struct phylink_pcs *gsw1xx_phylink_mac_select_p= cs(struct phylink_config * } } =20 +static int gsw1xx_port_setup(struct dsa_switch *ds, int port) +{ + struct dsa_port *dp =3D dsa_to_port(ds, port); + struct gsw1xx_priv *gsw1xx_priv; + struct gswip_priv *gswip_priv; + int ret; + + if (dp->index !=3D GSW1XX_MII_PORT) + return 0; + + gswip_priv =3D ds->priv; + gsw1xx_priv =3D container_of(gswip_priv, struct gsw1xx_priv, gswip); + + if (of_property_read_bool(dp->dn, "maxlinear,mii-slew-rate-slow")) + ret =3D regmap_set_bits(gsw1xx_priv->shell, GSW1XX_SHELL_RGMII_SLEW_CFG, + RGMII_SLEW_CFG_DRV_TXD | RGMII_SLEW_CFG_DRV_TXC); + else + ret =3D regmap_clear_bits(gsw1xx_priv->shell, GSW1XX_SHELL_RGMII_SLEW_CF= G, + RGMII_SLEW_CFG_DRV_TXD | RGMII_SLEW_CFG_DRV_TXC); + + return ret; +} + static struct regmap *gsw1xx_regmap_init(struct gsw1xx_priv *priv, const char *name, unsigned int reg_base, @@ -674,6 +697,7 @@ static const struct gswip_hw_info gsw12x_data =3D { .pce_microcode =3D &gsw1xx_pce_microcode, .pce_microcode_size =3D ARRAY_SIZE(gsw1xx_pce_microcode), .tag_protocol =3D DSA_TAG_PROTO_MXL_GSW1XX, + .port_setup =3D gsw1xx_port_setup, }; =20 static const struct gswip_hw_info gsw140_data =3D { @@ -687,6 +711,7 @@ static const struct gswip_hw_info gsw140_data =3D { .pce_microcode =3D &gsw1xx_pce_microcode, .pce_microcode_size =3D ARRAY_SIZE(gsw1xx_pce_microcode), .tag_protocol =3D DSA_TAG_PROTO_MXL_GSW1XX, + .port_setup =3D gsw1xx_port_setup, }; =20 static const struct gswip_hw_info gsw141_data =3D { @@ -699,6 +724,7 @@ static const struct gswip_hw_info gsw141_data =3D { .pce_microcode =3D &gsw1xx_pce_microcode, .pce_microcode_size =3D ARRAY_SIZE(gsw1xx_pce_microcode), .tag_protocol =3D DSA_TAG_PROTO_MXL_GSW1XX, + .port_setup =3D gsw1xx_port_setup, }; =20 /* diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.h b/drivers/net/dsa/lantiq/m= xl-gsw1xx.h index 38e03c048a26c..8c0298b2b7663 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.h +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.h @@ -110,6 +110,8 @@ #define GSW1XX_RST_REQ_SGMII_SHELL BIT(5) /* RGMII PAD Slew Control Register */ #define GSW1XX_SHELL_RGMII_SLEW_CFG 0x78 +#define RGMII_SLEW_CFG_DRV_TXC BIT(2) +#define RGMII_SLEW_CFG_DRV_TXD BIT(3) #define RGMII_SLEW_CFG_RX_2_5_V BIT(4) #define RGMII_SLEW_CFG_TX_2_5_V BIT(5) =20 --=20 2.52.0