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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2d6ee1fa4; Tue, 16 Dec 2025 19:21:03 +0800 (GMT+08:00) From: Ye Zhang To: Ye Zhang , Linus Walleij , Heiko Stuebner Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tao.huang@rock-chips.com Subject: [PATCH v3 7/7] pinctrl: rockchip: add rmio support Date: Tue, 16 Dec 2025 19:20:53 +0800 Message-Id: <20251216112053.1927852-8-ye.zhang@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251216112053.1927852-1-ye.zhang@rock-chips.com> References: <20251216112053.1927852-1-ye.zhang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9b26e46e3909d8kunm7ab62e1d2a7b435 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQh1JHVZPTB0aGkxMTk1KGkJWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=ENLkM34DDZZcIrbJI4xBuZHaYatYVX1t4Bl9Zs8Vccg+farMvQQ9hYqpJpj5aWlCotIm9KL+XWyEOyNZzx5zdosmBrBP8/XsmwPtfJsqQChKX5id3clSfnUQbqfHvUSm3p8xg21OFW08H/m0j3lVyD3LZ5wRJh9KtjpdIP2nKTI=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=JMsY/6xUIYg72FO9i8/WKAtOJS3xupDI20CcO/zF1Uo=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Support Rockchip Matrix IO(RMIO), which can be configured with registers to route arbitrary signals from low-speed IP, such as UART/I2C, to the selected IO PAD. Signed-off-by: Ye Zhang --- drivers/pinctrl/pinctrl-rockchip.c | 401 ++++++++++++++++++++++++++++- drivers/pinctrl/pinctrl-rockchip.h | 42 +++ 2 files changed, 442 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-r= ockchip.c index dc7ef12dfcb0..cfd8117ab460 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3961,6 +3961,11 @@ static const struct of_device_id rockchip_bank_match= [] =3D { {}, }; =20 +static const struct of_device_id rockchip_rmio_dt_match[] =3D { + { .compatible =3D "rockchip,rmio" }, + {}, +}; + static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, struct device_node *np) { @@ -3969,6 +3974,8 @@ static void rockchip_pinctrl_child_count(struct rockc= hip_pinctrl *info, for_each_child_of_node(np, child) { if (of_match_node(rockchip_bank_match, child)) continue; + if (of_match_node(rockchip_rmio_dt_match, child)) + continue; =20 info->nfunctions++; info->ngroups +=3D of_get_child_count(child); @@ -4101,6 +4108,8 @@ static int rockchip_pinctrl_parse_dt(struct platform_= device *pdev, for_each_child_of_node_scoped(np, child) { if (of_match_node(rockchip_bank_match, child)) continue; + if (of_match_node(rockchip_rmio_dt_match, child)) + continue; =20 ret =3D rockchip_pinctrl_parse_functions(child, info, i++); if (ret) { @@ -4431,6 +4440,388 @@ static void rockchip_pinctrl_remove(struct platform= _device *pdev) } } =20 +static int rockchip_rmio_set_mux(struct rockchip_rmio *info, int id, int f= unc) +{ + struct device *dev =3D info->dev; + + if (id >=3D info->nr_pins) + return -EINVAL; + + dev_dbg(dev, "setting function of %s%d to %d\n", dev_name(dev), id, func); + + return regmap_write(info->regmap, info->offset + id * 4, + RK_RMIO_WRITE_ENABLE_MASK | func); +} + +static int rockchip_rmio_parse_groups(struct device_node *np, + struct rockchip_rmio_group *grp, + struct rockchip_rmio *info, + u32 index) +{ + struct device *dev =3D info->dev; + int count; + u32 *tmp; + int i; + + dev_dbg(dev, "group(%d): %pOFn\n", index, np); + + /* + * the binding format is rockchip,rmio =3D , + * do sanity check and calculate pins number + */ + count =3D of_property_count_u32_elems(np, "rockchip,rmio"); + if (count <=3D 0 || count % 2 !=3D 0) + return -EINVAL; + + tmp =3D kcalloc(count, sizeof(u32), GFP_KERNEL); + if (!tmp) + return -ENOMEM; + + of_property_read_u32_array(np, "rockchip,rmio", tmp, count); + + /* Initialise group */ + grp->name =3D np->name; + grp->npins =3D count / 2; + grp->pins =3D devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNE= L); + grp->func =3D devm_kcalloc(dev, grp->npins, sizeof(*grp->func), GFP_KERNE= L); + if (!grp->pins || !grp->func) { + kfree(tmp); + return -ENOMEM; + } + + for (i =3D 0; i < grp->npins; i++) { + grp->pins[i] =3D tmp[2 * i]; + grp->func[i] =3D tmp[2 * i + 1]; + } + kfree(tmp); + + return 0; +} + +static int rockchip_rmio_parse_functions(struct device_node *np, + struct rockchip_rmio *info, + u32 index) +{ + struct device *dev =3D info->dev; + struct device_node *child; + struct rockchip_rmio_func *func; + struct rockchip_rmio_group *grp; + int ret; + u32 i, grp_index =3D 0; + + dev_dbg(dev, "parse function(%d): %pOFn\n", index, np); + + for (i =3D 0, func =3D info->functions; i < index; i++, func++) + grp_index +=3D func->ngroups; + + func =3D &info->functions[index]; + + /* Initialise function */ + func->name =3D np->name; + func->ngroups =3D of_get_child_count(np); + if (func->ngroups <=3D 0) + return 0; + + func->groups =3D devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), = GFP_KERNEL); + if (!func->groups) + return -ENOMEM; + + i =3D 0; + for_each_child_of_node(np, child) { + func->groups[i] =3D child->name; + grp =3D &info->groups[grp_index + i]; + ret =3D rockchip_rmio_parse_groups(child, grp, info, i++); + if (ret) { + of_node_put(child); + return ret; + } + } + + return 0; +} + +static int rockchip_rmio_parse_dt(struct platform_device *pdev, + struct rockchip_rmio *info) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + struct device_node *child; + int ret; + int i =3D 0; + + for_each_child_of_node(np, child) { + info->nfunctions++; + info->ngroups +=3D of_get_child_count(child); + } + + dev_dbg(dev, "nfunctions =3D %d\n", info->nfunctions); + dev_dbg(dev, "ngroups =3D %d\n", info->ngroups); + + info->functions =3D devm_kcalloc(dev, info->nfunctions, sizeof(*info->fun= ctions), GFP_KERNEL); + if (!info->functions) + return -ENOMEM; + + info->groups =3D devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), = GFP_KERNEL); + if (!info->groups) + return -ENOMEM; + + for_each_child_of_node(np, child) { + ret =3D rockchip_rmio_parse_functions(child, info, i++); + if (ret) { + dev_err(dev, "failed to parse function, ret =3D %d\n", ret); + of_node_put(child); + return ret; + } + } + + return 0; +} + +static int rockchip_rmio_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + + return info->ngroups; +} + +static const char *rockchip_rmio_get_group_name(struct pinctrl_dev *pctlde= v, + unsigned int selector) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + + return info->groups[selector].name; +} + +static int rockchip_rmio_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *npins) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + + if (selector >=3D info->ngroups) + return -EINVAL; + + *pins =3D info->groups[selector].pins; + *npins =3D info->groups[selector].npins; + + return 0; +} + +static int rockchip_rmio_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + struct device *dev =3D info->dev; + struct pinctrl_map *new_map; + struct device_node *parent; + + parent =3D of_get_parent(np); + if (!parent) + return -EINVAL; + + /* the rmio only need to create mux map */ + new_map =3D kzalloc(sizeof(*new_map), GFP_KERNEL); + if (!new_map) { + of_node_put(parent); + return -ENOMEM; + } + + *map =3D new_map; + *num_maps =3D 1; + + /* the rmio only need to create mux map */ + new_map->type =3D PIN_MAP_TYPE_MUX_GROUP; + new_map->data.mux.function =3D parent->name; + new_map->data.mux.group =3D np->name; + of_node_put(parent); + + dev_dbg(dev, "maps: function %s group %s\n", + (*map)->data.mux.function, (*map)->data.mux.group); + + return 0; +} + +static void rockchip_rmio_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned int num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops rockchip_rmio_pctrl_ops =3D { + .get_groups_count =3D rockchip_rmio_get_groups_count, + .get_group_name =3D rockchip_rmio_get_group_name, + .get_group_pins =3D rockchip_rmio_get_group_pins, + .dt_node_to_map =3D rockchip_rmio_dt_node_to_map, + .dt_free_map =3D rockchip_rmio_dt_free_map, +}; + +static int rockchip_rmio_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + + return info->nfunctions; +} + +static const char *rockchip_rmio_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + + return info->functions[selector].name; +} + +static int rockchip_rmio_get_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + + *groups =3D info->functions[selector].groups; + *num_groups =3D info->functions[selector].ngroups; + + return 0; +} + +static int rockchip_rmio_pmx_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned int group) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins =3D info->groups[group].pins; + const unsigned int *func =3D info->groups[group].func; + struct device *dev =3D info->dev; + int cnt, ret =3D 0; + + dev_dbg(dev, "enable function %s group %s\n", + info->functions[selector].name, info->groups[group].name); + + /* + * for each pin in the pin group selected, program the corresponding + * pin function number in the config register. + */ + for (cnt =3D 0; cnt < info->groups[group].npins; cnt++) { + ret =3D rockchip_rmio_set_mux(info, pins[cnt], func[cnt]); + if (ret) + break; + } + + if (ret && cnt) { + /* revert the already done pin settings */ + for (cnt--; cnt >=3D 0; cnt--) + rockchip_rmio_set_mux(info, pins[cnt], RK_RMIO_NC); + + return ret; + } + + return 0; +} + +static const struct pinmux_ops rockchip_rmio_pmx_ops =3D { + .get_functions_count =3D rockchip_rmio_get_funcs_count, + .get_function_name =3D rockchip_rmio_get_func_name, + .get_function_groups =3D rockchip_rmio_get_groups, + .set_mux =3D rockchip_rmio_pmx_set, +}; + +static int rockchip_rmio_register(struct platform_device *pdev, + struct rockchip_rmio *info) +{ + struct pinctrl_desc *ctrldesc =3D &info->pctl; + struct pinctrl_pin_desc *pindesc, *pdesc; + struct device *dev =3D &pdev->dev; + char **pin_names; + int ret; + int i; + int nr_pins =3D info->nr_pins; + + ctrldesc->name =3D dev_name(dev); + ctrldesc->owner =3D THIS_MODULE; + ctrldesc->pctlops =3D &rockchip_rmio_pctrl_ops; + ctrldesc->pmxops =3D &rockchip_rmio_pmx_ops; + + pindesc =3D devm_kcalloc(dev, nr_pins, sizeof(*pindesc), GFP_KERNEL); + if (!pindesc) + return -ENOMEM; + + ctrldesc->pins =3D pindesc; + ctrldesc->npins =3D nr_pins; + + pdesc =3D pindesc; + pin_names =3D devm_kasprintf_strarray(dev, dev_name(dev), nr_pins); + if (IS_ERR(pin_names)) + return PTR_ERR(pin_names); + for (i =3D 0; i < nr_pins; i++) { + pdesc->number =3D i; + pdesc->name =3D pin_names[i]; + pdesc++; + } + + ret =3D rockchip_rmio_parse_dt(pdev, info); + if (ret) + return ret; + + info->pctl_dev =3D devm_pinctrl_register(dev, ctrldesc, info); + if (IS_ERR(info->pctl_dev)) + return dev_err_probe(dev, PTR_ERR(info->pctl_dev), + "could not register pinctrl driver\n"); + + return 0; +} + +static int rockchip_rmio_probe(struct platform_device *pdev) +{ + struct rockchip_rmio *info; + struct device *dev =3D &pdev->dev; + struct device_node *np =3D pdev->dev.of_node; + int ret; + + info =3D devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->dev =3D dev; + + info->regmap =3D syscon_regmap_lookup_by_phandle(np, "rockchip,rmio-grf"); + if (IS_ERR(info->regmap)) { + dev_err(&pdev->dev, "missing rockchip,rmio-grf property\n"); + return PTR_ERR(info->regmap); + } + + ret =3D of_property_read_u32(np, "rockchip,offset", &info->offset); + if (ret < 0) { + dev_err(&pdev->dev, "missing rockchip,offset property\n"); + return ret; + } + + ret =3D of_property_read_u32(np, "rockchip,pins-num", &info->nr_pins); + if (ret < 0) { + dev_err(&pdev->dev, "missing rockchip,pins-num property\n"); + return ret; + } + + ret =3D rockchip_rmio_register(pdev, info); + if (ret) + return ret; + + platform_set_drvdata(pdev, info); + dev_info(dev, "probed %pfw\n", dev_fwnode(dev)); + + return 0; +} + +static struct platform_driver rockchip_rmio_driver =3D { + .probe =3D rockchip_rmio_probe, + .driver =3D { + .name =3D "rockchip-rmio", + .of_match_table =3D rockchip_rmio_dt_match, + }, +}; + static struct rockchip_pin_bank px30_pin_banks[] =3D { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, @@ -5190,12 +5581,19 @@ static struct platform_driver rockchip_pinctrl_driv= er =3D { =20 static int __init rockchip_pinctrl_drv_register(void) { - return platform_driver_register(&rockchip_pinctrl_driver); + int ret; + + ret =3D platform_driver_register(&rockchip_pinctrl_driver); + if (ret) + return ret; + + return platform_driver_register(&rockchip_rmio_driver); } postcore_initcall(rockchip_pinctrl_drv_register); =20 static void __exit rockchip_pinctrl_drv_unregister(void) { + platform_driver_unregister(&rockchip_rmio_driver); platform_driver_unregister(&rockchip_pinctrl_driver); } module_exit(rockchip_pinctrl_drv_unregister); @@ -5204,3 +5602,4 @@ MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:pinctrl-rockchip"); MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); +MODULE_DEVICE_TABLE(of, rockchip_rmio_dt_match); diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-r= ockchip.h index fe18b62ed994..db875f7a3d2f 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -183,6 +183,9 @@ #define RK_GPIO4_D6 158 #define RK_GPIO4_D7 159 =20 +#define RK_RMIO_NC 0 +#define RK_RMIO_WRITE_ENABLE_MASK 0xFFFF0000 + enum rockchip_pinctrl_type { PX30, RV1108, @@ -473,4 +476,43 @@ struct rockchip_pinctrl { unsigned int nfunctions; }; =20 +/** + * struct rockchip_rmio_group: represent a group of pins in RMIO controlle= r. + * @name: name of the pin group, used to lookup the group. + * @pins: array of pins included in this group. + * @npins: number of pins included in this group. + * @func: local pins function select + */ +struct rockchip_rmio_group { + const char *name; + unsigned int npins; + unsigned int *pins; + unsigned int *func; +}; + +/** + * struct rockchip_rmio_func: represent a RMIO pin function. + * @name: name of the RMIO function, used to lookup the function. + * @groups: array of group names that can provide this RMIO function. + * @ngroups: number of groups included in @groups. + */ +struct rockchip_rmio_func { + const char *name; + const char **groups; + u8 ngroups; +}; + +struct rockchip_rmio { + struct regmap *regmap; + u32 offset; + struct device *dev; + struct pinctrl_desc pctl; + struct pinctrl_dev *pctl_dev; + unsigned int nr_pins; + struct rockchip_rmio_group *groups; + unsigned int ngroups; + struct rockchip_rmio_func *functions; + unsigned int nfunctions; +}; + #endif --=20 2.34.1