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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2d6ee1fa0; Tue, 16 Dec 2025 19:21:01 +0800 (GMT+08:00) From: Ye Zhang To: Ye Zhang , Linus Walleij , Heiko Stuebner Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tao.huang@rock-chips.com Subject: [PATCH v3 6/7] dt-bindings: pinctrl: rockchip: Add RMIO controller binding Date: Tue, 16 Dec 2025 19:20:52 +0800 Message-Id: <20251216112053.1927852-7-ye.zhang@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251216112053.1927852-1-ye.zhang@rock-chips.com> References: <20251216112053.1927852-1-ye.zhang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9b26e4691409d8kunm7ab62e1d2a7b3bf X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQkpLTlZKSkgfQklNTh1MSx9WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=ULTOS+RsdtB/JaLyeX8BDv5ZWIBiA1Hp4yQl5a7ZSQaKB8imQVtmxx7Ry0jGp6rSXU8KOdBKCRGEXr5HOp2669uXa3czx0WTv1xiwls4l72xGef1mZBiY8QwKH+2X8o7E1gSba3dVWMjs26pWGI8yTQfDwcOJe6HtegA0IjIw78=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=9YZsNhFzzR6dDdU0HTPthyvmRQ2DTHuowAWIUZgM/GY=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" 1. Add header file with constants for RMIO function IDs for the Rockchip RK3506 SoC. 2. Add device tree binding for the RMIO (Rockchip Matrix I/O) controller which is a sub-device of the main pinctrl on some Rockchip SoCs. Signed-off-by: Ye Zhang --- .../bindings/pinctrl/rockchip,pinctrl.yaml | 9 ++ .../bindings/pinctrl/rockchip,rmio.yaml | 106 +++++++++++++++++ .../pinctrl/rockchip,rk3506-rmio.h | 109 ++++++++++++++++++ 3 files changed, 224 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/rockchip,rmio= .yaml create mode 100644 include/dt-bindings/pinctrl/rockchip,rk3506-rmio.h diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yam= l b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index 97960245676d..9a27eaf7942b 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -82,6 +82,15 @@ required: - rockchip,grf =20 patternProperties: + "rmio[0-9]*$": + type: object + + $ref: "/schemas/pinctrl/rockchip,rmio.yaml#" + + description: + The RMIO (Rockchip Matrix I/O) controller node which functions as a + sub-device of the main pinctrl to handle flexible function routing. + "gpio@[0-9a-f]+$": type: object =20 diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,rmio.yaml b= /Documentation/devicetree/bindings/pinctrl/rockchip,rmio.yaml new file mode 100644 index 000000000000..af0b34512fb9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,rmio.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/rockchip,rmio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RMIO (Rockchip Matrix I/O) Controller + +maintainers: + - Heiko Stuebner + +description: | + The RMIO controller provides a flexible routing matrix that allows mappi= ng + various internal peripheral functions (UART, SPI, PWM, etc.) to specific + physical pins. This block is typically a sub-block of the GRF + (General Register Files) or PMU (Power Management Unit). + +properties: + compatible: + items: + - enum: + - rockchip,rk3506-rmio + - const: rockchip,rmio + + rockchip,rmio-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node (GRF or PMU) containing the RMIO regi= sters. + This property is required if the RMIO registers are located in a dif= ferent + syscon than the parent pinctrl node. + + rockchip,offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The offset of the RMIO configuration registers within the GRF. + + rockchip,pins-num: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The number of physical pins supported by this RMIO instance. + Used for boundary checking and driver initialization. + +patternProperties: + "^[a-z0-9-]+$": + type: object + description: + Function node grouping multiple groups. + + patternProperties: + "^[a-z0-9-]+$": + type: object + description: + Group node containing the pinmux configuration. + + properties: + rockchip,rmio: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + A list of pin-function pairs. The format is . + minItems: 1 + items: + items: + - description: RMIO Pin ID (0 to pins-num - 1) + minimum: 0 + maximum: 31 + - description: Function ID + minimum: 0 + maximum: 98 + + required: + - rockchip,rmio + + additionalProperties: false + + additionalProperties: false + +required: + - compatible + - rockchip,rmio-grf + - rockchip,offset + - rockchip,pins-num + +additionalProperties: false + +examples: + - | + #include + + pinctrl: pinctrl { + rmio: rmio { + compatible =3D "rockchip,rk3506-rmio", "rockchip,rmio"; + rockchip,rmio-grf =3D <&grf_pmu>; + rockchip,offset =3D <0x80>; + rockchip,pins-num =3D <32>; + + rmio-uart { + rmio_pin27_uart1_tx: rmio-pin27-uart1-tx { + rockchip,rmio =3D <27 RMIO_UART1_TX>; + }; + + rmio_pin28_uart1_rx: rmio-pin28-uart1-rx { + rockchip,rmio =3D <28 RMIO_UART1_RX>; + }; + }; + }; + }; diff --git a/include/dt-bindings/pinctrl/rockchip,rk3506-rmio.h b/include/d= t-bindings/pinctrl/rockchip,rk3506-rmio.h new file mode 100644 index 000000000000..b129e9a8c287 --- /dev/null +++ b/include/dt-bindings/pinctrl/rockchip,rk3506-rmio.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +#ifndef __DT_BINDINGS_PINCTRL_ROCKCHIP_RK3506_RMIO_H +#define __DT_BINDINGS_PINCTRL_ROCKCHIP_RK3506_RMIO_H + +/* RMIO function definition */ +#define RMIO_UART1_TX 1 +#define RMIO_UART1_RX 2 +#define RMIO_UART2_TX 3 +#define RMIO_UART2_RX 4 +#define RMIO_UART3_TX 5 +#define RMIO_UART3_RX 6 +#define RMIO_UART3_CTSN 7 +#define RMIO_UART3_RTSN 8 +#define RMIO_UART4_TX 9 +#define RMIO_UART4_RX 10 +#define RMIO_UART4_CTSN 11 +#define RMIO_UART4_RTSN 12 +#define RMIO_MIPITE 13 +#define RMIO_CLK_32K 14 +#define RMIO_I2C0_SCL 15 +#define RMIO_I2C0_SDA 16 +#define RMIO_I2C1_SCL 17 +#define RMIO_I2C1_SDA 18 +#define RMIO_I2C2_SCL 19 +#define RMIO_I2C2_SDA 20 +#define RMIO_PDM_CLK0 21 +#define RMIO_PDM_SDI0 22 +#define RMIO_PDM_SDI1 23 +#define RMIO_PDM_SDI2 24 +#define RMIO_PDM_SDI3 25 +#define RMIO_CAN1_TX 26 +#define RMIO_CAN1_RX 27 +#define RMIO_CAN0_TX 28 +#define RMIO_CAN0_RX 29 +#define RMIO_PWM0_CH0 30 +#define RMIO_PWM0_CH1 31 +#define RMIO_PWM0_CH2 32 +#define RMIO_PWM0_CH3 33 +#define RMIO_PWM1_CH0 34 +#define RMIO_PWM1_CH1 35 +#define RMIO_PWM1_CH2 36 +#define RMIO_PWM1_CH3 37 +#define RMIO_PWM1_CH4 38 +#define RMIO_PWM1_CH5 39 +#define RMIO_PWM1_CH6 40 +#define RMIO_PWM1_CH7 41 +#define RMIO_TOUCH_KEY_DRIVE 42 +#define RMIO_TOUCH_KEY_IN0 43 +#define RMIO_TOUCH_KEY_IN1 44 +#define RMIO_TOUCH_KEY_IN2 45 +#define RMIO_TOUCH_KEY_IN3 46 +#define RMIO_TOUCH_KEY_IN4 47 +#define RMIO_TOUCH_KEY_IN5 48 +#define RMIO_TOUCH_KEY_IN6 49 +#define RMIO_TOUCH_KEY_IN7 50 +#define RMIO_SAI0_MCLK 51 +#define RMIO_SAI0_SCLK 52 +#define RMIO_SAI0_LRCK 53 +#define RMIO_SAI0_SDI0 54 +#define RMIO_SAI0_SDI1 55 +#define RMIO_SAI0_SDI2 56 +#define RMIO_SAI0_SDI3 57 +#define RMIO_SAI0_SDO 58 +#define RMIO_SAI1_MCLK 59 +#define RMIO_SAI1_SCLK 60 +#define RMIO_SAI1_LRCK 61 +#define RMIO_SAI1_SDI 62 +#define RMIO_SAI1_SDO0 63 +#define RMIO_SAI1_SDO1 64 +#define RMIO_SAI1_SDO2 65 +#define RMIO_SAI1_SDO3 66 +#define RMIO_SPI0_CLK 67 +#define RMIO_SPI0_MOSI 68 +#define RMIO_SPI0_MISO 69 +#define RMIO_SPI0_CSN0 70 +#define RMIO_SPI0_CSN1 71 +#define RMIO_SPI1_CLK 72 +#define RMIO_SPI1_MOSI 73 +#define RMIO_SPI1_MISO 74 +#define RMIO_SPI1_CSN0 75 +#define RMIO_SPI1_CSN1 76 +#define RMIO_WDT_TSADC_SHUT 77 +#define RMIO_PMU_SLEEP 78 +#define RMIO_CORE_POWER_OFF 79 +#define RMIO_SPDIF_TX 80 +#define RMIO_SPDIF_RX 81 +#define RMIO_PWM1_BIP_CNTR_A0 82 +#define RMIO_PWM1_BIP_CNTR_A1 83 +#define RMIO_PWM1_BIP_CNTR_A2 84 +#define RMIO_PWM1_BIP_CNTR_A3 85 +#define RMIO_PWM1_BIP_CNTR_A4 86 +#define RMIO_PWM1_BIP_CNTR_A5 87 +#define RMIO_PWM1_BIP_CNTR_B0 88 +#define RMIO_PWM1_BIP_CNTR_B1 89 +#define RMIO_PWM1_BIP_CNTR_B2 90 +#define RMIO_PWM1_BIP_CNTR_B3 91 +#define RMIO_PWM1_BIP_CNTR_B4 92 +#define RMIO_PWM1_BIP_CNTR_B5 93 +#define RMIO_PDM_CLK1 94 +#define RMIO_ETH_RMII0_PPSCLK 95 +#define RMIO_ETH_RMII0_PPSTRIG 96 +#define RMIO_ETH_RMII1_PPSCLK 97 +#define RMIO_ETH_RMII1_PPSTRIG 98 + +#endif /* __DT_BINDINGS_PINCTRL_ROCKCHIP_RK3506_RMIO_H */ --=20 2.34.1