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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2d6ee1f97; Tue, 16 Dec 2025 19:20:57 +0800 (GMT+08:00) From: Ye Zhang To: Ye Zhang , Linus Walleij , Heiko Stuebner Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tao.huang@rock-chips.com Subject: [PATCH v3 3/7] pinctrl: rockchip: Add rv1126b pinctrl support Date: Tue, 16 Dec 2025 19:20:49 +0800 Message-Id: <20251216112053.1927852-4-ye.zhang@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251216112053.1927852-1-ye.zhang@rock-chips.com> References: <20251216112053.1927852-1-ye.zhang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9b26e4593009d8kunm7ab62e1d2a7b26b X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQk0YH1ZCSRlCSUlNGkpPThhWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=bX2+5KIIz9+yqvMTanixYEdU7m16vkrtEL86+ULuHO/hma9zJq8GuoU/PVJIJyY+8jgGcnCAJNJ4UThXN9W0Qick+XgIZunvUeHKhCk+Ax6n1mLnIT1PvZ/zoYdijxVRTBrug9nk2eN/DK4Rkykj5L9XhYO3l9BfdMTudq4lzKo=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=53wx/l9Bicx82HEIi48rhqopVN+cJfr8QQsKHaeSvYs=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add gpio and pinctrl support for the 8 GPIO banks on RV1126B. Signed-off-by: Ye Zhang --- drivers/pinctrl/pinctrl-rockchip.c | 181 ++++++++++++++++++++++++++++- drivers/pinctrl/pinctrl-rockchip.h | 1 + 2 files changed, 181 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-r= ockchip.c index e44ef262beec..dc7ef12dfcb0 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -307,6 +307,20 @@ #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \ PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P) =20 +#define PIN_BANK_IOMUX_4_OFFSET_DRV_8(id, pins, label, offset0, \ + offset1, offset2, offset3) \ + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, \ + IOMUX_WIDTH_4BIT, \ + IOMUX_WIDTH_4BIT, \ + IOMUX_WIDTH_4BIT, \ + IOMUX_WIDTH_4BIT, \ + offset0, offset1, \ + offset2, offset3, \ + DRV_TYPE_IO_LEVEL_8_BIT, \ + DRV_TYPE_IO_LEVEL_8_BIT, \ + DRV_TYPE_IO_LEVEL_8_BIT, \ + DRV_TYPE_IO_LEVEL_8_BIT) + static struct regmap_config rockchip_regmap_config =3D { .reg_bits =3D 32, .val_bits =3D 32, @@ -1701,6 +1715,136 @@ static int rv1126_calc_schmitt_reg_and_bit(struct r= ockchip_pin_bank *bank, return 0; } =20 +#define RV1126B_DRV_BITS_PER_PIN 8 +#define RV1126B_DRV_PINS_PER_REG 2 +#define RV1126B_DRV_GPIO0_A_OFFSET 0x100 +#define RV1126B_DRV_GPIO0_C_OFFSET 0x8120 +#define RV1126B_DRV_GPIO_OFFSET(GPION) (0x8100 + GPION * 0x8040) + +static int rv1126b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info =3D bank->drvdata; + + *regmap =3D info->regmap_base; + switch (bank->bank_num) { + case 0: + if (pin_num < 16) + *reg =3D RV1126B_DRV_GPIO0_A_OFFSET; + else + *reg =3D RV1126B_DRV_GPIO0_C_OFFSET - 0x20; + break; + + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + *reg =3D RV1126B_DRV_GPIO_OFFSET(bank->bank_num); + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg +=3D ((pin_num / RV1126B_DRV_PINS_PER_REG) * 4); + *bit =3D pin_num % RV1126B_DRV_PINS_PER_REG; + *bit *=3D RV1126B_DRV_BITS_PER_PIN; + + return 0; +} + +#define RV1126B_PULL_BITS_PER_PIN 2 +#define RV1126B_PULL_PINS_PER_REG 8 +#define RV1126B_PULL_GPIO0_A_OFFSET 0x300 +#define RV1126B_PULL_GPIO0_C_OFFSET 0x8308 +#define RV1126B_PULL_GPIO_OFFSET(GPION) (0x8300 + GPION * 0x8010) + +static int rv1126b_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info =3D bank->drvdata; + + *regmap =3D info->regmap_base; + switch (bank->bank_num) { + case 0: + if (pin_num < 16) + *reg =3D RV1126B_PULL_GPIO0_A_OFFSET; + else + *reg =3D RV1126B_PULL_GPIO0_C_OFFSET - 0x8; + break; + + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + *reg =3D RV1126B_PULL_GPIO_OFFSET(bank->bank_num); + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg +=3D ((pin_num / RV1126B_PULL_PINS_PER_REG) * 4); + *bit =3D pin_num % RV1126B_PULL_PINS_PER_REG; + *bit *=3D RV1126B_PULL_BITS_PER_PIN; + + return 0; +} + +#define RV1126B_SMT_BITS_PER_PIN 1 +#define RV1126B_SMT_PINS_PER_REG 8 +#define RV1126B_SMT_GPIO0_A_OFFSET 0x500 +#define RV1126B_SMT_GPIO0_C_OFFSET 0x8508 +#define RV1126B_SMT_GPIO_OFFSET(GPION) (0x8500 + GPION * 0x8010) + +static int rv1126b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info =3D bank->drvdata; + + *regmap =3D info->regmap_base; + switch (bank->bank_num) { + case 0: + if (pin_num < 16) + *reg =3D RV1126B_SMT_GPIO0_A_OFFSET; + else + *reg =3D RV1126B_SMT_GPIO0_C_OFFSET - 0x8; + break; + + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + *reg =3D RV1126B_SMT_GPIO_OFFSET(bank->bank_num); + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg +=3D ((pin_num / RV1126B_SMT_PINS_PER_REG) * 4); + *bit =3D pin_num % RV1126B_SMT_PINS_PER_REG; + *bit *=3D RV1126B_SMT_BITS_PER_PIN; + + return 0; +} + #define RK3308_SCHMITT_PINS_PER_REG 8 #define RK3308_SCHMITT_BANK_STRIDE 16 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 @@ -3071,7 +3215,8 @@ static int rockchip_set_drive_perpin(struct rockchip_= pin_bank *bank, rmask_bits =3D RK3588_DRV_BITS_PER_PIN; ret =3D strength; goto config; - } else if (ctrl->type =3D=3D RK3506 || + } else if (ctrl->type =3D=3D RV1126B || + ctrl->type =3D=3D RK3506 || ctrl->type =3D=3D RK3528 || ctrl->type =3D=3D RK3562 || ctrl->type =3D=3D RK3568) { @@ -3237,6 +3382,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank= *bank, int pin_num) : PIN_CONFIG_BIAS_DISABLE; case PX30: case RV1108: + case RV1126B: case RK3188: case RK3288: case RK3308: @@ -3299,6 +3445,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank= *bank, case PX30: case RV1108: case RV1126: + case RV1126B: case RK3188: case RK3288: case RK3308: @@ -3582,6 +3729,7 @@ static bool rockchip_pinconf_pull_valid(struct rockch= ip_pin_ctrl *ctrl, case PX30: case RV1108: case RV1126: + case RV1126B: case RK3188: case RK3288: case RK3308: @@ -4386,6 +4534,35 @@ static struct rockchip_pin_ctrl rv1126_pin_ctrl =3D { .schmitt_calc_reg =3D rv1126_calc_schmitt_reg_and_bit, }; =20 +static struct rockchip_pin_bank rv1126b_pin_banks[] =3D { + PIN_BANK_IOMUX_4_OFFSET_DRV_8(0, 32, "gpio0", + 0x0, 0x8, 0x8010, 0x8018), + PIN_BANK_IOMUX_4_OFFSET_DRV_8(1, 32, "gpio1", + 0x10020, 0x10028, 0x10030, 0x10038), + PIN_BANK_IOMUX_4_OFFSET_DRV_8(2, 32, "gpio2", + 0x18040, 0x18048, 0x18050, 0x18058), + PIN_BANK_IOMUX_4_OFFSET_DRV_8(3, 32, "gpio3", + 0x20060, 0x20068, 0x20070, 0x20078), + PIN_BANK_IOMUX_4_OFFSET_DRV_8(4, 32, "gpio4", + 0x28080, 0x28088, 0x28090, 0x28098), + PIN_BANK_IOMUX_4_OFFSET_DRV_8(5, 32, "gpio5", + 0x300a0, 0x300a8, 0x300b0, 0x300b8), + PIN_BANK_IOMUX_4_OFFSET_DRV_8(6, 32, "gpio6", + 0x380c0, 0x380c8, 0x380d0, 0x380d8), + PIN_BANK_IOMUX_4_OFFSET_DRV_8(7, 32, "gpio7", + 0x400e0, 0x400e8, 0x400f0, 0x400f8), +}; + +static struct rockchip_pin_ctrl rv1126b_pin_ctrl __maybe_unused =3D { + .pin_banks =3D rv1126b_pin_banks, + .nr_banks =3D ARRAY_SIZE(rv1126b_pin_banks), + .label =3D "RV1126B-GPIO", + .type =3D RV1126B, + .pull_calc_reg =3D rv1126b_calc_pull_reg_and_bit, + .drv_calc_reg =3D rv1126b_calc_drv_reg_and_bit, + .schmitt_calc_reg =3D rv1126b_calc_schmitt_reg_and_bit, +}; + static struct rockchip_pin_bank rk2928_pin_banks[] =3D { PIN_BANK(0, 32, "gpio0"), PIN_BANK(1, 32, "gpio1"), @@ -4960,6 +5137,8 @@ static const struct of_device_id rockchip_pinctrl_dt_= match[] =3D { .data =3D &rv1108_pin_ctrl }, { .compatible =3D "rockchip,rv1126-pinctrl", .data =3D &rv1126_pin_ctrl }, + { .compatible =3D "rockchip,rv1126b-pinctrl", + .data =3D &rv1126b_pin_ctrl }, { .compatible =3D "rockchip,rk2928-pinctrl", .data =3D &rk2928_pin_ctrl }, { .compatible =3D "rockchip,rk3036-pinctrl", diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-r= ockchip.h index 4f4aff42a80a..fe18b62ed994 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -187,6 +187,7 @@ enum rockchip_pinctrl_type { PX30, RV1108, RV1126, + RV1126B, RK2928, RK3066B, RK3128, --=20 2.34.1