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Mon, 15 Dec 2025 17:47:50 -0800 (PST) From: Yunhui Cui To: aou@eecs.berkeley.edu, alex@ghiti.fr, andii@kernel.org, andybnac@gmail.com, apatel@ventanamicro.com, ast@kernel.org, ben.dooks@codethink.co.uk, bjorn@kernel.org, bpf@vger.kernel.org, charlie@rivosinc.com, cl@gentwo.org, conor.dooley@microchip.com, cuiyunhui@bytedance.com, cyrilbur@tenstorrent.com, daniel@iogearbox.net, debug@rivosinc.com, dennis@kernel.org, eddyz87@gmail.com, haoluo@google.com, john.fastabend@gmail.com, jolsa@kernel.org, kpsingh@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux@rasmusvillemoes.dk, martin.lau@linux.dev, palmer@dabbelt.com, pjw@kernel.org, puranjay@kernel.org, pulehui@huawei.com, ruanjinjie@huawei.com, rkrcmar@ventanamicro.com, samuel.holland@sifive.com, sdf@fomichev.me, song@kernel.org, tglx@linutronix.de, tj@kernel.org, thuth@redhat.com, yonghong.song@linux.dev, yury.norov@gmail.com, zong.li@sifive.com Subject: [PATCH v3 1/3] riscv: remove irqflags.h inclusion in asm/bitops.h Date: Tue, 16 Dec 2025 09:47:19 +0800 Message-Id: <20251216014721.42262-2-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251216014721.42262-1-cuiyunhui@bytedance.com> References: <20251216014721.42262-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The arch/riscv/include/asm/bitops.h does not functionally require including /linux/irqflags.h. Additionally, adding arch/riscv/include/asm/percpu.h causes a circular inclusion: kernel/bounds.c ->include/linux/log2.h ->include/linux/bitops.h ->arch/riscv/include/asm/bitops.h ->include/linux/irqflags.h ->include/linux/find.h ->return val ? __ffs(val) : size; ->arch/riscv/include/asm/bitops.h The compilation log is as follows: CC kernel/bounds.s In file included from ./include/linux/bitmap.h:11, from ./include/linux/cpumask.h:12, from ./arch/riscv/include/asm/processor.h:55, from ./arch/riscv/include/asm/thread_info.h:42, from ./include/linux/thread_info.h:60, from ./include/asm-generic/preempt.h:5, from ./arch/riscv/include/generated/asm/preempt.h:1, from ./include/linux/preempt.h:79, from ./arch/riscv/include/asm/percpu.h:8, from ./include/linux/irqflags.h:19, from ./arch/riscv/include/asm/bitops.h:14, from ./include/linux/bitops.h:68, from ./include/linux/log2.h:12, from kernel/bounds.c:13: ./include/linux/find.h: In function 'find_next_bit': ./include/linux/find.h:66:30: error: implicit declaration of function '__ff= s' [-Wimplicit-function-declaration] 66 | return val ? __ffs(val) : size; | ^~~~~ Signed-off-by: Yunhui Cui Acked-by: Yury Norov (NVIDIA) --- arch/riscv/include/asm/bitops.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitop= s.h index 238092125c118..3c1a15be54d80 100644 --- a/arch/riscv/include/asm/bitops.h +++ b/arch/riscv/include/asm/bitops.h @@ -11,7 +11,6 @@ #endif /* _LINUX_BITOPS_H */ =20 #include -#include #include #include =20 --=20 2.39.5 From nobody Fri Dec 19 11:50:37 2025 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56FE128469F for ; Tue, 16 Dec 2025 01:48:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765849688; cv=none; b=cnPjfUQAeKbhyW2CCt0ZPyC1WhlUTtxiwqxNpjra/oDfvLjYWGelk70bqLXXldJcR0VBlDlP8zU6NwoNVNdPaMGZ7j0f6DWf3zZMJ5NIRPzT6vv5wMgOitVAAg8h6zZoQMBESIHVBBYpTKWd57tEobdAFXvf/Yur1OniEmnNkUE= ARC-Message-Signature: i=1; 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Mon, 15 Dec 2025 17:48:04 -0800 (PST) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.224]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c0c2c963b53sm13632790a12.36.2025.12.15.17.47.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 15 Dec 2025 17:48:02 -0800 (PST) From: Yunhui Cui To: aou@eecs.berkeley.edu, alex@ghiti.fr, andii@kernel.org, andybnac@gmail.com, apatel@ventanamicro.com, ast@kernel.org, ben.dooks@codethink.co.uk, bjorn@kernel.org, bpf@vger.kernel.org, charlie@rivosinc.com, cl@gentwo.org, conor.dooley@microchip.com, cuiyunhui@bytedance.com, cyrilbur@tenstorrent.com, daniel@iogearbox.net, debug@rivosinc.com, dennis@kernel.org, eddyz87@gmail.com, haoluo@google.com, john.fastabend@gmail.com, jolsa@kernel.org, kpsingh@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux@rasmusvillemoes.dk, martin.lau@linux.dev, palmer@dabbelt.com, pjw@kernel.org, puranjay@kernel.org, pulehui@huawei.com, ruanjinjie@huawei.com, rkrcmar@ventanamicro.com, samuel.holland@sifive.com, sdf@fomichev.me, song@kernel.org, tglx@linutronix.de, tj@kernel.org, thuth@redhat.com, yonghong.song@linux.dev, yury.norov@gmail.com, zong.li@sifive.com Subject: [PATCH v3 2/3] riscv: introduce percpu.h into include/asm Date: Tue, 16 Dec 2025 09:47:20 +0800 Message-Id: <20251216014721.42262-3-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251216014721.42262-1-cuiyunhui@bytedance.com> References: <20251216014721.42262-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Current percpu operations rely on generic implementations, where raw_local_irq_save() introduces substantial overhead. Optimization is achieved through atomic operations and preemption disabling. Currently, since RISC-V does not support lr/sc.b/h, when ZABHA is not supported, lr/sc.w needs to be used instead, which requires some additional mask operations. Signed-off-by: Yunhui Cui --- arch/riscv/include/asm/percpu.h | 244 ++++++++++++++++++++++++++++++++ 1 file changed, 244 insertions(+) create mode 100644 arch/riscv/include/asm/percpu.h diff --git a/arch/riscv/include/asm/percpu.h b/arch/riscv/include/asm/percp= u.h new file mode 100644 index 0000000000000..c5bacf6d864ee --- /dev/null +++ b/arch/riscv/include/asm/percpu.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __ASM_PERCPU_H +#define __ASM_PERCPU_H + +#include + +#include +#include +#include + +#define PERCPU_RW_OPS(sz) \ +static inline unsigned long __percpu_read_##sz(void *ptr) \ +{ \ + return READ_ONCE(*(u##sz *)ptr); \ +} \ + \ +static inline void __percpu_write_##sz(void *ptr, unsigned long val) \ +{ \ + WRITE_ONCE(*(u##sz *)ptr, (u##sz)val); \ +} + +PERCPU_RW_OPS(8) +PERCPU_RW_OPS(16) +PERCPU_RW_OPS(32) +PERCPU_RW_OPS(64) + +#define __PERCPU_AMO_OP_CASE(sfx, name, sz, amo_insn) \ +static inline void \ +__percpu_##name##_amo_case_##sz(void *ptr, unsigned long val) \ +{ \ + asm volatile ( \ + "amo" #amo_insn #sfx " zero, %[val], %[ptr]" \ + : [ptr] "+A" (*(u##sz *)ptr) \ + : [val] "r" ((u##sz)(val)) \ + : "memory"); \ +} + +#define PERCPU_OP(name, amo_insn) \ + __PERCPU_AMO_OP_CASE(.w, name, 32, amo_insn) \ + __PERCPU_AMO_OP_CASE(.d, name, 64, amo_insn) + +PERCPU_OP(add, add) +PERCPU_OP(andnot, and) +PERCPU_OP(or, or) + +/* + * Currently, only this_cpu_add_return_xxx() requires a return value, + * and the PERCPU_RET_OP() does not account for other operations. + */ +#define __PERCPU_AMO_RET_OP_CASE(sfx, name, sz, amo_insn) \ +static inline u##sz \ +__percpu_##name##_return_amo_case_##sz(void *ptr, unsigned long val) \ +{ \ + register u##sz ret; \ + \ + asm volatile ( \ + "amo" #amo_insn #sfx " %[ret], %[val], %[ptr]" \ + : [ptr] "+A" (*(u##sz *)ptr), [ret] "=3Dr" (ret) \ + : [val] "r" ((u##sz)(val)) \ + : "memory"); \ + \ + return ret + val; \ +} + +#define PERCPU_RET_OP(name, amo_insn) \ + __PERCPU_AMO_RET_OP_CASE(.w, name, 32, amo_insn) \ + __PERCPU_AMO_RET_OP_CASE(.d, name, 64, amo_insn) + +PERCPU_RET_OP(add, add) + +#define PERCPU_8_16_GET_SHIFT(ptr) (((unsigned long)(ptr) & 0x3) * BITS_PE= R_BYTE) +#define PERCPU_8_16_GET_MASK(sz) GENMASK((sz)-1, 0) +#define PERCPU_8_16_GET_PTR32(ptr) ((u32 *)((unsigned long)(ptr) & ~0x3)) + +#define PERCPU_8_16_OP(name, amo_insn, sz, sfx, val_type, new_val_expr, as= m_op) \ +static inline void __percpu_##name##_amo_case_##sz(void *ptr, unsigned lon= g val) \ +{ \ + if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA) && \ + riscv_has_extension_unlikely(RISCV_ISA_EXT_ZABHA)) { \ + asm volatile ("amo" #amo_insn #sfx " zero, %[val], %[ptr]" \ + : [ptr] "+A"(*(val_type *)ptr) \ + : [val] "r"((val_type)((new_val_expr) & PERCPU_8_16_GET_MASK(sz))) \ + : "memory"); \ + } else { \ + u32 *ptr32 =3D PERCPU_8_16_GET_PTR32(ptr); \ + const unsigned long shift =3D PERCPU_8_16_GET_SHIFT(ptr); \ + const u32 mask =3D PERCPU_8_16_GET_MASK(sz) << shift; \ + const val_type val_trunc =3D (val_type)((new_val_expr) \ + & PERCPU_8_16_GET_MASK(sz)); \ + u32 retx, rc; \ + val_type new_val_type; \ + \ + asm volatile ( \ + "0: lr.w %0, %2\n" \ + "and %3, %0, %4\n" \ + "srl %3, %3, %5\n" \ + #asm_op " %3, %3, %6\n" \ + "sll %3, %3, %5\n" \ + "and %1, %0, %7\n" \ + "or %1, %1, %3\n" \ + "sc.w %1, %1, %2\n" \ + "bnez %1, 0b\n" \ + : "=3D&r"(retx), "=3D&r"(rc), "+A"(*ptr32), "=3D&r"(new_val_type) \ + : "r"(mask), "r"(shift), "r"(val_trunc), "r"(~mask) \ + : "memory"); \ + } \ +} + +#define PERCPU_OP_8_16(op_name, op, expr, final_op) \ + PERCPU_8_16_OP(op_name, op, 8, .b, u8, expr, final_op); \ + PERCPU_8_16_OP(op_name, op, 16, .h, u16, expr, final_op) + +PERCPU_OP_8_16(add, add, val, add) +PERCPU_OP_8_16(andnot, and, ~val, and) +PERCPU_OP_8_16(or, or, val, or) + +#define PERCPU_8_16_RET_OP(name, amo_insn, sz, sfx, val_type, new_val_expr= ) \ +static inline val_type __percpu_##name##_return_amo_case_##sz(void *ptr, u= nsigned long val) \ +{ \ + if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA) && \ + riscv_has_extension_unlikely(RISCV_ISA_EXT_ZABHA)) { \ + register val_type ret; \ + asm volatile ("amo" #amo_insn #sfx " %[ret], %[val], %[ptr]" \ + : [ptr] "+A"(*(val_type *)ptr), [ret] "=3Dr"(ret) \ + : [val] "r"((val_type)((new_val_expr) & PERCPU_8_16_GET_MASK(sz))) \ + : "memory"); \ + return ret + (val_type)((new_val_expr) & PERCPU_8_16_GET_MASK(sz)); \ + } else { \ + u32 *ptr32 =3D PERCPU_8_16_GET_PTR32(ptr); \ + const unsigned long shift =3D PERCPU_8_16_GET_SHIFT(ptr); \ + const u32 mask =3D (PERCPU_8_16_GET_MASK(sz) << shift); \ + const u32 inv_mask =3D ~mask; \ + const val_type val_trunc =3D (val_type)((new_val_expr) \ + & PERCPU_8_16_GET_MASK(sz)); \ + u32 old, new, tmp; \ + \ + asm volatile ( \ + "0: lr.w %0, %3\n" \ + "and %1, %0, %4\n" \ + "srl %1, %1, %5\n" \ + "add %1, %1, %6\n" \ + "and %1, %1, %7\n" \ + "sll %1, %1, %5\n" \ + "and %2, %0, %8\n" \ + "or %2, %2, %1\n" \ + "sc.w %2, %2, %3\n" \ + "bnez %2, 0b\n" \ + : "=3Dr"(old), "=3Dr"(tmp), "=3D&r"(new), "+A"(*ptr32) \ + : "r"(mask), "r"(shift), "r"(val_trunc), "r"(PERCPU_8_16_GET_MASK(sz)),= \ + "r"(inv_mask) \ + : "memory"); \ + return (val_type)(tmp); \ + } \ +} + +PERCPU_8_16_RET_OP(add, add, 8, .b, u8, val) +PERCPU_8_16_RET_OP(add, add, 16, .h, u16, val) + +#define _pcp_protect(op, pcp, ...) \ +({ \ + preempt_disable_notrace(); \ + op(raw_cpu_ptr(&(pcp)), __VA_ARGS__); \ + preempt_enable_notrace(); \ +}) + +#define _pcp_protect_return(op, pcp, args...) \ +({ \ + typeof(pcp) __retval; \ + preempt_disable_notrace(); \ + __retval =3D (typeof(pcp))op(raw_cpu_ptr(&(pcp)), ##args); \ + preempt_enable_notrace(); \ + __retval; \ +}) + +#define this_cpu_read_1(pcp) _pcp_protect_return(__percpu_read_8, pcp) +#define this_cpu_read_2(pcp) _pcp_protect_return(__percpu_read_16, pcp) +#define this_cpu_read_4(pcp) _pcp_protect_return(__percpu_read_32, pcp) +#define this_cpu_read_8(pcp) _pcp_protect_return(__percpu_read_64, pcp) + +#define this_cpu_write_1(pcp, val) _pcp_protect(__percpu_write_8, pcp, (un= signed long)val) +#define this_cpu_write_2(pcp, val) _pcp_protect(__percpu_write_16, pcp, (u= nsigned long)val) +#define this_cpu_write_4(pcp, val) _pcp_protect(__percpu_write_32, pcp, (u= nsigned long)val) +#define this_cpu_write_8(pcp, val) _pcp_protect(__percpu_write_64, pcp, (u= nsigned long)val) + +#define this_cpu_add_1(pcp, val) _pcp_protect(__percpu_add_amo_case_8, pcp= , val) +#define this_cpu_add_2(pcp, val) _pcp_protect(__percpu_add_amo_case_16, pc= p, val) +#define this_cpu_add_4(pcp, val) _pcp_protect(__percpu_add_amo_case_32, pc= p, val) +#define this_cpu_add_8(pcp, val) _pcp_protect(__percpu_add_amo_case_64, pc= p, val) + +#define this_cpu_add_return_1(pcp, val) \ +_pcp_protect_return(__percpu_add_return_amo_case_8, pcp, val) + +#define this_cpu_add_return_2(pcp, val) \ +_pcp_protect_return(__percpu_add_return_amo_case_16, pcp, val) + +#define this_cpu_add_return_4(pcp, val) \ +_pcp_protect_return(__percpu_add_return_amo_case_32, pcp, val) + +#define this_cpu_add_return_8(pcp, val) \ +_pcp_protect_return(__percpu_add_return_amo_case_64, pcp, val) + +#define this_cpu_and_1(pcp, val) _pcp_protect(__percpu_andnot_amo_case_8, = pcp, ~val) +#define this_cpu_and_2(pcp, val) _pcp_protect(__percpu_andnot_amo_case_16,= pcp, ~val) +#define this_cpu_and_4(pcp, val) _pcp_protect(__percpu_andnot_amo_case_32,= pcp, ~val) +#define this_cpu_and_8(pcp, val) _pcp_protect(__percpu_andnot_amo_case_64,= pcp, ~val) + +#define this_cpu_or_1(pcp, val) _pcp_protect(__percpu_or_amo_case_8, pcp, = val) +#define this_cpu_or_2(pcp, val) _pcp_protect(__percpu_or_amo_case_16, pcp,= val) +#define this_cpu_or_4(pcp, val) _pcp_protect(__percpu_or_amo_case_32, pcp,= val) +#define this_cpu_or_8(pcp, val) _pcp_protect(__percpu_or_amo_case_64, pcp,= val) + +#define this_cpu_xchg_1(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, v= al) +#define this_cpu_xchg_2(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, v= al) +#define this_cpu_xchg_4(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, v= al) +#define this_cpu_xchg_8(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, v= al) + +#define this_cpu_cmpxchg_1(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed,= pcp, o, n) +#define this_cpu_cmpxchg_2(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed,= pcp, o, n) +#define this_cpu_cmpxchg_4(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed,= pcp, o, n) +#define this_cpu_cmpxchg_8(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed,= pcp, o, n) + +#define this_cpu_cmpxchg64(pcp, o, n) this_cpu_cmpxchg_8(pcp, o, n) + +#ifdef system_has_cmpxchg128 +#define this_cpu_cmpxchg128(pcp, o, n) \ +({ \ + u128 ret__; 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Mon, 15 Dec 2025 17:48:16 -0800 (PST) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.224]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c0c2c963b53sm13632790a12.36.2025.12.15.17.48.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 15 Dec 2025 17:48:16 -0800 (PST) From: Yunhui Cui To: aou@eecs.berkeley.edu, alex@ghiti.fr, andii@kernel.org, andybnac@gmail.com, apatel@ventanamicro.com, ast@kernel.org, ben.dooks@codethink.co.uk, bjorn@kernel.org, bpf@vger.kernel.org, charlie@rivosinc.com, cl@gentwo.org, conor.dooley@microchip.com, cuiyunhui@bytedance.com, cyrilbur@tenstorrent.com, daniel@iogearbox.net, debug@rivosinc.com, dennis@kernel.org, eddyz87@gmail.com, haoluo@google.com, john.fastabend@gmail.com, jolsa@kernel.org, kpsingh@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux@rasmusvillemoes.dk, martin.lau@linux.dev, palmer@dabbelt.com, pjw@kernel.org, puranjay@kernel.org, pulehui@huawei.com, ruanjinjie@huawei.com, rkrcmar@ventanamicro.com, samuel.holland@sifive.com, sdf@fomichev.me, song@kernel.org, tglx@linutronix.de, tj@kernel.org, thuth@redhat.com, yonghong.song@linux.dev, yury.norov@gmail.com, zong.li@sifive.com Subject: [PATCH v3 3/3] riscv: store percpu offset into thread_info Date: Tue, 16 Dec 2025 09:47:21 +0800 Message-Id: <20251216014721.42262-4-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251216014721.42262-1-cuiyunhui@bytedance.com> References: <20251216014721.42262-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Originally we planned to add a register for the percpu offset, which would speed up percpu variable R/W and reduce access instructions. After discussion [1], it=E2=80=99s now stored in thread_info. [1] https://lists.riscv.org/g/tech-privileged/topic/risc_v_tech_arch_review= /113437553?page=3D2 Signed-off-by: Yunhui Cui --- arch/riscv/include/asm/asm.h | 6 +----- arch/riscv/include/asm/percpu.h | 4 ++++ arch/riscv/include/asm/switch_to.h | 8 ++++++++ arch/riscv/include/asm/thread_info.h | 5 +++-- arch/riscv/kernel/asm-offsets.c | 1 + arch/riscv/kernel/smpboot.c | 7 +++++++ arch/riscv/net/bpf_jit_comp64.c | 9 +-------- 7 files changed, 25 insertions(+), 15 deletions(-) diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h index e9e8ba83e632f..137a49488325e 100644 --- a/arch/riscv/include/asm/asm.h +++ b/arch/riscv/include/asm/asm.h @@ -91,11 +91,7 @@ =20 #ifdef CONFIG_SMP .macro asm_per_cpu dst sym tmp - lw \tmp, TASK_TI_CPU_NUM(tp) - slli \tmp, \tmp, RISCV_LGPTR - la \dst, __per_cpu_offset - add \dst, \dst, \tmp - REG_L \tmp, 0(\dst) + REG_L \tmp, TASK_TI_PCPU_OFFSET(tp) la \dst, \sym add \dst, \dst, \tmp .endm diff --git a/arch/riscv/include/asm/percpu.h b/arch/riscv/include/asm/percp= u.h index c5bacf6d864ee..35a63420a76a4 100644 --- a/arch/riscv/include/asm/percpu.h +++ b/arch/riscv/include/asm/percpu.h @@ -7,7 +7,9 @@ =20 #include #include +#include #include +#include =20 #define PERCPU_RW_OPS(sz) \ static inline unsigned long __percpu_read_##sz(void *ptr) \ @@ -239,6 +241,8 @@ _pcp_protect_return(__percpu_add_return_amo_case_64, pc= p, val) }) #endif =20 +#define __my_cpu_offset (((struct thread_info *)current)->pcpu_offset) + #include =20 #endif /* __ASM_PERCPU_H */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 0e71eb82f920c..733b6cd306e40 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -88,6 +88,13 @@ static inline void __switch_to_envcfg(struct task_struct= *next) :: "r" (next->thread.envcfg) : "memory"); } =20 +static inline void __switch_to_pcpu_offset(struct task_struct *next) +{ +#ifdef CONFIG_SMP + next->thread_info.pcpu_offset =3D __my_cpu_offset; +#endif +} + extern struct task_struct *__switch_to(struct task_struct *, struct task_struct *); =20 @@ -122,6 +129,7 @@ do { \ if (switch_to_should_flush_icache(__next)) \ local_flush_icache_all(); \ __switch_to_envcfg(__next); \ + __switch_to_pcpu_offset(__next); \ ((last) =3D __switch_to(__prev, __next)); \ } while (0) =20 diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/= thread_info.h index 36918c9200c92..8d7d43cc9c405 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -52,7 +52,8 @@ */ struct thread_info { unsigned long flags; /* low level flags */ - int preempt_count; /* 0=3D>preemptible, <0=3D>BUG */ + int preempt_count; /* 0=3D>preemptible, <0=3D>BUG */ + int cpu; /* * These stack pointers are overwritten on every system call or * exception. SP is also saved to the stack it can be recovered when @@ -60,8 +61,8 @@ struct thread_info { */ long kernel_sp; /* Kernel stack pointer */ long user_sp; /* User stack pointer */ - int cpu; unsigned long syscall_work; /* SYSCALL_WORK_ flags */ + unsigned long pcpu_offset; #ifdef CONFIG_SHADOW_CALL_STACK void *scs_base; void *scs_sp; diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offset= s.c index af827448a609e..fbf53b66b0e06 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -38,6 +38,7 @@ void asm_offsets(void) OFFSET(TASK_THREAD_SUM, task_struct, thread.sum); =20 OFFSET(TASK_TI_CPU, task_struct, thread_info.cpu); + OFFSET(TASK_TI_PCPU_OFFSET, task_struct, thread_info.pcpu_offset); OFFSET(TASK_TI_PREEMPT_COUNT, task_struct, thread_info.preempt_count); OFFSET(TASK_TI_KERNEL_SP, task_struct, thread_info.kernel_sp); OFFSET(TASK_TI_USER_SP, task_struct, thread_info.user_sp); diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index d85916a3660c3..9e95c068b966b 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -209,6 +209,11 @@ int __cpu_up(unsigned int cpu, struct task_struct *tid= le) } #endif =20 +void __init smp_prepare_boot_cpu(void) +{ + __my_cpu_offset =3D per_cpu_offset(smp_processor_id()); +} + void __init smp_cpus_done(unsigned int max_cpus) { } @@ -234,6 +239,8 @@ asmlinkage __visible void smp_callin(void) mmgrab(mm); current->active_mm =3D mm; =20 + __my_cpu_offset =3D per_cpu_offset(smp_processor_id()); + #ifdef CONFIG_HOTPLUG_PARALLEL cpuhp_ap_sync_alive(); #endif diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp6= 4.c index 5f9457e910e87..4a492a6a1cc1e 100644 --- a/arch/riscv/net/bpf_jit_comp64.c +++ b/arch/riscv/net/bpf_jit_comp64.c @@ -1345,15 +1345,8 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, s= truct rv_jit_context *ctx, if (rd !=3D rs) emit_mv(rd, rs, ctx); #ifdef CONFIG_SMP - /* Load current CPU number in T1 */ - emit_lw(RV_REG_T1, offsetof(struct thread_info, cpu), + emit_lw(RV_REG_T1, offsetof(struct thread_info, pcpu_offset), RV_REG_TP, ctx); - /* Load address of __per_cpu_offset array in T2 */ - emit_addr(RV_REG_T2, (u64)&__per_cpu_offset, extra_pass, ctx); - /* Get address of __per_cpu_offset[cpu] in T1 */ - emit_sh3add(RV_REG_T1, RV_REG_T1, RV_REG_T2, ctx); - /* Load __per_cpu_offset[cpu] in T1 */ - emit_ld(RV_REG_T1, 0, RV_REG_T1, ctx); /* Add the offset to Rd */ emit_add(rd, rd, RV_REG_T1, ctx); #endif --=20 2.39.5