From nobody Thu Dec 18 01:37:29 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8405737C0E8 for ; Tue, 16 Dec 2025 12:52:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765889531; cv=none; b=kCqFO/ZJNfK7lkVCc4Oc0S56QK/6lJYrq6nj5EFPJeePUaQcEWHK/HNG6mL+MSyvpPBe1JttvCOdR2Js+R4ygMkTJZ9kpxwnmKKQEOmtwPvA5XUEGwBH2cC7aoSQeUkQ32jx9Wvat96fhuwKo6oe2bGSusl++43ho+bt9NPyscY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765889531; c=relaxed/simple; bh=AxJppRgcYa8seS/5FsyKFOOD0QXwFKTptF3sj3pGcEs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BviGN2xJuIbLZcJhAVxtOyoTKa5dhneyO5W24EpJ8vR77OVfAZ/kVRk3Vu/ScmhhUh0/geVoNvkRZWgcM6opQa2HuuOll/6Z6joRwwdgccBTwd5N2RL525zbeYZWLSBk1tY559g99hlOeF/YU3YfqendC272BwbnwLNs24POp14= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ZKpNU2Gg; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=BNetlMAj; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ZKpNU2Gg"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="BNetlMAj" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BGAMAcG3829469 for ; Tue, 16 Dec 2025 12:52:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= dPioBKyHQGix4/YkwPml8E9/ulH+evd13A8ZjC482MI=; b=ZKpNU2GgQhVzPtRE VyJ0bs2Hopws9cMrlj2lCNHj4YzqYvE26SvEByfi7kqFoPuXV+y6/IFmgnboIUnB q/SFIEVLEr4ZeqcieS8iYy+LfNOb7lPKAWcVmW9/8Rdi+lfJugJC/UoeM2+94gPT 7D5vDzuAdzMGxZflVXoRE74lYx3qu1ClcJR4rKRVCLkTkKfHcv2/Cvy2MmTygvp0 Y0EGb0QigYvzCSFJVipH8YUMw6eNUa54LDkP1aoLUEq2gauwcav9H6g2Vpa/Bsr7 Kxac1cJyhI9kMqal6QTURFRQDmIBGE4KemmLK/B4xbC9KY6R6CmOLCvEgda4r6ru eeqgtA== Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b35m2rh3y-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 16 Dec 2025 12:52:04 +0000 (GMT) Received: by mail-pf1-f197.google.com with SMTP id d2e1a72fcca58-7b9321b9312so9264808b3a.1 for ; Tue, 16 Dec 2025 04:52:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1765889523; x=1766494323; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dPioBKyHQGix4/YkwPml8E9/ulH+evd13A8ZjC482MI=; b=BNetlMAjOXETgcVFMOUrvPA43ebJRY4tmIQFByqc8MKz/5Fx0YbL4A3Oc0+0NGhyQ1 +HiKU/NHmNYQmRtNE4M4KMMsrz1g92In66C9h+Ywq4a3KpMLwpIND1aMOZGDDbnpifDh ssGzHCtjBzflCbkQcZQ/hAwpREa1UYjgn2pEAwhI7ZECK+Rw/CmKYCT8VIq7hfEiDzhs +TtQeaXrRb4gEdSx+c8F9wjGd2lLrUuMGBS2yV83R7LGiJ07mxWNdqVem+tLBW3wOdlU ocHKip0dh/l3ZbutrONmyAvUoREKr1eSs/+Sq4kcB/e1U3k2EkA+ahC91kckJ7R8vqZs P1Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765889523; x=1766494323; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=dPioBKyHQGix4/YkwPml8E9/ulH+evd13A8ZjC482MI=; b=Q0itYoxdeLYN7ceQ6u1Q7zcYHxhkkm+Z76H3+wi5fT+R47KpmcaCTj3bkhpJOCXQgj VCwUojerJDJfcpECkE4GjnEX+6KeEuHCuC1kS0XHiBX9VvbMsYYJrScEo6SHqLR0UuTC B2f2pdifWZdVEM2h0Gu5i+zjRZe4/ZlmJFlDU+trWWPuMI37npUlHyf5P1ssACmDxsiN 70fR6lticWmSeotFiFVcqTOPdxNxy6nvfPhmBNNxHckBtpqflTvtyh/YNQZ/D30VGRJw 28joXI1X/xXfrL8iGRVP5Q0MwFqeQTDHS3d8LCy1kwsONAeJMo9AYmwd8tPONGWLXZea htBg== X-Forwarded-Encrypted: i=1; AJvYcCWnwMhCs9CmZ3mf2i0R/IUOwOvFgGgGd3poL/UXb2/Lm2uNZ5EIwAdJoJmlRYQyi/Z1zwb0l8uiR9AeQ78=@vger.kernel.org X-Gm-Message-State: AOJu0YxEI1uogZDbHFqjlynMb0S91HkwZNzETwqCfW/GqcQiPg/SfcOm 7LSLt2RFleHlFbfSkOys7fdYZPANAZe90S6JnUx4A9XnedXnlBy+5/IcrEd2VyXJocs9B2bC40j mfHa+k8tN/x8aMzCl9VfIXiQyIDdNPuUMXU38Ls1/Cqjq/yGKC5PW2yym1o8xegg0tEtH39wO5s o= X-Gm-Gg: AY/fxX7aTf+nNNFzWQP3FSAtbR9RYqzNAHQYRk+n6JzVAPIUPl7OoW4hRSqpgHK5rco qeQ9VTKK4rqYvK0XtaarCldCJVPKdcID+4uD5w3wSTmDvwr0mO9jLBTgMNFZXUguQzpXjVs6UvQ 5j0P8p9dUEoPal/50YRS/tyl+EBedms1GCuSQKs5e9pG+sDtjuhKVaRw27slg9KMleNnFC5ozvE tAQ4OkjkP4/CTUclDf/aVi6LlMAmu+QGDTtjw1Bd0jacTQMKB+59mWGOZYkBMmNYTjw5EqMmXuq dsylobolY2ChurNxh+/55S8GbOC9kbf3n05EJyjm4PoWRItvr91i/mEGe/E6HwbSR3Crn5VGzas 3rKuo0rbEyI3UQjGGOV2om9xXBac+jNTIi0aPltmwAQ== X-Received: by 2002:a05:6a00:6ca1:b0:7a2:6b48:5359 with SMTP id d2e1a72fcca58-7f6679368f6mr14489946b3a.24.1765889523107; Tue, 16 Dec 2025 04:52:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IEPl3d2KGIwILstUtASrOvLk2LZLE7T3dGcnoLQpDR2FH5CrqA1YrdJ4MrgZdloc/MaQQoM9A== X-Received: by 2002:a05:6a00:6ca1:b0:7a2:6b48:5359 with SMTP id d2e1a72fcca58-7f6679368f6mr14489922b3a.24.1765889522561; Tue, 16 Dec 2025 04:52:02 -0800 (PST) Received: from [192.168.1.102] ([117.193.213.190]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7f5ab7d87e8sm13634362b3a.25.2025.12.16.04.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Dec 2025 04:52:02 -0800 (PST) From: Manivannan Sadhasivam Date: Tue, 16 Dec 2025 18:21:43 +0530 Subject: [PATCH v2 1/5] PCI: qcom: Parse PERST# from all PCIe bridge nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251216-pci-pwrctrl-rework-v2-1-745a563b9be6@oss.qualcomm.com> References: <20251216-pci-pwrctrl-rework-v2-0-745a563b9be6@oss.qualcomm.com> In-Reply-To: <20251216-pci-pwrctrl-rework-v2-0-745a563b9be6@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Bartosz Golaszewski , Bartosz Golaszewski Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai , Brian Norris , Krishna Chaitanya Chundru , Niklas Cassel , Alex Elder , Manivannan Sadhasivam , Chen-Yu Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7502; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=AxJppRgcYa8seS/5FsyKFOOD0QXwFKTptF3sj3pGcEs=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpQVXoQKinTJXtBmgeKHf4UWzgeJqWHOAIYLFSR fFrXeGG9SuJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaUFV6AAKCRBVnxHm/pHO 9S0iCACSdGQz8geJOBd+d9udFswEfStON+sBAnT6wzMEECy6Kx+Rppz/rDrJPKnGd6WwR6Uc+YP WwUAdjI5aP24oqU5to62e1QRLJUZNLw09b00qEqoflK+erOs1c08/cVLB/pRRAAHktO+RBDsVTe 1uTBLgY0SyATW4UlZSBcxQBUtTPdC12BslroOCVnfaRYyWeeZmHqYVNq/s6VcTrKI41tKScaH1T PMio5rP/1PWrHzOSXXXaYLjlFzcTBzUkfZkuyfU9BUbMtOcs4vqrojL95bRWLEdzMEZfNBHn2Cd W7Y31pKSo9KpFO2YPEhA/4NjEibNLtCrXxqFcxbcBfnxgTgS X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Authority-Analysis: v=2.4 cv=LpGfC3dc c=1 sm=1 tr=0 ts=694155f4 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=wnJ2AIBC+6MZbTdryK78rQ==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=cm27Pg_UAAAA:8 a=EUspDBNiAAAA:8 a=xvucdaCnflZx_vE3ezEA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-GUID: kvLwUlNPZTanU3y11V0gV1hBAlcXAaVU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE2MDEwOSBTYWx0ZWRfXzhP4OuzhqCtX +EDt2QXJyW3utcXL8t2TWNxW5NyvHCJcKs21bX7GsjH+lCKLp8d06u+LPdigvkLhuJlVkaoEdyr dt7mXjNgb9LZO7HxzUwaH4qSNIv154MLUlqCY7hEs73oGQ3te3ojiBZMTDDeJedye8BudA7WxVt D1Q11eEpiiGvfV2NLzDbG9rh5sdIi8EX/nJ56mRohNO/d9AyMqvAkj+Pvg5on0y6Ir2bEX2Skj5 RpvSaCQqfBgtnwM4SembgliajJpAq8LwBNR5ZjuWyvl2P59jH71qntMsWmyyBmX5SYa5YkcnbM1 Tz7gWyqzr/D8OC61siVcvQ9lr6lmyG33OOwd6L1/bW3D8l0GILSgx9VbxFghUNfQ5acrS+qUuHT y9gmNgr8GaEKaJVuDpgAtFbYNNoruw== X-Proofpoint-ORIG-GUID: kvLwUlNPZTanU3y11V0gV1hBAlcXAaVU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-16_02,2025-12-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 phishscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 spamscore=0 bulkscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512160109 Devicetree schema allows the PERST# GPIO to be present in all PCIe bridge nodes, not just in Root Port node. But the current logic parses PERST# only from the Root Port nodes. Though it is not causing any issue on the current platforms, the upcoming platforms will have PERST# in PCIe switch downstream ports also. So this requires parsing all the PCIe bridge nodes for the PERST# GPIO. Hence, rework the parsing logic to extend to all PCIe bridge nodes starting from the Root Port node. If the 'reset-gpios' property is found for a PCI bridge node, the GPIO descriptor will be stored in qcom_pcie_perst::desc and added to the qcom_pcie_port::perst list. It should be noted that if more than one bridge node has the same GPIO for PERST# (shared PERST#), the driver will error out. This is due to the limitation in the GPIOLIB subsystem that allows only exclusive (non-shared) access to GPIOs from consumers. But this is soon going to get fixed. Once that happens, it will get incorporated in this driver. So for now, PERST# sharing is not supported. Tested-by: Chen-Yu Tsai Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 102 +++++++++++++++++++++++++++--= ---- 1 file changed, 85 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 7b92e7a1c0d9..73032449d289 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -267,10 +267,15 @@ struct qcom_pcie_cfg { bool no_l0s; }; =20 +struct qcom_pcie_perst { + struct list_head list; + struct gpio_desc *desc; +}; + struct qcom_pcie_port { struct list_head list; - struct gpio_desc *reset; struct phy *phy; + struct list_head perst; }; =20 struct qcom_pcie { @@ -291,11 +296,14 @@ struct qcom_pcie { =20 static void qcom_perst_assert(struct qcom_pcie *pcie, bool assert) { + struct qcom_pcie_perst *perst; struct qcom_pcie_port *port; int val =3D assert ? 1 : 0; =20 - list_for_each_entry(port, &pcie->ports, list) - gpiod_set_value_cansleep(port->reset, val); + list_for_each_entry(port, &pcie->ports, list) { + list_for_each_entry(perst, &port->perst, list) + gpiod_set_value_cansleep(perst->desc, val); + } =20 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); } @@ -1702,18 +1710,58 @@ static const struct pci_ecam_ops pci_qcom_ecam_ops = =3D { } }; =20 -static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node= *node) +/* Parse PERST# from all nodes in depth first manner starting from @np */ +static int qcom_pcie_parse_perst(struct qcom_pcie *pcie, + struct qcom_pcie_port *port, + struct device_node *np) { struct device *dev =3D pcie->pci->dev; - struct qcom_pcie_port *port; + struct qcom_pcie_perst *perst; struct gpio_desc *reset; - struct phy *phy; int ret; =20 - reset =3D devm_fwnode_gpiod_get(dev, of_fwnode_handle(node), - "reset", GPIOD_OUT_HIGH, "PERST#"); - if (IS_ERR(reset)) + if (!of_find_property(np, "reset-gpios", NULL)) + goto parse_child_node; + + reset =3D devm_fwnode_gpiod_get(dev, of_fwnode_handle(np), "reset", + GPIOD_OUT_HIGH, "PERST#"); + if (IS_ERR(reset)) { + /* + * FIXME: GPIOLIB currently supports exclusive GPIO access only. + * Non exclusive access is broken. But shared PERST# requires + * non-exclusive access. So once GPIOLIB properly supports it, + * implement it here. + */ + if (PTR_ERR(reset) =3D=3D -EBUSY) + dev_err(dev, "Shared PERST# is not supported\n"); + return PTR_ERR(reset); + } + + perst =3D devm_kzalloc(dev, sizeof(*perst), GFP_KERNEL); + if (!perst) + return -ENOMEM; + + INIT_LIST_HEAD(&perst->list); + perst->desc =3D reset; + list_add_tail(&perst->list, &port->perst); + +parse_child_node: + for_each_available_child_of_node_scoped(np, child) { + ret =3D qcom_pcie_parse_perst(pcie, port, child); + if (ret) + return ret; + } + + return 0; +} + +static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node= *node) +{ + struct device *dev =3D pcie->pci->dev; + struct qcom_pcie_port *port; + struct phy *phy; + int ret; =20 phy =3D devm_of_phy_get(dev, node, NULL); if (IS_ERR(phy)) @@ -1727,7 +1775,12 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pc= ie, struct device_node *node if (ret) return ret; =20 - port->reset =3D reset; + INIT_LIST_HEAD(&port->perst); + + ret =3D qcom_pcie_parse_perst(pcie, port, node); + if (ret) + return ret; + port->phy =3D phy; INIT_LIST_HEAD(&port->list); list_add_tail(&port->list, &pcie->ports); @@ -1737,9 +1790,10 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pc= ie, struct device_node *node =20 static int qcom_pcie_parse_ports(struct qcom_pcie *pcie) { + struct qcom_pcie_perst *perst, *tmp_perst; + struct qcom_pcie_port *port, *tmp_port; struct device *dev =3D pcie->pci->dev; - struct qcom_pcie_port *port, *tmp; - int ret =3D -ENOENT; + int ret =3D -ENODEV; =20 for_each_available_child_of_node_scoped(dev->of_node, of_port) { if (!of_node_is_type(of_port, "pci")) @@ -1752,7 +1806,9 @@ static int qcom_pcie_parse_ports(struct qcom_pcie *pc= ie) return ret; =20 err_port_del: - list_for_each_entry_safe(port, tmp, &pcie->ports, list) { + list_for_each_entry_safe(port, tmp_port, &pcie->ports, list) { + list_for_each_entry_safe(perst, tmp_perst, &port->perst, list) + list_del(&perst->list); phy_exit(port->phy); list_del(&port->list); } @@ -1763,6 +1819,7 @@ static int qcom_pcie_parse_ports(struct qcom_pcie *pc= ie) static int qcom_pcie_parse_legacy_binding(struct qcom_pcie *pcie) { struct device *dev =3D pcie->pci->dev; + struct qcom_pcie_perst *perst; struct qcom_pcie_port *port; struct gpio_desc *reset; struct phy *phy; @@ -1784,19 +1841,28 @@ static int qcom_pcie_parse_legacy_binding(struct qc= om_pcie *pcie) if (!port) return -ENOMEM; =20 - port->reset =3D reset; + perst =3D devm_kzalloc(dev, sizeof(*perst), GFP_KERNEL); + if (!perst) + return -ENOMEM; + port->phy =3D phy; INIT_LIST_HEAD(&port->list); list_add_tail(&port->list, &pcie->ports); =20 + perst->desc =3D reset; + INIT_LIST_HEAD(&port->perst); + INIT_LIST_HEAD(&perst->list); + list_add_tail(&perst->list, &port->perst); + return 0; } =20 static int qcom_pcie_probe(struct platform_device *pdev) { + struct qcom_pcie_perst *perst, *tmp_perst; + struct qcom_pcie_port *port, *tmp_port; const struct qcom_pcie_cfg *pcie_cfg; unsigned long max_freq =3D ULONG_MAX; - struct qcom_pcie_port *port, *tmp; struct device *dev =3D &pdev->dev; struct dev_pm_opp *opp; struct qcom_pcie *pcie; @@ -1937,7 +2003,7 @@ static int qcom_pcie_probe(struct platform_device *pd= ev) =20 ret =3D qcom_pcie_parse_ports(pcie); if (ret) { - if (ret !=3D -ENOENT) { + if (ret !=3D -ENODEV) { dev_err_probe(pci->dev, ret, "Failed to parse Root Port: %d\n", ret); goto err_pm_runtime_put; @@ -1996,7 +2062,9 @@ static int qcom_pcie_probe(struct platform_device *pd= ev) err_host_deinit: dw_pcie_host_deinit(pp); err_phy_exit: - list_for_each_entry_safe(port, tmp, &pcie->ports, list) { + list_for_each_entry_safe(port, tmp_port, &pcie->ports, list) { + list_for_each_entry_safe(perst, tmp_perst, &port->perst, list) + list_del(&perst->list); phy_exit(port->phy); list_del(&port->list); } --=20 2.48.1 From nobody Thu Dec 18 01:37:29 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E03B393775 for ; Tue, 16 Dec 2025 12:52:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765889533; cv=none; b=Cm6NpkT1zf072DpQ2rn0cRD5o0m4FCSYnnd+WLhh4UjEdkdnO/JGDU6ae+cUSVTSTt+3biXFNE6IXmeXpBNLkemHtsklHIV62W7RFYFULnPgXv/T7gS+aNqVJZS3AWqplLlKZ/7RjThU8UWEXwcG8IaVnjLsy1PaNn1xmDlTaD8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765889533; c=relaxed/simple; bh=hImE7GQrCuzWz+LCETc8MWiZwVHo4qo/PyPQSktScRQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VNYUVd5Oo5ynrgmYxG+XuwePkcghibKLd+fbR4X39xrP395Um36Sk5imb+9gjWRoFx5qBw2CDjjf0VK+b9ivjh5XSCykRiuN0+W4u/b0h75b/xAtu5V+Q0JdQ2N4dFdPh4uyl2jvW0noQQFibXZIRyDaKvXveBc9tlhmAAVAqds= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=LraelETJ; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=SdWRJtTo; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="LraelETJ"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="SdWRJtTo" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BGB1pZZ018800 for ; Tue, 16 Dec 2025 12:52:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= jy1598yUJqUvu+a7XgM5cYaI53QGia/dl9hRsBk1Zhk=; b=LraelETJ8uHo7rm4 z4g4tkiP9GsG63ZX40EEg9dp74yWZzTsQxlpy/Wdd7YKtnIxgiljEyrERjtMzRP2 +N+8951XtOPmYmyZjuMjBRbcp/UWyEuoO68sKZRMevXlX0AmJ08zOvCEGcid957k JtTjS4jwxezJeRngiOiuhh9ln5c1/xzX7O2v9xWf/bNru/VGOKkTDAW3T8qwRFbP IRiTMUPLOFXV16Fo+eJoVLy/9IdLcSIoilf+H5fRaHzk72uG2FKRjX6cwAugdDP0 txKVKow35q73dEoYkIVsaGggSG9hs+LRzMsGBWolR389bCIdWp3nwKTuSxhVX5XU iCFwow== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b366q8bba-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 16 Dec 2025 12:52:09 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-7b9ef46df43so4791893b3a.1 for ; Tue, 16 Dec 2025 04:52:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1765889528; x=1766494328; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jy1598yUJqUvu+a7XgM5cYaI53QGia/dl9hRsBk1Zhk=; b=SdWRJtToHDKUJnxPXXehCof0yjpAwLxywQzxdghGgJ84FTEpt8OkvaerVd8ZeQMLZ/ yrXons8Kevo9DSER7ZuKQCNPTryipxAO9e7gaoirbcy22kIYvf80sTqXYkSVV8yJ1OC3 uEAQmoqyFDZkDCSMRlGJkeCHgwdiT9iAGhR3QArA3VTtSuM1BHwJ4cyAn+YEfoJLWenQ 1D5M77ewz3kap1DPgnKeE2cFJfFEerAJzCZk8+c9tbbVFYHUAowlLUXSfINACPuPIX0J lkIn8WvGVW9yYT0SD2PouHLFnVnPRdmc0SnKy6YbrZkaeWHfKCuJxKevHheYqICkSYMS PMZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765889528; x=1766494328; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=jy1598yUJqUvu+a7XgM5cYaI53QGia/dl9hRsBk1Zhk=; b=ULGTT4Cn0HaKl0+KdvABblZtDEb50PbJVeWnokzxijLAZxhAXlBamMQIVPBxZyPa8S m+xeKxuDtaoXoehF85W6zT478xaMohql9Cm5kxOTOGPpqcgAoDtgcQu625wR/3COi2MU EWtExS5i/LdCCAcKbZCqkFYiL3vFYa5yI7lvgqy7Ym2n/Kmgi5Mj7BvcH8HP6epsxT5M rJ+S/opbJkY2jk3vQWF8kWD/oD9hvrdzHQGXdexhdcDnfXsal/lJdZEw3o0mCdItk8L/ pnJf8U1+vapQSSLRBv6ehsQzxhXZVLaFD73b4c4K+YEskvQfGd9r8oFomyNsnjGZV30Q eMtA== X-Forwarded-Encrypted: i=1; AJvYcCXEeM2gVi8EtKrNIZEpgq04c154Dyhq4TUs86GrVM1+plw1dTH76ZpQRevdw+4cfkni1FZ0lFn6LlX8rqg=@vger.kernel.org X-Gm-Message-State: AOJu0YzQOs1mWsyAiE936f7fTH8ByxC2wjp/9uzakp6Di6hKQvcXw/d6 TEES519/spj2gzgPC0XlsSN0oMWLL3ZfqzvMpgKTxRGVURIdULo0PsY4PoiY8+NDrmCq9s3isTM CwWXNo7deJZWOskjM7Zyo/oRnwLB7FA/Po5MSK8CtBA9gUhszQwLTgw35cDbliBAqe80TR5lshY o= X-Gm-Gg: AY/fxX5Ny1GRX69PNQl74RqQUVHhJoBAE2k2b8Ia9t7/QKZLe4Y1+ipAKukm2fMW6Ee m2S9p1SY2FquAz+0X8fwJUSxIg1TwJZNyWi6c644AFctdlaoe8bWEWPBplrb58p9ufbUpMd3dLv 73o0SN8BnLWXyV7gdVrO5rX2e5F9K9EcxY/3YmAXu2Qm+ehquBQK10uGXg/noPiNIjexWGHt7Za CB9VcOyu2z0wLgYb01uve3Wd8Z9spMrY/EvrbKggaKKbAeE6YBwN+J3XToIfqteclk+nIIy92s4 ewwm6X+vJQqLdqbfXbz2VXrx80ekn7C/dcv6YItsw3ok4cUnlvO1v8svxopGw1FEMfI7fbJHv90 Evmhpbd8Eb4Hn8zqvAMp1aL3ZiMyILEzLkCyjIQIioA== X-Received: by 2002:a05:6a20:939f:b0:35e:4017:3f32 with SMTP id adf61e73a8af0-369afa0f149mr12539063637.38.1765889528345; Tue, 16 Dec 2025 04:52:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IHjzD7R4uaZ9Cp8BC5PKe+O45asaEaN2RWQgZGhm1UDQOaN2oNuTVDcVsFmdwaYr/60winWHA== X-Received: by 2002:a05:6a20:939f:b0:35e:4017:3f32 with SMTP id adf61e73a8af0-369afa0f149mr12539021637.38.1765889527748; Tue, 16 Dec 2025 04:52:07 -0800 (PST) Received: from [192.168.1.102] ([117.193.213.190]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7f5ab7d87e8sm13634362b3a.25.2025.12.16.04.52.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Dec 2025 04:52:07 -0800 (PST) From: Manivannan Sadhasivam Date: Tue, 16 Dec 2025 18:21:44 +0530 Subject: [PATCH v2 2/5] PCI/pwrctrl: Add 'struct pci_pwrctrl::power_{on/off}' callbacks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251216-pci-pwrctrl-rework-v2-2-745a563b9be6@oss.qualcomm.com> References: <20251216-pci-pwrctrl-rework-v2-0-745a563b9be6@oss.qualcomm.com> In-Reply-To: <20251216-pci-pwrctrl-rework-v2-0-745a563b9be6@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Bartosz Golaszewski , Bartosz Golaszewski Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai , Brian Norris , Krishna Chaitanya Chundru , Niklas Cassel , Alex Elder , Manivannan Sadhasivam , Chen-Yu Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6339; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=hImE7GQrCuzWz+LCETc8MWiZwVHo4qo/PyPQSktScRQ=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpQVXoI2KPJRcOdMTIipPr6Ud1/OJHbwdy8AEwn Nrm5E+vwmmJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaUFV6AAKCRBVnxHm/pHO 9XVsB/9YvZIzl+Mywl3tkwyVsxgkXlZ9ldkwCpfjg+sz0vqfzO5ed+Cs6GDQIu//5Hw3WQcPsZD J/8Ef4P8D7KSwduDxa7aVa+8z+iLWcTsbqZjFbz+2nbSCZUqCbkybLtWt72nk9bBLFOJ54y4W2g rFINTSID4Dk9sFaDSyBwKHoP4ZIbsRlSaLItUCICHGGpwur1d/88YH2orCf4K9VIETbVa8TCcYv ZBMJti2YogCB9erkpZXJDi/Dco5bYpDoWpm7zTmuWmBHomp40SacXsAyyOJOB/DKAsaQRmtTxdS fiGqx7ZHW3nT+KpiHGi8Q8rgwUqY2ev0qaVTa3zujXF82nix X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Proofpoint-GUID: coeKx68ZdsKRAWA5l-Qy2VpJh9GIVDis X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE2MDEwOSBTYWx0ZWRfX6PMFiCcIS8pt NPLx8W0SzrqGs1t7amiN3gwzk9j/hLeBezo9mjdLv270fjjfs9LnByLuBuh8rT4d5lx6pdV/sB7 r9q4nnnJDhikG3KTy1UBVEL1LVjkaveckMF5mjNKKo5AGOy6AhoSa6AsA9ZQg2gnS/3VIQG/DZ7 SM5KWcyryHdaI2ZeAn3b/mwMkXYZir8xJnpv+FrOGgFDrV/r0/ygREsqQNSfJQMsMGIfS0Rxd7C pzVb1bnINiQkautGQqXDphdeBtmL0Bz8JYuSzd++CfSrQEwv7rOQY6rREeXnouClRcty7hRltqv miiJ8ABv+OcDToGG7JQwgImWmjO0HYTFBDn9zHuKYTXcWxIV0dpRFuL48nabogTom6PekExAHBW 7zf5EZZ+WGyexAGg3DISu2QN6GK7yw== X-Authority-Analysis: v=2.4 cv=RKe+3oi+ c=1 sm=1 tr=0 ts=694155f9 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=wnJ2AIBC+6MZbTdryK78rQ==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=cm27Pg_UAAAA:8 a=awzhGNnQlOWheNBC8EkA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: coeKx68ZdsKRAWA5l-Qy2VpJh9GIVDis X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-16_02,2025-12-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 phishscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512160109 To allow the pwrctrl core to control the power on/off sequences of the pwrctrl drivers, add the 'struct pci_pwrctrl::power_{on/off}' callbacks and populate them in the respective pwrctrl drivers. The pwrctrl drivers still power on the resources on their own now. So there is no functional change. Co-developed-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Tested-by: Chen-Yu Tsai Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pwrctrl/pci-pwrctrl-pwrseq.c | 27 +++++++++++++++--- drivers/pci/pwrctrl/slot.c | 48 ++++++++++++++++++++++------= ---- include/linux/pci-pwrctrl.h | 4 +++ 3 files changed, 61 insertions(+), 18 deletions(-) diff --git a/drivers/pci/pwrctrl/pci-pwrctrl-pwrseq.c b/drivers/pci/pwrctrl= /pci-pwrctrl-pwrseq.c index 4e664e7b8dd2..0fb9038a1d18 100644 --- a/drivers/pci/pwrctrl/pci-pwrctrl-pwrseq.c +++ b/drivers/pci/pwrctrl/pci-pwrctrl-pwrseq.c @@ -52,11 +52,27 @@ static const struct pci_pwrctrl_pwrseq_pdata pci_pwrctr= l_pwrseq_qcom_wcn_pdata =3D .validate_device =3D pci_pwrctrl_pwrseq_qcm_wcn_validate_device, }; =20 +static int pci_pwrctrl_pwrseq_power_on(struct pci_pwrctrl *ctx) +{ + struct pci_pwrctrl_pwrseq_data *data =3D container_of(ctx, struct pci_pwr= ctrl_pwrseq_data, + ctx); + + return pwrseq_power_on(data->pwrseq); +} + +static void pci_pwrctrl_pwrseq_power_off(struct pci_pwrctrl *ctx) +{ + struct pci_pwrctrl_pwrseq_data *data =3D container_of(ctx, struct pci_pwr= ctrl_pwrseq_data, + ctx); + + pwrseq_power_off(data->pwrseq); +} + static void devm_pci_pwrctrl_pwrseq_power_off(void *data) { - struct pwrseq_desc *pwrseq =3D data; + struct pci_pwrctrl_pwrseq_data *pwrseq_data =3D data; =20 - pwrseq_power_off(pwrseq); + pci_pwrctrl_pwrseq_power_off(&pwrseq_data->ctx); } =20 static int pci_pwrctrl_pwrseq_probe(struct platform_device *pdev) @@ -85,16 +101,19 @@ static int pci_pwrctrl_pwrseq_probe(struct platform_de= vice *pdev) return dev_err_probe(dev, PTR_ERR(data->pwrseq), "Failed to get the power sequencer\n"); =20 - ret =3D pwrseq_power_on(data->pwrseq); + ret =3D pci_pwrctrl_pwrseq_power_on(&data->ctx); if (ret) return dev_err_probe(dev, ret, "Failed to power-on the device\n"); =20 ret =3D devm_add_action_or_reset(dev, devm_pci_pwrctrl_pwrseq_power_off, - data->pwrseq); + data); if (ret) return ret; =20 + data->ctx.power_on =3D pci_pwrctrl_pwrseq_power_on; + data->ctx.power_off =3D pci_pwrctrl_pwrseq_power_off; + pci_pwrctrl_init(&data->ctx, dev); =20 ret =3D devm_pci_pwrctrl_device_set_ready(dev, &data->ctx); diff --git a/drivers/pci/pwrctrl/slot.c b/drivers/pci/pwrctrl/slot.c index 3320494b62d8..14701f65f1f2 100644 --- a/drivers/pci/pwrctrl/slot.c +++ b/drivers/pci/pwrctrl/slot.c @@ -17,13 +17,36 @@ struct pci_pwrctrl_slot_data { struct pci_pwrctrl ctx; struct regulator_bulk_data *supplies; int num_supplies; + struct clk *clk; }; =20 -static void devm_pci_pwrctrl_slot_power_off(void *data) +static int pci_pwrctrl_slot_power_on(struct pci_pwrctrl *ctx) { - struct pci_pwrctrl_slot_data *slot =3D data; + struct pci_pwrctrl_slot_data *slot =3D container_of(ctx, struct pci_pwrct= rl_slot_data, ctx); + int ret; + + ret =3D regulator_bulk_enable(slot->num_supplies, slot->supplies); + if (ret < 0) { + dev_err(slot->ctx.dev, "Failed to enable slot regulators\n"); + return ret; + } + + return clk_prepare_enable(slot->clk); +} + +static void pci_pwrctrl_slot_power_off(struct pci_pwrctrl *ctx) +{ + struct pci_pwrctrl_slot_data *slot =3D container_of(ctx, struct pci_pwrct= rl_slot_data, ctx); =20 regulator_bulk_disable(slot->num_supplies, slot->supplies); + clk_disable_unprepare(slot->clk); +} + +static void devm_pci_pwrctrl_slot_release(void *data) +{ + struct pci_pwrctrl_slot_data *slot =3D data; + + pci_pwrctrl_slot_power_off(&slot->ctx); regulator_bulk_free(slot->num_supplies, slot->supplies); } =20 @@ -31,7 +54,6 @@ static int pci_pwrctrl_slot_probe(struct platform_device = *pdev) { struct pci_pwrctrl_slot_data *slot; struct device *dev =3D &pdev->dev; - struct clk *clk; int ret; =20 slot =3D devm_kzalloc(dev, sizeof(*slot), GFP_KERNEL); @@ -46,23 +68,21 @@ static int pci_pwrctrl_slot_probe(struct platform_devic= e *pdev) } =20 slot->num_supplies =3D ret; - ret =3D regulator_bulk_enable(slot->num_supplies, slot->supplies); - if (ret < 0) { - dev_err_probe(dev, ret, "Failed to enable slot regulators\n"); - regulator_bulk_free(slot->num_supplies, slot->supplies); - return ret; - } =20 - ret =3D devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off, + ret =3D devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_release, slot); if (ret) return ret; =20 - clk =3D devm_clk_get_optional_enabled(dev, NULL); - if (IS_ERR(clk)) { - return dev_err_probe(dev, PTR_ERR(clk), + slot->clk =3D devm_clk_get_optional(dev, NULL); + if (IS_ERR(slot->clk)) + return dev_err_probe(dev, PTR_ERR(slot->clk), "Failed to enable slot clock\n"); - } + + pci_pwrctrl_slot_power_on(&slot->ctx); + + slot->ctx.power_on =3D pci_pwrctrl_slot_power_on; + slot->ctx.power_off =3D pci_pwrctrl_slot_power_off; =20 pci_pwrctrl_init(&slot->ctx, dev); =20 diff --git a/include/linux/pci-pwrctrl.h b/include/linux/pci-pwrctrl.h index 4aefc7901cd1..bd0ee9998125 100644 --- a/include/linux/pci-pwrctrl.h +++ b/include/linux/pci-pwrctrl.h @@ -31,6 +31,8 @@ struct device_link; /** * struct pci_pwrctrl - PCI device power control context. * @dev: Address of the power controlling device. + * @power_on: Callback to power on the power controlling device. + * @power_off: Callback to power off the power controlling device. * * An object of this type must be allocated by the PCI power control devic= e and * passed to the pwrctrl subsystem to trigger a bus rescan and setup a dev= ice @@ -38,6 +40,8 @@ struct device_link; */ struct pci_pwrctrl { struct device *dev; + int (*power_on)(struct pci_pwrctrl *pwrctrl); + void (*power_off)(struct pci_pwrctrl *pwrctrl); =20 /* private: internal use only */ struct notifier_block nb; --=20 2.48.1 From nobody Thu Dec 18 01:37:29 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3784637D53D for ; Tue, 16 Dec 2025 12:52:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765889538; cv=none; b=HZomYwy5GgaOCrMVMg5I47rVGtKGgLJG1q0dBnQA/xj/RSXdwGMf1RF6Bt1D+IXw32+0WlbEhhsyNxn5dRz7dfliuGDzukXKjYq+rZqNCKHCDyvjgHx73NMJ/iaDq8CZ5h6h2XzZE4RCDy7oKLNeZTliLflB8sGEFkSMWlh+Tx0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765889538; c=relaxed/simple; bh=Euy9ek4QLZuPFAnOhsN9KCwtXXEQaqYZLJTxTZGnA4c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=S1WekkwXWyY/ckWJv7aGJPTFD5+iL8AkbgEoMD8tVvHkEc/hfHl+s6ijFEGLQevWtMTaIK4lVx+OTWyDkzkoUYQYrzzRqV/YwvoszRJXHwrpmD8oIptxOVPjrhE9SdqOzwzQstrpkmKQoWjHFKKtWePx4Zw13twBhiOcn0pM9Cc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Ob/rS13G; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=YnKHilH0; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Ob/rS13G"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="YnKHilH0" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BGAXWLb3598153 for ; Tue, 16 Dec 2025 12:52:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= zuGyltVA6H6nPxZKnvtWx6VprlmZukvoZn9Yp/vgZHc=; b=Ob/rS13GoqBVbFYD wdp16VmrANKoEioP7jAoGTbpTssK3gfNXbMQHbwIDAariPSyvMKR8A1tkcaijm+v 9SvjeoNs4areadaC7oek210kWh9F4d8ZiFJoYi2VSEk61P2DJSyWQu7u910Q1cNN Py8GEt5oafpqYVwZqQ8sSAAtXPKmaYcYVgfdmzLja4fKbo2aUVOEYF6DvmUteqRz AuuAUmK0AXAyQgSM/pU3Nkf1Ny2NICe4o6McOe7S7qSKxTSPdngPn/SzProEOMNE bRaY+edvbKDspq9Rokb1KYS/zAoHhK03D3BhlO0mDHI6ox4TpM5iudQTiIwXdDic rx2VaA== Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b35se0f7e-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 16 Dec 2025 12:52:14 +0000 (GMT) Received: by mail-pf1-f199.google.com with SMTP id d2e1a72fcca58-7aa9f595688so7217680b3a.2 for ; Tue, 16 Dec 2025 04:52:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1765889533; x=1766494333; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=zuGyltVA6H6nPxZKnvtWx6VprlmZukvoZn9Yp/vgZHc=; b=YnKHilH0gkmKjPHztZcibOTBe7bxBgT+KMaep4gh9uzEpOB3eqHXlFUKuIV1JOt/Bz eWSdam2mY0YTb6d+NSOvIOWRaI9tqojXIKl7Ir/tQWKlrbXYVjAOSptvL/OaFr2mZh8C Gg0x2DB3mc78oWWQfZYZaoESIv7vH5U4+B15c2fC1NSeddzeCqOz8uhj5FIWsAvEJ2ys zwzvmOJF6nPJx6jLANz45/4yOV69xfVNkhNhpb80gxg+M8FwW2c+2Tz4GjFiLyjUjdqL oXI+ktF9PvgN3zjxk7UBdyOS9QiQCO/wgDw8Mv7TQWe0PgEEDRdAowZMdexHdccHV1cD d20g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765889533; x=1766494333; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=zuGyltVA6H6nPxZKnvtWx6VprlmZukvoZn9Yp/vgZHc=; b=K/zS0lo2y+seE24Bihjn9Ssec0o4WxPJzjnPfmbW0h7wh+YyItfCkGHPBZ+1qsw4cP DRUsKcEhy4iDTYJUkjiVISUsYQSkiVaFprXsPoJ4zm8bPzZ9O+R3CN6D7SgHvhX1+AnC p3z6YMuo0duu7yShQqb5Fumcs8d34UvMNoeMtX79C6o/aEYFLYlf2GgavE+KdoVcWT29 WbrpQU4nSM27Zo/e/B8VNYnuetjIujRwfeka5j/PmGs19k/DOABVb/H++GKecMwp3F5N czp4dOlRtZRMFkjkJnnB8jUhd4tHeMa88tzGTGFxinfV8UyOuwWDxOEco5XntQODajEy h9Zg== X-Forwarded-Encrypted: i=1; AJvYcCWMwzpfgHosw4lgqMYmbll2XABXqozqPgiAYFE3+911TViTQ/nQZERFtgGtHmOhgG4L5skqRox3KK5zgyI=@vger.kernel.org X-Gm-Message-State: AOJu0Yzs+ry4m5lSTIBNbrYcOpDw4Lu1WaNx7f4oAKlILVQ/ZYJK/1D6 AV+mU2scVloJ8dPUvCNLZNimulzjR/YSV/XchGgVy8q94z736BXGP5Ok0wjA81xkknnUOx+x23m 5xhpbQbxoH+0WFev6/auDD0BY52kQd0bJ4xZoi4ckuwMfQa/HTEVXYgoEanNfH1/orIdJY8sHML k= X-Gm-Gg: AY/fxX5lCe/Ep+W2K5Ei8Amjlfo0vhwMCLEgA3irQ06rz4otMZMOjuTjYHFhK+MI1eU QDzDStiGua/I0MhQUZHWytVEn4uC2X0WjVvd80CFF0asMO3ScURoqWI3kEZ+njHQ2gDH/yPMXYK 2WkvdQzWnfWdxgxDbY7SwPbttVP/wJ4qB1ijTqrYRbtHBsiU2FcOh72mZDe27ku8y23MXgA11Yp q5YRmgwhII2szFskLesq6YRm1PAN+G7g0BWMENEIMAlKnh4UVkGI1U+P8GdrOLKsrDn+6U7E/T7 BlzSP7yb4d+JvLfOf58DiuYzVC3p5YBFKYdq56dX5ZLWxZwMz1vikPFrK0xZRFiRHlBL/reRjBY ivK3tDHceJSLXc+LDf+DQP+px9h2CkBoCqorg48Z/+w== X-Received: by 2002:a05:6a00:400c:b0:78c:994a:fc87 with SMTP id d2e1a72fcca58-7f66792ecf8mr12198573b3a.6.1765889533277; Tue, 16 Dec 2025 04:52:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IHbzWWEuXvy3Bb0GZybRlU1R9lBHtqRfDs1n7sfrT91bknh/oRbvNgSVQ+89tPZ8Sywl1O1lg== X-Received: by 2002:a05:6a00:400c:b0:78c:994a:fc87 with SMTP id d2e1a72fcca58-7f66792ecf8mr12198546b3a.6.1765889532741; Tue, 16 Dec 2025 04:52:12 -0800 (PST) Received: from [192.168.1.102] ([117.193.213.190]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7f5ab7d87e8sm13634362b3a.25.2025.12.16.04.52.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Dec 2025 04:52:12 -0800 (PST) From: Manivannan Sadhasivam Date: Tue, 16 Dec 2025 18:21:45 +0530 Subject: [PATCH v2 3/5] PCI/pwrctrl: Add APIs for explicitly creating and destroying pwrctrl devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251216-pci-pwrctrl-rework-v2-3-745a563b9be6@oss.qualcomm.com> References: <20251216-pci-pwrctrl-rework-v2-0-745a563b9be6@oss.qualcomm.com> In-Reply-To: <20251216-pci-pwrctrl-rework-v2-0-745a563b9be6@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Bartosz Golaszewski , Bartosz Golaszewski Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai , Brian Norris , Krishna Chaitanya Chundru , Niklas Cassel , Alex Elder , Manivannan Sadhasivam , Chen-Yu Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7336; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=RVCEpUIHxSA8U7uEnCgFGs1zmOAMqmbSgGgoPH/vJ+s=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpQVXowa0/qVQmVD9ttth18ch8HEhPBicNLp/6r q/fznDA/S+JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaUFV6AAKCRBVnxHm/pHO 9W8AB/0dVPIqtUNItBuVnF70kFtvmucI+rTyuRPKA/kU9qN5BmXs9CHfiGMJwFpiSNYXOuRMOW9 N/g+Lhsh44uC/DlEhqrzCjG1/25isbTdJg2Vsc+5uetfq9EplOJIkH6QmIdvz1Y304a92mqpwic +CbYb3q8F9JTwSX0XF5gzTgNK2HgtE+dkfDXO189vCbSosz8Rn1wx4XCDi9LtL9sYZ0cV5jI9vv SJIqyAZ/daKt7sbwzKOSt3tFkuBhoUnG0OSpzhZaneXI7bfkq4vFTpGHi18Sd/VvBKAE5wRmMap CHtAhWlOO30Lk4xYkjsbFoizqJYIqzHnNeqI1Cl66yFGza7S X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Proofpoint-ORIG-GUID: lwr4fkBr8zp8ZtVbMSCnMa7cyvO4QL1R X-Authority-Analysis: v=2.4 cv=ar2/yCZV c=1 sm=1 tr=0 ts=694155fe cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=wnJ2AIBC+6MZbTdryK78rQ==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=cm27Pg_UAAAA:8 a=KKAkSRfTAAAA:8 a=I2O-u4IYt9Uj2DONGs4A:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: lwr4fkBr8zp8ZtVbMSCnMa7cyvO4QL1R X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE2MDEwNiBTYWx0ZWRfXxVbqfyoZsAZx 0SVPtBJNIGCzDFFq04FIaNuL/wYkcicxwlABeiSOHL/12MTAsK7/ke1D2tftuesKEpkpGmtLNOe aVEHwboCLHJlrGQpuMxSp41gZP1baEjy058kxiDSODSPOzsPqp2GilkgSN+vP0M3JXjzLHIXRvC WxkAxd8nzhshvwhiKB0wz5MKQQe2knVrJudO7U2DBwPmEk4vN3BN1p0Q/dV3Y6WombW23rcA2PG E4cX+n1n57VcYKCaBF/zYwx0nHALNvMkBEC9TgeisKNCSRlW8JyfAbw9qW2Pj40mJxZw+JIfhIb 0fBEq2vC3TPPJTb2c4L4Uf9vnlbVBCDIzd7xBv/Ttl+yCqvrKu9hehNvXLPjHlCTUL0vpIFCpk4 O4r47BCWK5b21OtfwwEtnpixcJFo9w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-16_02,2025-12-16_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 suspectscore=0 adultscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512160106 From: Krishna Chaitanya Chundru Previously, the PCI core created pwrctrl devices during pci_scan_device() on its own and then skipped enumeration of those devices, hoping the pwrctrl driver would power them on and trigger a bus rescan. This approach works for endpoint devices directly connected to Root Ports, but it fails for PCIe switches acting as bus extenders. When the switch requires pwrctrl support, and the pwrctrl driver is not available during the pwrctrl device creation, it's enumeration will be skipped during the initial PCI bus scan. This premature scan leads the PCI core to allocate resources (bridge windows, bus numbers) for the upstream bridge based on available downstream buses at scan time. For non-hotplug capable bridges, PCI core typically allocates resources based on the number of buses available during the initial bus scan, which happens to be just one if the switch is not powered on and enumerated at that time. When the switch gets enumerated later on, it will fail due to the lack of upstream resources. As a result, a PCIe switch powered on by the pwrctrl driver cannot be reliably enumerated currently. Either the switch has to be enabled in the bootloader or the switch pwrctrl driver has to be loaded during the pwrctrl device creation time to workaround these issues. This commit introduces new APIs to explicitly create and destroy pwrctrl devices from controller drivers by recursively scanning the PCI child nodes of the controller. These APIs allow creating pwrctrl devices based on the original criteria and are intended to be called during controller probe and removal. These APIs, together with the upcoming APIs for power on/off will allow the controller drivers to power on all the devices before starting the initial bus scan, thereby solving the resource allocation issue. Signed-off-by: Krishna Chaitanya Chundru [mani: splitted the patch, cleaned up the code, and rewrote description] Tested-by: Chen-Yu Tsai Signed-off-by: Manivannan Sadhasivam --- drivers/pci/of.c | 1 + drivers/pci/pwrctrl/core.c | 112 ++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/pci-pwrctrl.h | 8 +++- 3 files changed, 120 insertions(+), 1 deletion(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 3579265f1198..9bb5f258759b 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -867,6 +867,7 @@ bool of_pci_supply_present(struct device_node *np) =20 return false; } +EXPORT_SYMBOL_GPL(of_pci_supply_present); =20 #endif /* CONFIG_PCI */ =20 diff --git a/drivers/pci/pwrctrl/core.c b/drivers/pci/pwrctrl/core.c index 6bdbfed584d6..6eca54e0d540 100644 --- a/drivers/pci/pwrctrl/core.c +++ b/drivers/pci/pwrctrl/core.c @@ -3,14 +3,21 @@ * Copyright (C) 2024 Linaro Ltd. */ =20 +#define dev_fmt(fmt) "Pwrctrl: " fmt + #include #include #include +#include +#include #include #include +#include #include #include =20 +#include "../pci.h" + static int pci_pwrctrl_notify(struct notifier_block *nb, unsigned long act= ion, void *data) { @@ -145,6 +152,111 @@ int devm_pci_pwrctrl_device_set_ready(struct device *= dev, } EXPORT_SYMBOL_GPL(devm_pci_pwrctrl_device_set_ready); =20 +static int pci_pwrctrl_create_device(struct device_node *np, struct device= *parent) +{ + struct platform_device *pdev; + int ret; + + for_each_available_child_of_node_scoped(np, child) { + ret =3D pci_pwrctrl_create_device(child, parent); + if (ret) + return ret; + } + + /* Bail out if the platform device is already available for the node */ + pdev =3D of_find_device_by_node(np); + if (pdev) { + put_device(&pdev->dev); + return 0; + } + + /* + * Sanity check to make sure that the node has the compatible property + * to allow driver binding. + */ + if (!of_property_present(np, "compatible")) + return 0; + + /* + * Check whether the pwrctrl device really needs to be created or not. + * This is decided based on at least one of the power supplies being + * defined in the devicetree node of the device. + */ + if (!of_pci_supply_present(np)) { + dev_dbg(parent, "Skipping OF node: %s\n", np->name); + return 0; + } + + /* Now create the pwrctrl device */ + pdev =3D of_platform_device_create(np, NULL, parent); + if (!pdev) { + dev_err(parent, "Failed to create pwrctrl device for node: %s\n", np->na= me); + return -EINVAL; + } + + return 0; +} + +/** + * pci_pwrctrl_create_devices - Create pwrctrl devices + * + * @parent: Parent PCI device for which the pwrctrl devices need to be cre= ated. + * + * This function recursively creates pwrctrl devices for the child nodes + * of the specified PCI parent device in a depth first manner. + * + * Returns: 0 on success, negative error number on error. + */ +int pci_pwrctrl_create_devices(struct device *parent) +{ + int ret; + + for_each_available_child_of_node_scoped(parent->of_node, child) { + ret =3D pci_pwrctrl_create_device(child, parent); + if (ret) { + pci_pwrctrl_destroy_devices(parent); + return ret; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(pci_pwrctrl_create_devices); + +static void pci_pwrctrl_destroy_device(struct device_node *np) +{ + struct platform_device *pdev; + + for_each_available_child_of_node_scoped(np, child) + pci_pwrctrl_destroy_device(child); + + pdev =3D of_find_device_by_node(np); + if (!pdev) + return; + + of_device_unregister(pdev); + put_device(&pdev->dev); + + of_node_clear_flag(np, OF_POPULATED); +} + +/** + * pci_pwrctrl_destroy_devices - Destroy pwrctrl devices + * + * @parent: Parent PCI device for which the pwrctrl devices need to be des= troyed. + * + * This function recursively destroys pwrctrl devices for the child nodes + * of the specified PCI parent device in a depth first manner. + */ +void pci_pwrctrl_destroy_devices(struct device *parent) +{ + struct device_node *np =3D parent->of_node; + + for_each_available_child_of_node_scoped(np, child) + pci_pwrctrl_destroy_device(child); +} +EXPORT_SYMBOL_GPL(pci_pwrctrl_destroy_devices); + MODULE_AUTHOR("Bartosz Golaszewski "); MODULE_DESCRIPTION("PCI Device Power Control core driver"); MODULE_LICENSE("GPL"); diff --git a/include/linux/pci-pwrctrl.h b/include/linux/pci-pwrctrl.h index bd0ee9998125..5590ffec0bea 100644 --- a/include/linux/pci-pwrctrl.h +++ b/include/linux/pci-pwrctrl.h @@ -54,5 +54,11 @@ int pci_pwrctrl_device_set_ready(struct pci_pwrctrl *pwr= ctrl); void pci_pwrctrl_device_unset_ready(struct pci_pwrctrl *pwrctrl); int devm_pci_pwrctrl_device_set_ready(struct device *dev, struct pci_pwrctrl *pwrctrl); - +#if IS_ENABLED(CONFIG_PCI_PWRCTRL) +int pci_pwrctrl_create_devices(struct device *parent); +void pci_pwrctrl_destroy_devices(struct device *parent); +#else +static inline int pci_pwrctrl_create_devices(struct device *parent) { retu= rn 0; } +static void pci_pwrctrl_destroy_devices(struct device *parent) { } +#endif #endif /* __PCI_PWRCTRL_H__ */ --=20 2.48.1 From nobody Thu Dec 18 01:37:29 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66051382D2A for ; Tue, 16 Dec 2025 12:52:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765889542; cv=none; b=W1dOhK7E98O+fnsjxfmrj3QM4pheXklLTtAOOdGn8V22j7w0tcFw9+WLtCH8+sM0fQb/wOeNbOwSYaTY8QExjgL7KdkCdVCkjFzc+AaLv/9+l/fHJt7jPUi+zQPFE/R42KqteCuBTuHEGMILeMoJPc1Xr55ZFBAoUp6AFl1B5fc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765889542; c=relaxed/simple; bh=tJ3oGSmbF0uqKIwPRkbZG//2gq/sUu33RqRKbMsLjEo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=o+ztXqHdB3x3hX7YLwDuWmw1Q0c9+avuoK5WzqyVbNZ3MbY3XxFFv0+M7azRv4GabWN6P0t1F7jRc4fRFJbtRYhuNNOEIXjqm9k4zqLG0Gw94nwKe3GK6cLD6sjdQov5Jvus7iWDDuRyRYnoP4qZrgyp1WZb5/vRDsL8Pce/zPk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=YUvr9Lhb; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=UMiEuLCX; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="YUvr9Lhb"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="UMiEuLCX" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BGBOLTg3391337 for ; Tue, 16 Dec 2025 12:52:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= M9RCd35HO7B795ZOFtTVgJAEk6vZrWP6EDm6tO69gdI=; b=YUvr9Lhb8HL2/Qbn BaL28BkxTMgPHz7LIjCIXeuYr0q0XT9tMTETSUlF3qrlFwjh3BpkPs/XsxJee89G YUUMBtsqQJgFYvn/YATc0O+Yvmf5N/f3DKG/eb9h61ak27BC84Sy5oUNTCg9xqo0 n+tPMUDFUitHVk8OZi40a4hvtXXIVVgzblUU1x97XYA8a2uafBsgUnKSMgjDizkb IesbeGDBLVX2/T4ZSQJP6OV1YMTvJv+02pNlltqSCQywFsRCGE1ABBqvwzj9u8Gx J83dBimO4E4FzOuiQvZ5bfHS8OgZgWENX7LAMMr19kRgKTdP8ZBwon/GMNbPQrhu tfj7GQ== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b36h389rx-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 16 Dec 2025 12:52:19 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-7b8a12f0cb4so5636400b3a.3 for ; Tue, 16 Dec 2025 04:52:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1765889539; x=1766494339; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=M9RCd35HO7B795ZOFtTVgJAEk6vZrWP6EDm6tO69gdI=; b=UMiEuLCXeXaH/1bG2yCnO/rpgvkDyfQPcFsIU7n7FxDNL1LxUcue51Sglz2c1Ngy+Q GFre1IBOReZTCLjCXTyI77aIrLfyR8mByPDg1dP6bDjtUg4pK3VpDogBffZEVWUfMsJ+ HFQD4nFeKBXrFr/zvVvRdmA0CH+C6qsm/+/ISuW7+gFFztEFErkiL1bokKpNrptktPxK jvn+0b6HYzCxd3kDINyOMAq6VKZU5yl2gI4gMUIFv8z56INrIHAzeQ+huZEFAhEOj4y2 PCcKZwQbpt04onMDsrxIx6EHvtHZ2+H+5EbIjS1BJ2WyN87/o6h2ZXbl4rUzdYDtVLT3 Q6Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765889539; x=1766494339; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=M9RCd35HO7B795ZOFtTVgJAEk6vZrWP6EDm6tO69gdI=; b=O1hmCtIgd4+cU7u4B+Yc0xQYOvj6qgru2WlLBeTTT+dFCUvYOk2F8JJ2GTvDywbfFI 0uCU9ZLAo5sUisvZjfBGuoOec7GTeVPLvZQ0KXJiqRL05m/nOnvuPTpCjEPmf1uOsnRc t2Cs5Fy1LtE/v2ZFayJpo6g3dZz137m3ObqDJaBWIusXzpp9gc3c8/E6w78C9oqMD0bk kWP1gCO8F5GkvDRk98GYC4JYdqfDhMRfinYTz98a31/Lp3z9fC2g4OAFQ+trqzEcZ8LO t5hG7N1WtB+eOZzFxbojUFWxZvofra77lkgXB+Hc2RAUhH/woEGUu3z6Isq/1sEBh458 0QuA== X-Forwarded-Encrypted: i=1; AJvYcCWJcItbkd+iwJ3Av9X5tB85vTBFaKn6TUJsJfPxy6A/0MBgFVH/iIw4fpw2x+TVhHFZAkhYv5CWGT0MkmM=@vger.kernel.org X-Gm-Message-State: AOJu0Yyt626TOmfVg5SuEXkkNOantDh+ShskvnF/aUcBxGOK2UhEckS7 wjadn8oiiagT1sxO1WSYl+xfmWfFW/neMiyrWn4lIdMHEP9eV75E5EJJfdlMf+nRnRR5oZcpsHX /NKC1wyj7ZAWBYNGP9SuElTZ8LKWScKvN6YmXLqGEqlwGltjBdIIaiHVpyxIP4Y1alGMTNcAr+A 4= X-Gm-Gg: AY/fxX4OrDZgtrjKQoLx5ZrpbeZWJugTia1k9BbdFJvF/AIl0Hs/e3W2E3gcJ3Tgi5G gczp8cYx0JbHCdworTyoNprEyUfZBgh9BUFf+mgQJHxNfEM6onmNDeZmA9isW2TIUvQYJ2+iWlg laeJiF3pbMTGeu4vEAspZNkASzlLO5NO2yoMt3OMwl+SeRE4+kggNMKA0FftDVqexesx2mtx6v0 AdddAZFejPFm9SygG+B9wctA2NtD8dG6+ftlNPf43v5w7U8Ye83PcL/pcxkeF2OXHzsRkMZqJjw Dq5HU9Uq+PBnlniiOoK03tfjL4TE+PL9HKYiXbBIwnU7R1fVYBvmI9MLjh6JMLbMyhCEOrpXSUs MsRzMsp/9TO0AWfzawnx/DDXSRJ4x00tTWzj08fQV2A== X-Received: by 2002:a05:6a00:429b:b0:7e8:43f5:bd55 with SMTP id d2e1a72fcca58-7f669c8ba28mr11528953b3a.65.1765889538577; Tue, 16 Dec 2025 04:52:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IGW+M8UF2OnxF2QQLMe2t94UUedPRIEiBdPAnCYqd00GJ7WaY9ekheOQ3SyQO+OsYryx/7XvA== X-Received: by 2002:a05:6a00:429b:b0:7e8:43f5:bd55 with SMTP id d2e1a72fcca58-7f669c8ba28mr11528933b3a.65.1765889538081; Tue, 16 Dec 2025 04:52:18 -0800 (PST) Received: from [192.168.1.102] ([117.193.213.190]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7f5ab7d87e8sm13634362b3a.25.2025.12.16.04.52.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Dec 2025 04:52:17 -0800 (PST) From: Manivannan Sadhasivam Date: Tue, 16 Dec 2025 18:21:46 +0530 Subject: [PATCH v2 4/5] PCI/pwrctrl: Add APIs to power on/off the pwrctrl devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251216-pci-pwrctrl-rework-v2-4-745a563b9be6@oss.qualcomm.com> References: <20251216-pci-pwrctrl-rework-v2-0-745a563b9be6@oss.qualcomm.com> In-Reply-To: <20251216-pci-pwrctrl-rework-v2-0-745a563b9be6@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Bartosz Golaszewski , Bartosz Golaszewski Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai , Brian Norris , Krishna Chaitanya Chundru , Niklas Cassel , Alex Elder , Manivannan Sadhasivam , Chen-Yu Tsai , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6123; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=tJ3oGSmbF0uqKIwPRkbZG//2gq/sUu33RqRKbMsLjEo=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpQVXoJshYDHbsyksxVQhRBCuW4SoUJYUyBpS6P Gj/UPdchMOJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaUFV6AAKCRBVnxHm/pHO 9Un7CACIz8vUMEsmPwq2dAYw/IqptY36Bc+4vC1uj12ujaHijC5HIsoTEJ+/QbyjDV1CxGcLy7N WeEOc5uEuKh8tR3Uxs3Yu9JWC9wlICZWLyLrFcU2eHjgR8SugTnajWk56xCuDsQwpw7oYPjBIOo in+lSOWmVB9EC8j+YlCpNUe4vBDNco/ruQpPNZZLaLWgt2MxdT4Cmt+bBtUsRf99DLJjUfWJvqy Pt47beVYC9dxX4YUIstC6jzu/DvvL2i9Emq4PWo5WEoskr2m/vs50QVHOR2m/fjq7x1hDSr+DBC TUYtNLUFWAL7Vz089OCFUb05cTumGn3BEw/GNaeCfxne4+iP X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE2MDEwOSBTYWx0ZWRfXzHS0zAmTfO5l fBAZi80Ca+ddPQHfi2RYVv1DWEUNoS27Hi3jTZ2JyjvXqkkDsPUQW8TPwvMRd1yE5kEjDX80fVY f19LRv62avb3vfuwfb+y9Llx2c0hCChhLenGu6Gi/2nF+UVd009Hl+OWvG5H+E78z6kjxruELTW A6/eFWql6yxoExJYfSUKsqUtgn4VMw2POKFMpmMFMLIks95CQ1yC/R3RF9LR6aVGAIL45deLSfZ COGRR/x5kg7RQFxl+Y9vji9DDyc5AR9CzqK/fpQSno6qZMv3832vJIEl2EuB9CN1Lu/BzSyEkbp TiEPIB2/QAAJ6Xp6ZalD3g61dXdjQIbO+XuzuYaOaDLL6f9bKrmrA46YSXhKSKvcl7hHXRSBtx5 zoSoVJjZgyTXGTbxXW1jEUU7LkC/7w== X-Proofpoint-GUID: Oh6A0oNkB8hu91-d6W26R8_LEwgA4tFE X-Authority-Analysis: v=2.4 cv=QeRrf8bv c=1 sm=1 tr=0 ts=69415603 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=wnJ2AIBC+6MZbTdryK78rQ==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=cm27Pg_UAAAA:8 a=KKAkSRfTAAAA:8 a=RyQsIt2LcgCPV6mEHuQA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: Oh6A0oNkB8hu91-d6W26R8_LEwgA4tFE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-16_02,2025-12-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 adultscore=0 clxscore=1015 suspectscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512160109 To fix PCIe bridge resource allocation issues when powering PCIe switches with the pwrctrl driver, introduce APIs to explicitly power on and off all related devices simultaneously. Previously, the individual pwrctrl drivers powered on/off the PCIe devices autonomously, without any control from the controller drivers. But to enforce ordering w.r.t powering on the devices, these APIs will power on/off all the devices at the same time. The pci_pwrctrl_power_on_devices() API recursively scans the PCI child nodes, makes sure that pwrctrl drivers are bind to devices, and calls their power_on() callbacks. Similarly, pci_pwrctrl_power_off_devices() API powers off devices recursively via their power_off() callbacks. These APIs are expected to be called during the controller probe and suspend/resume time to power on/off the devices. But before calling these APIs, the pwrctrl devices should've been created beforehand using the pci_pwrctrl_{create/destroy}_devices() APIs. Co-developed-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Tested-by: Chen-Yu Tsai Reviewed-by: Bartosz Golaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pwrctrl/core.c | 121 ++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/pci-pwrctrl.h | 4 ++ 2 files changed, 125 insertions(+) diff --git a/drivers/pci/pwrctrl/core.c b/drivers/pci/pwrctrl/core.c index 6eca54e0d540..ebe1740b7c1c 100644 --- a/drivers/pci/pwrctrl/core.c +++ b/drivers/pci/pwrctrl/core.c @@ -65,6 +65,7 @@ void pci_pwrctrl_init(struct pci_pwrctrl *pwrctrl, struct= device *dev) { pwrctrl->dev =3D dev; INIT_WORK(&pwrctrl->work, rescan_work_func); + dev_set_drvdata(dev, pwrctrl); } EXPORT_SYMBOL_GPL(pci_pwrctrl_init); =20 @@ -152,6 +153,126 @@ int devm_pci_pwrctrl_device_set_ready(struct device *= dev, } EXPORT_SYMBOL_GPL(devm_pci_pwrctrl_device_set_ready); =20 +static int __pci_pwrctrl_power_on_device(struct device *dev) +{ + struct pci_pwrctrl *pwrctrl =3D dev_get_drvdata(dev); + + if (!pwrctrl) + return 0; + + return pwrctrl->power_on(pwrctrl); +} + +/* + * Power on the devices in a depth first manner. Before powering on the de= vice, + * make sure its driver is bound. + */ +static int pci_pwrctrl_power_on_device(struct device_node *np) +{ + struct platform_device *pdev; + int ret; + + for_each_available_child_of_node_scoped(np, child) { + ret =3D pci_pwrctrl_power_on_device(child); + if (ret) + return ret; + } + + pdev =3D of_find_device_by_node(np); + if (pdev) { + if (!device_is_bound(&pdev->dev)) { + dev_dbg(&pdev->dev, "driver is not bound\n"); + ret =3D -EPROBE_DEFER; + } else { + ret =3D __pci_pwrctrl_power_on_device(&pdev->dev); + } + put_device(&pdev->dev); + + if (ret) + return ret; + } + + return 0; +} + +/** + * pci_pwrctrl_power_on_devices - Power on the pwrctrl devices + * + * @parent: Parent PCI device for which the pwrctrl devices need to be pow= ered + * on. + * + * This function recursively traverses all pwrctrl devices for the child n= odes + * of the specified PCI parent device, and powers them on in a depth first + * manner. + * + * Returns: 0 on success, negative error number on error. + */ +int pci_pwrctrl_power_on_devices(struct device *parent) +{ + struct device_node *np =3D parent->of_node; + int ret; + + for_each_available_child_of_node_scoped(np, child) { + ret =3D pci_pwrctrl_power_on_device(child); + if (ret) { + pci_pwrctrl_power_off_devices(parent); + return ret; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(pci_pwrctrl_power_on_devices); + +static void __pci_pwrctrl_power_off_device(struct device *dev) +{ + struct pci_pwrctrl *pwrctrl =3D dev_get_drvdata(dev); + + if (!pwrctrl) + return; + + return pwrctrl->power_off(pwrctrl); +} + +static int pci_pwrctrl_power_off_device(struct device_node *np) +{ + struct platform_device *pdev; + + for_each_available_child_of_node_scoped(np, child) + pci_pwrctrl_power_off_device(child); + + pdev =3D of_find_device_by_node(np); + if (pdev) { + if (device_is_bound(&pdev->dev)) + __pci_pwrctrl_power_off_device(&pdev->dev); + + put_device(&pdev->dev); + } + + return 0; +} + +/** + * pci_pwrctrl_power_off_devices - Power off the pwrctrl devices + * + * @parent: Parent PCI device for which the pwrctrl devices need to be pow= ered + * off. + * + * This function recursively traverses all pwrctrl devices for the child n= odes + * of the specified PCI parent device, and powers them off in a depth first + * manner. + * + * Returns: 0 on success, negative error number on error. + */ +void pci_pwrctrl_power_off_devices(struct device *parent) +{ + struct device_node *np =3D parent->of_node; + + for_each_available_child_of_node_scoped(np, child) + pci_pwrctrl_power_off_device(child); +} +EXPORT_SYMBOL_GPL(pci_pwrctrl_power_off_devices); + static int pci_pwrctrl_create_device(struct device_node *np, struct device= *parent) { struct platform_device *pdev; diff --git a/include/linux/pci-pwrctrl.h b/include/linux/pci-pwrctrl.h index 5590ffec0bea..1b77769eebbe 100644 --- a/include/linux/pci-pwrctrl.h +++ b/include/linux/pci-pwrctrl.h @@ -57,8 +57,12 @@ int devm_pci_pwrctrl_device_set_ready(struct device *dev, #if IS_ENABLED(CONFIG_PCI_PWRCTRL) int pci_pwrctrl_create_devices(struct device *parent); void pci_pwrctrl_destroy_devices(struct device *parent); +int pci_pwrctrl_power_on_devices(struct device *parent); +void pci_pwrctrl_power_off_devices(struct device *parent); #else static inline int pci_pwrctrl_create_devices(struct device *parent) { retu= rn 0; } static void pci_pwrctrl_destroy_devices(struct device *parent) { } +static inline int pci_pwrctrl_power_on_devices(struct device *parent) { re= turn 0; } +static void pci_pwrctrl_power_off_devices(struct device *parent) { } #endif #endif /* __PCI_PWRCTRL_H__ */ --=20 2.48.1 From nobody Thu Dec 18 01:37:29 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 596B2382D56 for ; Tue, 16 Dec 2025 12:52:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765889547; cv=none; b=jIK+lZm+pv4WWQEbwqlCKdotx4H2ZdYRMXfsj8wqO3gGFmTYxcGZXlyDkpuMTkl5Mc3ho3Gnl8zm+TWiq1vM2Ei6T5C4E8sWN3knUvfzy6hpG5iTqw/qFzKs+oKmdlp5GNannqibzL9sb3brYzE5hMRHuE41zJwQ1lD0lT5u4kU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765889547; c=relaxed/simple; bh=4RZqS9C5omgsMD+6meE6/yDTZg9+e38zvxvu7kBnSY8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=c4Azc6htMj2gPj89ywzv2OES72nhyPBSi2eN1ODBNxPKSvuAhs6ybXfr87ihu7bj+98dYD4lA6NsOwxYUtMjLGcCuJ20sCk62NUSczYzMCR9iSFPbLxCuIH4ahcclVUMLnHg9xlrqGBus385BktUdMUHuHA8xWhdG+e0FJp9SBk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=IsLSz0nx; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ZXI0Se36; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="IsLSz0nx"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ZXI0Se36" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BG9bb452516185 for ; Tue, 16 Dec 2025 12:52:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 2gpMHf9kn3YsZ6lMZhd5fnKWGfnj5wMtwuzg4GBEGD8=; b=IsLSz0nxHPWWcOHn Gt8EWBJgOJxBSZA91uBsq6mneCxj1NOOIzqFCYsnWEXc/QPrWcs+hi9jYL/uVvmd 79GMgviTYdiuelNpUzfE3o0vZYQiv0bf7jtEfC2xvGOoff//QqM9cp+0JcJKEe2x ZrY0oZO/Uu2lABy4dVdK3HeB3UA/GRlQLwglrhBXn3lHTAaj6n2niuoQX+FIPAgg 9JyKEzu6xJG73/dHIWsHpfvVGJvbldBGwUusVXU6HKxdwwaRyRiwipU5N1bQhC18 dgOLHIoCaUc0J005tHtYMxKZpCnJPJLJXf9PoaX2Ii9WA4MRhGWayuG2yTabA1MT RIEFbQ== Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b34y80qah-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 16 Dec 2025 12:52:24 +0000 (GMT) Received: by mail-pf1-f200.google.com with SMTP id d2e1a72fcca58-7d5564057d0so12778822b3a.0 for ; Tue, 16 Dec 2025 04:52:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1765889544; x=1766494344; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2gpMHf9kn3YsZ6lMZhd5fnKWGfnj5wMtwuzg4GBEGD8=; b=ZXI0Se36h6YycNZt5s2NjyDDNCAcvZlgcndEHmkEBxkn1oVMCVb9/Jqe72F5wn0KMz xfCR9i+CEXgJonSyZ6Rz2dr7wDRfk0PWko0/f99f1IpXRiXtNp8rbHZ0h8kLpuuuPzrr L3DM01UetPQWr4XvMU3dN2e3HyzM2cTeNyzD19Z6uimhRjnufykkQ60NP3cwZzFVqPvS 0KqgisTuv140k0MAu+8XtniniBpYR7iJ5UMU4ZeOwoS1waMcuG80/oFrx/yka1DcdHX2 SqIsGooFrbHcNnqiXu5XsaOLHn2Z6AkPh6d6XtInGd0iUrFbhMHVIxYBgBS8+uh9IULn V/Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765889544; x=1766494344; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=2gpMHf9kn3YsZ6lMZhd5fnKWGfnj5wMtwuzg4GBEGD8=; b=fss6eK5sUpI5Z0DxooJOR71PE27W/MZRkg1REVOnsnMLiFCmSfYyUiShFWFCjSgEq1 5UMtOXdb0DMhnBiTWPZ7aNsO8+6pi/qYeoCp90Hif3uDI/KZcze5bSrTNFY1g7bH0QWI ZgiDe9Rdr/HkTp8N8XRTtegnZfOEjxf74zOhmfwP7QFN13Feh7EquWk7Py1fpba6HoF9 eRYr5LGsCLVNK4xLKaDnTB/HqqUfU4+KGdaczVDqs6QnyqKv6kmLR27f7ngBykTYQSo5 bslH5muL9dd04UX1b9uDZDfE6CFsaVVCD78m/17l5YIpWFV10gXHbf8swFyb/zQHLjGV xsRw== X-Forwarded-Encrypted: i=1; AJvYcCWyb7VqTrWG2VD8XVZvg6wY2BJQBpRdBAWbxrAAXMzc4ZZeQ+zrDcgyGNq0FvaDAfwj9bDGK0fyF++LJq0=@vger.kernel.org X-Gm-Message-State: AOJu0YyaelmeAbQwy1UdZvwwLF6dZCv0/o6Iu2dKc99Q6wgA1Ht58wAT TdcmK6JH4JTypali3OYyrScsoZzoBUBHTWwlDwYIG5gCaszQf3EZcadRY9KnJAGlz9ki1g+dvgB XI1JAFcgtCcjH+iqcFXCvEXTu4kwGY4A7R6u/020zzrrDi+Xm/Ct9xNFpO41XPDP6DcCexs3XyW A= X-Gm-Gg: AY/fxX7Xfql0PZfb2zp7ZNn+s0q+k8g0lnMdmXZrskhjLc7GBTU74Hr98D6rq/GVZnT s9KOGQU1pEkzl2XaFVKqMVEQavd71IlTLVFnCzECPjc5Ff2s1Ufo0aMW3+uvS5iy5CNWsNY/KtZ ZRJFuAV+1JNoe8wdXIsuiGi+w2rBTtjXB1P3Jc+4jL4ZqaZzV2hq3YhxUlg/BvFwjSemTebbt0y kQG325IXWlH3FgjCemhWov/WUYdQEhs4nmRFy9SrDJPXrU04Q5FuILm5A2Gt0lMOG8tQR72x4p5 lIhZ4t+miAWE62Vk/MSBtmtt6dCRrJDaXcTt1N3dNuJ/XjkSpyAGm5CBxE192YL+/0U/cC1STK2 Xpzzv0oCMjtLVm+R24KmNvOIJEtTv3LMxaQRoUi5P6Q== X-Received: by 2002:a05:6a00:138e:b0:7f7:612e:461e with SMTP id d2e1a72fcca58-7f7612e46e6mr12318142b3a.57.1765889543516; Tue, 16 Dec 2025 04:52:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IFJU7gwo5fGnKCS3PuUWKoDT3aiGbjLTaLkWJF6hxZ6AQlFNOvCz8g7NH9FrkvzDdVucqhcWQ== X-Received: by 2002:a05:6a00:138e:b0:7f7:612e:461e with SMTP id d2e1a72fcca58-7f7612e46e6mr12318108b3a.57.1765889543027; Tue, 16 Dec 2025 04:52:23 -0800 (PST) Received: from [192.168.1.102] ([117.193.213.190]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7f5ab7d87e8sm13634362b3a.25.2025.12.16.04.52.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Dec 2025 04:52:22 -0800 (PST) From: Manivannan Sadhasivam Date: Tue, 16 Dec 2025 18:21:47 +0530 Subject: [PATCH v2 5/5] PCI/pwrctrl: Switch to the new pwrctrl APIs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251216-pci-pwrctrl-rework-v2-5-745a563b9be6@oss.qualcomm.com> References: <20251216-pci-pwrctrl-rework-v2-0-745a563b9be6@oss.qualcomm.com> In-Reply-To: <20251216-pci-pwrctrl-rework-v2-0-745a563b9be6@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Bartosz Golaszewski , Bartosz Golaszewski Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai , Brian Norris , Krishna Chaitanya Chundru , Niklas Cassel , Alex Elder , Manivannan Sadhasivam , Chen-Yu Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=9481; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=4RZqS9C5omgsMD+6meE6/yDTZg9+e38zvxvu7kBnSY8=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpQVXom9V2sD9uL0evNrzSmHVYO68vB9b5L+b1r OIr2xTo2ZKJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaUFV6AAKCRBVnxHm/pHO 9WR8CACV9ioXJL2gvQG9MY5qC3NCLI2ENXaj++tsd52Z/IGkmJerU9KaiwLKp1LHrV4MayX53XE aFjZKYSYHyg09D8/CWaHEYr64fjWcwH0zvqWy2aQQNYFGfRrJlFsW187ArNI1FyUYpF1gwI7jbw ygiLuqoj7smnXwq1+AOyEadAtlWInOoPaAVduxky3xWMyn2GRW6UAfMz0yvHHsYE5QNIGyNAjSD i2IVi/3+8muE7lyrjcqiyPqzuOSMwmdb6IprF1waRlzxQ0v0QxbZ1BZ+1lJjZ479MgdhAhk/5H6 H4yZ6B27H0M7fnWersSQjpQgrdynB6RCna3BrYQG92DUehzl X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Authority-Analysis: v=2.4 cv=LrCfC3dc c=1 sm=1 tr=0 ts=69415608 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=wnJ2AIBC+6MZbTdryK78rQ==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=cm27Pg_UAAAA:8 a=Via3SN_SAYv5dIAeqUIA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-ORIG-GUID: Wqn1HgaBb0tb6OOwCWPk6kEAPecr4xEk X-Proofpoint-GUID: Wqn1HgaBb0tb6OOwCWPk6kEAPecr4xEk X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE2MDEwOSBTYWx0ZWRfX8dFnwhAMhNhk rIPwuYcViJYjrUr2oXEmToj87wq8eaLlY1aSEDOLWd2r2U+eIh/jKKOn7mpNHZ03nJs2URwULYI 2Gpl+C9Unc7rJTKYGoCH82vu1ekS28p0igUTz6ZJZdEW+sy1GU8yyZn6iOMY834NxhUGzt7Lq76 BxzsNqZOjvteLZZ9O0q9QuQAMwSDOHiz4r+scdQ9I2HFxGi0pBD9CZxUV9mYgz5an08L5HJVS96 lLwIbwu1kcQKHiBhuZ4ThghF+fi0vlCl2ArKNu2LhSqA5uuai6QPjAeopSUkB4uZMY8Tgqk9dCY WqN2fw0EIFU23bdhVgSExrSCQh37DjrrO4FGaszgwxpnLK06NR+CESP/KyccOf9VRfnqEv9UySB qIP69GxxcRensrrnV/zsfpwsJH1PoA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-16_02,2025-12-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512160109 Adopt the recently introduced pwrctrl APIs to create, power on, destroy, and power off pwrctrl devices. In qcom_pcie_host_init(), call pci_pwrctrl_create_devices() to create devices, then pci_pwrctrl_power_on_devices() to power them on, both after controller resource initialization. Once successful, deassert PERST# for all devices. In qcom_pcie_host_deinit(), call pci_pwrctrl_power_off_devices() after asserting PERST#. Note that pci_pwrctrl_destroy_devices() is not called here, as deinit is only invoked during system suspend where device destruction is unnecessary. If the driver becomes removable in future, pci_pwrctrl_destroy_devices() should be called in the remove() handler. At last, remove the old pwrctrl framework code from the PCI core, as the new APIs are now the sole consumer of pwrctrl functionality. And also do not power on the pwrctrl drivers during probe() as this is now handled by the APIs. Co-developed-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Tested-by: Chen-Yu Tsai Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 22 ++++++++++-- drivers/pci/probe.c | 59 ----------------------------= ---- drivers/pci/pwrctrl/core.c | 15 -------- drivers/pci/pwrctrl/pci-pwrctrl-pwrseq.c | 5 --- drivers/pci/pwrctrl/slot.c | 2 -- drivers/pci/remove.c | 20 ----------- 6 files changed, 20 insertions(+), 103 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 73032449d289..7c0c66480f12 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -1318,10 +1319,18 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *p= p) if (ret) goto err_deinit; =20 + ret =3D pci_pwrctrl_create_devices(pci->dev); + if (ret) + goto err_disable_phy; + + ret =3D pci_pwrctrl_power_on_devices(pci->dev); + if (ret) + goto err_pwrctrl_destroy; + if (pcie->cfg->ops->post_init) { ret =3D pcie->cfg->ops->post_init(pcie); if (ret) - goto err_disable_phy; + goto err_pwrctrl_power_off; } =20 qcom_ep_reset_deassert(pcie); @@ -1336,6 +1345,10 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) =20 err_assert_reset: qcom_ep_reset_assert(pcie); +err_pwrctrl_power_off: + pci_pwrctrl_power_off_devices(pci->dev); +err_pwrctrl_destroy: + pci_pwrctrl_destroy_devices(pci->dev); err_disable_phy: qcom_pcie_phy_power_off(pcie); err_deinit: @@ -1350,6 +1363,11 @@ static void qcom_pcie_host_deinit(struct dw_pcie_rp = *pp) struct qcom_pcie *pcie =3D to_qcom_pcie(pci); =20 qcom_ep_reset_assert(pcie); + /* + * No need to destroy pwrctrl devices as this function only gets called + * during system suspend as of now. + */ + pci_pwrctrl_power_off_devices(pci->dev); qcom_pcie_phy_power_off(pcie); pcie->cfg->ops->deinit(pcie); } @@ -2027,7 +2045,7 @@ static int qcom_pcie_probe(struct platform_device *pd= ev) =20 ret =3D dw_pcie_host_init(pp); if (ret) { - dev_err(dev, "cannot initialize host\n"); + dev_err_probe(dev, ret, "cannot initialize host\n"); goto err_phy_exit; } =20 diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 41183aed8f5d..6e7252404b58 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2563,56 +2563,6 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus,= int devfn, u32 *l, } EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); =20 -#if IS_ENABLED(CONFIG_PCI_PWRCTRL) -static struct platform_device *pci_pwrctrl_create_device(struct pci_bus *b= us, int devfn) -{ - struct pci_host_bridge *host =3D pci_find_host_bridge(bus); - struct platform_device *pdev; - struct device_node *np; - - np =3D of_pci_find_child_device(dev_of_node(&bus->dev), devfn); - if (!np) - return NULL; - - pdev =3D of_find_device_by_node(np); - if (pdev) { - put_device(&pdev->dev); - goto err_put_of_node; - } - - /* - * First check whether the pwrctrl device really needs to be created or - * not. This is decided based on at least one of the power supplies - * being defined in the devicetree node of the device. - */ - if (!of_pci_supply_present(np)) { - pr_debug("PCI/pwrctrl: Skipping OF node: %s\n", np->name); - goto err_put_of_node; - } - - /* Now create the pwrctrl device */ - pdev =3D of_platform_device_create(np, NULL, &host->dev); - if (!pdev) { - pr_err("PCI/pwrctrl: Failed to create pwrctrl device for node: %s\n", np= ->name); - goto err_put_of_node; - } - - of_node_put(np); - - return pdev; - -err_put_of_node: - of_node_put(np); - - return NULL; -} -#else -static struct platform_device *pci_pwrctrl_create_device(struct pci_bus *b= us, int devfn) -{ - return NULL; -} -#endif - /* * Read the config data for a PCI device, sanity-check it, * and fill in the dev structure. @@ -2622,15 +2572,6 @@ static struct pci_dev *pci_scan_device(struct pci_bu= s *bus, int devfn) struct pci_dev *dev; u32 l; =20 - /* - * Create pwrctrl device (if required) for the PCI device to handle the - * power state. If the pwrctrl device is created, then skip scanning - * further as the pwrctrl core will rescan the bus after powering on - * the device. - */ - if (pci_pwrctrl_create_device(bus, devfn)) - return NULL; - if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) return NULL; =20 diff --git a/drivers/pci/pwrctrl/core.c b/drivers/pci/pwrctrl/core.c index ebe1740b7c1c..4e2c41bc4ffe 100644 --- a/drivers/pci/pwrctrl/core.c +++ b/drivers/pci/pwrctrl/core.c @@ -45,16 +45,6 @@ static int pci_pwrctrl_notify(struct notifier_block *nb,= unsigned long action, return NOTIFY_DONE; } =20 -static void rescan_work_func(struct work_struct *work) -{ - struct pci_pwrctrl *pwrctrl =3D container_of(work, - struct pci_pwrctrl, work); - - pci_lock_rescan_remove(); - pci_rescan_bus(to_pci_host_bridge(pwrctrl->dev->parent)->bus); - pci_unlock_rescan_remove(); -} - /** * pci_pwrctrl_init() - Initialize the PCI power control context struct * @@ -64,7 +54,6 @@ static void rescan_work_func(struct work_struct *work) void pci_pwrctrl_init(struct pci_pwrctrl *pwrctrl, struct device *dev) { pwrctrl->dev =3D dev; - INIT_WORK(&pwrctrl->work, rescan_work_func); dev_set_drvdata(dev, pwrctrl); } EXPORT_SYMBOL_GPL(pci_pwrctrl_init); @@ -95,8 +84,6 @@ int pci_pwrctrl_device_set_ready(struct pci_pwrctrl *pwrc= trl) if (ret) return ret; =20 - schedule_work(&pwrctrl->work); - return 0; } EXPORT_SYMBOL_GPL(pci_pwrctrl_device_set_ready); @@ -109,8 +96,6 @@ EXPORT_SYMBOL_GPL(pci_pwrctrl_device_set_ready); */ void pci_pwrctrl_device_unset_ready(struct pci_pwrctrl *pwrctrl) { - cancel_work_sync(&pwrctrl->work); - /* * We don't have to delete the link here. Typically, this function * is only called when the power control device is being detached. If diff --git a/drivers/pci/pwrctrl/pci-pwrctrl-pwrseq.c b/drivers/pci/pwrctrl= /pci-pwrctrl-pwrseq.c index 0fb9038a1d18..7697a8a5cdde 100644 --- a/drivers/pci/pwrctrl/pci-pwrctrl-pwrseq.c +++ b/drivers/pci/pwrctrl/pci-pwrctrl-pwrseq.c @@ -101,11 +101,6 @@ static int pci_pwrctrl_pwrseq_probe(struct platform_de= vice *pdev) return dev_err_probe(dev, PTR_ERR(data->pwrseq), "Failed to get the power sequencer\n"); =20 - ret =3D pci_pwrctrl_pwrseq_power_on(&data->ctx); - if (ret) - return dev_err_probe(dev, ret, - "Failed to power-on the device\n"); - ret =3D devm_add_action_or_reset(dev, devm_pci_pwrctrl_pwrseq_power_off, data); if (ret) diff --git a/drivers/pci/pwrctrl/slot.c b/drivers/pci/pwrctrl/slot.c index 14701f65f1f2..888300aeefec 100644 --- a/drivers/pci/pwrctrl/slot.c +++ b/drivers/pci/pwrctrl/slot.c @@ -79,8 +79,6 @@ static int pci_pwrctrl_slot_probe(struct platform_device = *pdev) return dev_err_probe(dev, PTR_ERR(slot->clk), "Failed to enable slot clock\n"); =20 - pci_pwrctrl_slot_power_on(&slot->ctx); - slot->ctx.power_on =3D pci_pwrctrl_slot_power_on; slot->ctx.power_off =3D pci_pwrctrl_slot_power_off; =20 diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c index 417a9ea59117..e9d519993853 100644 --- a/drivers/pci/remove.c +++ b/drivers/pci/remove.c @@ -17,25 +17,6 @@ static void pci_free_resources(struct pci_dev *dev) } } =20 -static void pci_pwrctrl_unregister(struct device *dev) -{ - struct device_node *np; - struct platform_device *pdev; - - np =3D dev_of_node(dev); - if (!np) - return; - - pdev =3D of_find_device_by_node(np); - if (!pdev) - return; - - of_device_unregister(pdev); - put_device(&pdev->dev); - - of_node_clear_flag(np, OF_POPULATED); -} - static void pci_stop_dev(struct pci_dev *dev) { pci_pme_active(dev, false); @@ -73,7 +54,6 @@ static void pci_destroy_dev(struct pci_dev *dev) pci_ide_destroy(dev); pcie_aspm_exit_link_state(dev); pci_bridge_d3_update(dev); - pci_pwrctrl_unregister(&dev->dev); pci_free_resources(dev); put_device(&dev->dev); } --=20 2.48.1