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Tue, 16 Dec 2025 17:04:43 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A1FA120040; Tue, 16 Dec 2025 17:04:43 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7C4272004D; Tue, 16 Dec 2025 17:04:43 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 16 Dec 2025 17:04:43 +0000 (GMT) From: Gerd Bayer Date: Tue, 16 Dec 2025 18:04:42 +0100 Subject: [PATCH v2 1/2] PCI: AtomicOps: Define valid root port capabilities Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251216-fix_pciatops-v2-1-d013e9b7e2ee@linux.ibm.com> References: <20251216-fix_pciatops-v2-0-d013e9b7e2ee@linux.ibm.com> In-Reply-To: <20251216-fix_pciatops-v2-0-d013e9b7e2ee@linux.ibm.com> To: Bjorn Helgaas , Jay Cornwall , Felix Kuehling Cc: Niklas Schnelle , Alexander Schmidt , linux-s390@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Gerd Bayer , Leon Romanovsky X-Mailer: b4 0.14.2 X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEzMDAwMSBTYWx0ZWRfX1px1MSWgyMav nITTAW9pCiGaebfZyXa8jSDmasH+tEHPsBhFYDj2iwlRij53yvn9BgA07+yE0s4ni5if1jjIEzw XxgwLyGQ12sZ/cH5RSoac76xSO6aYs6cXaeJ0FZGpwq0kW7ac0+Lj3D+X35ldR5Plr1X98rl+Tz mDjghx9whuTDAftqr4hPidNAUn7lLBfkW+cFf0Bhp4+fQE0ey6X05paJHTATZDoyAc7BWUz4cJs UhKO4nuvTYhx0jbO6xnHNFiZDA3x2Ih2peHrWe0/cBQnMnRMNoZT3aBVmbqwUzWcxOD+WNuItQ+ YJuvBYQyrwccrrY9mo5El870ewukFEuE21JNSFEwUyyqCRAa4PWomspqeuTdQKvwJNnm4KeLur5 1z5JyhY+AoTyDSoQynzpkVDk5+H9GQ== X-Proofpoint-GUID: SPRw0oCoki-lCv9OchZmtUf4GfT4qr0h X-Proofpoint-ORIG-GUID: E39EOfgEmE-bMG2ENPsvqJ4p72mqzusm X-Authority-Analysis: v=2.4 cv=Kq5AGGWN c=1 sm=1 tr=0 ts=69419130 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=8GgRulezAQhDBDp5LV8A:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-16_02,2025-12-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 impostorscore=0 clxscore=1011 spamscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512130001 Provide the two combinations of Atomic Op Completion size attributes that a root port may support per PCIe Spec 7.0 section 6.15.3.1. - besides the trivial "No support" - as two new defines. Change documentation of pci_enable_atomic_ops_to_root() that these are the only ones that should be used. Also, spell out that all requested capabilities need to be supported at the root port for enable to succeed. Also emphasize that on success, this sets AtomicOpsCtl:ReqEn to 1, and leaves it untouched in case of failure. Suggested-by: Leon Romanovsky Signed-off-by: Gerd Bayer --- drivers/pci/pci.c | 13 +++++++------ include/uapi/linux/pci_regs.h | 8 ++++++++ 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 13dbb405dc31f8054afa090a2d14acf16845f587..d2261ac964316f3fc3efc4d5b30= cf821ac46d75d 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3661,15 +3661,16 @@ void pci_acs_init(struct pci_dev *dev) /** * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port * @dev: the PCI device - * @cap_mask: mask of desired AtomicOp sizes, including one or more of: - * PCI_EXP_DEVCAP2_ATOMIC_COMP32 - * PCI_EXP_DEVCAP2_ATOMIC_COMP64 - * PCI_EXP_DEVCAP2_ATOMIC_COMP128 + * @cap_mask: root port must support combinations of AtomicOp sizes + * PCI_EXP_ROOT_PORT_ATOMIC_BASE + * PCI_EXP_ROOT_PORT_ATOMIC_FULL * * Return 0 if all upstream bridges support AtomicOp routing, egress * blocking is disabled on all upstream ports, and the root port supports - * the requested completion capabilities (32-bit, 64-bit and/or 128-bit - * AtomicOp completion), or negative otherwise. + * all the requested completion capabilities (BASE: 32-bit, 64-bit or + * FULL: 32/64- and 128-bit AtomicOp completion). In that case enable the + * device to send AtomicOp requests. Otherwise, return negative and leave + * the enablement in the PCI config space untouched. */ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) { diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 3add74ae259483bab76e7552cb28bd9c9ef0b30c..e4d91c379416841fcf2090043b2= b4784d69538a0 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -664,6 +664,14 @@ #define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x00000080 /* 32b AtomicOp completi= on */ #define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completi= on */ #define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp comple= tion */ +/* PCIe spec 7.0 6.15.3.1: Root ports may support one of 2 sets of Atomic = Ops */ +#define PCI_EXP_ROOT_PORT_ATOMIC_BASE \ + (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | \ + PCI_EXP_DEVCAP2_ATOMIC_COMP64) +#define PCI_EXP_ROOT_PORT_ATOMIC_FULL \ + (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | \ + PCI_EXP_DEVCAP2_ATOMIC_COMP64 | \ + PCI_EXP_DEVCAP2_ATOMIC_COMP128) #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ #define PCI_EXP_DEVCAP2_TPH_COMP_MASK 0x00003000 /* TPH completer support= */ #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ --=20 2.51.0 From nobody Thu Dec 18 23:24:32 2025 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AEE2314D2C; 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Tue, 16 Dec 2025 17:04:43 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CD00B20040; Tue, 16 Dec 2025 17:04:43 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A66042004E; Tue, 16 Dec 2025 17:04:43 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.87.85.9]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 16 Dec 2025 17:04:43 +0000 (GMT) From: Gerd Bayer Date: Tue, 16 Dec 2025 18:04:43 +0100 Subject: [PATCH v2 2/2] PCI: AtomicOps: Fix logic in enable function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251216-fix_pciatops-v2-2-d013e9b7e2ee@linux.ibm.com> References: <20251216-fix_pciatops-v2-0-d013e9b7e2ee@linux.ibm.com> In-Reply-To: <20251216-fix_pciatops-v2-0-d013e9b7e2ee@linux.ibm.com> To: Bjorn Helgaas , Jay Cornwall , Felix Kuehling Cc: Niklas Schnelle , Alexander Schmidt , linux-s390@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Gerd Bayer , stable@vger.kernel.org X-Mailer: b4 0.14.2 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: XIZgrjMmIy5IgMHp3x1QqXOEnpTQajSx X-Authority-Analysis: v=2.4 cv=CLgnnBrD c=1 sm=1 tr=0 ts=69419130 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=VwQbUJbxAAAA:8 a=ud980_RLCRqylQVSWKAA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-GUID: CO2Bokk8N1kGnRsN3C-TFQffGrqzY7pI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEzMDAwOSBTYWx0ZWRfX7ya0nj8HlcZC +ZqvTPg1oFASz2bxIbspg1VqrYKXkdQ6Kglk1gIp9RcZecOqnpdYlSAtKrNZVzcLhO0gkVGyYzY SRU5YIc8eXGF8qjlg7VKb7IvG86J+/d6/9R/tH473AHxvj5W4E2dV3RwBAmNxh5L2L3X9egyWt7 EP1CguCQn5DisIWlekuyE0NiNe39kI01K3/3AKVRprkQp2IyNkL9WXKvns8fqktInQRXVc4I+mP Mas8wp2Al0IkznwsoChTOvRxmJD9E7DVIQvYYz245GTQPa/gn5plFwQ/zNFhy/8gVQo1Fgiq5ul 0WHXqiwkjZIQePPqbK0LL5ofw0gTIFG352JXNeVYQlFa3orhAJEsEaQuICOhqSa73gpbR+IiQyC E8uZR6LARlhRVea4qnDcl6Z1YYla3A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-16_02,2025-12-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 suspectscore=0 phishscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512130009 Move the check for root port requirements past the loop within pci_enable_atomic_ops_to_root() that checks on potential switch (up- and downstream) ports. Inside the loop traversing the PCI tree upwards, prepend the switch case to validate the routing capability on any port with a fallthrough-case that does the additional check for Atomic Ops not being blocked on upstream ports. Do not enable Atomic Op Requests if nothing can be learned about how the device is attached - e.g. if it is on an "isolated" bus, as in s390. Reported-by: Alexander Schmidt Cc: stable@vger.kernel.org Fixes: 430a23689dea ("PCI: Add pci_enable_atomic_ops_to_root()") Signed-off-by: Gerd Bayer --- drivers/pci/pci.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d2261ac964316f3fc3efc4d5b30cf821ac46d75d..5d25d42eece1bbaf16197068d7b= 6206937e9c3a0 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3675,7 +3675,7 @@ void pci_acs_init(struct pci_dev *dev) int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) { struct pci_bus *bus =3D dev->bus; - struct pci_dev *bridge; + struct pci_dev *bridge =3D NULL; u32 cap, ctl2; =20 /* @@ -3713,29 +3713,27 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *d= ev, u32 cap_mask) switch (pci_pcie_type(bridge)) { /* Ensure switch ports support AtomicOp routing */ case PCI_EXP_TYPE_UPSTREAM: - case PCI_EXP_TYPE_DOWNSTREAM: - if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) - return -EINVAL; - break; - - /* Ensure root port supports all the sizes we care about */ - case PCI_EXP_TYPE_ROOT_PORT: - if ((cap & cap_mask) !=3D cap_mask) - return -EINVAL; - break; - } - - /* Ensure upstream ports don't block AtomicOps on egress */ - if (pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_UPSTREAM) { + /* Upstream ports must not block AtomicOps on egress */ pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl2); if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) return -EINVAL; + fallthrough; + /* All switch ports need to route AtomicOps */ + case PCI_EXP_TYPE_DOWNSTREAM: + if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) + return -EINVAL; + break; } - bus =3D bus->parent; } =20 + /* Finally, last bridge must be root port and support requested sizes */ + if ((!bridge) || + (pci_pcie_type(bridge) !=3D PCI_EXP_TYPE_ROOT_PORT) || + ((cap & cap_mask) !=3D cap_mask)) + return -EINVAL; + pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_ATOMIC_REQ); return 0; --=20 2.51.0